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Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
2 * U-boot - Configuration file for BF533 STAMP board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_STAMP_H__
6#define __CONFIG_BF533_STAMP_H__
Aubrey.Li3f0606a2007-03-09 13:38:44 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey.Li3f0606a2007-03-09 13:38:44 +080010
Aubrey.Li3f0606a2007-03-09 13:38:44 +080011/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080013 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040014#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
15
16
17/*
18 * Clock Settings
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
21 */
22/* CONFIG_CLKIN_HZ is any value in Hz */
23#define CONFIG_CLKIN_HZ 11059200
24/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
25/* 1 = CLKIN / 2 */
26#define CONFIG_CLKIN_HALF 0
27/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
28/* 1 = bypass PLL */
29#define CONFIG_PLL_BYPASS 0
30/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31/* Values can range from 0-63 (where 0 means 64) */
Mike Frysinger9f64ba22008-10-12 23:49:13 -040032#define CONFIG_VCO_MULT 45
Mike Frysingercf6f4692008-06-01 09:09:48 -040033/* CCLK_DIV controls the core clock divider */
34/* Values can be 1, 2, 4, or 8 ONLY */
35#define CONFIG_CCLK_DIV 1
36/* SCLK_DIV controls the system clock divider */
37/* Values can range from 1-15 */
Mike Frysingerbaf35702009-07-10 10:42:06 -040038#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
Mike Frysingercf6f4692008-06-01 09:09:48 -040039
40
41/*
42 * Memory Settings
43 */
44#define CONFIG_MEM_ADD_WDTH 11
45#define CONFIG_MEM_SIZE 128
46
47#define CONFIG_EBIU_SDRRC_VAL 0x268
48#define CONFIG_EBIU_SDGCTL_VAL 0x911109
49
50#define CONFIG_EBIU_AMGCTL_VAL 0xFF
51#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
52#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
53
54#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
55#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
56
57
58/*
59 * Network Settings
60 */
61#define ADI_CMDS_NETWORK 1
Ben Warren7194ab82009-10-04 22:37:03 -070062#define CONFIG_NET_MULTI
63#define CONFIG_SMC91111 1
Aubrey Li8db13d62007-03-10 23:49:29 +080064#define CONFIG_SMC91111_BASE 0x20300300
Mike Frysingercf6f4692008-06-01 09:09:48 -040065#define SMC91111_EEPROM_INIT() \
66 do { \
Ben Warren7194ab82009-10-04 22:37:03 -070067 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
68 bfin_write_FIO_FLAG_C(PF1); \
69 bfin_write_FIO_FLAG_S(PF0); \
Mike Frysingercf6f4692008-06-01 09:09:48 -040070 SSYNC(); \
71 } while (0)
72#define CONFIG_HOSTNAME bf533-stamp
73/* Uncomment next line to use fixed MAC address */
74/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +080075
Aubrey.Li3f0606a2007-03-09 13:38:44 +080076
77/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040078 * Flash Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080079 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040080#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040082#define CONFIG_SYS_FLASH_CFI
83#define CONFIG_SYS_FLASH_CFI_AMD_RESET
84#define CONFIG_SYS_MAX_FLASH_BANKS 1
85#define CONFIG_SYS_MAX_FLASH_SECT 67
Aubrey.Li3f0606a2007-03-09 13:38:44 +080086
Mike Frysingercf6f4692008-06-01 09:09:48 -040087
88/*
89 * SPI Settings
90 */
91#define CONFIG_BFIN_SPI
92#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040093#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040094#define CONFIG_SPI_FLASH
Mike Frysingerf4532202010-09-19 16:26:55 -040095#define CONFIG_SPI_FLASH_ALL
Mike Frysingercf6f4692008-06-01 09:09:48 -040096
97
98/*
99 * Env Storage Settings
100 */
Mike Frysinger9171fc82008-03-30 15:46:13 -0400101#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -0400102#define CONFIG_ENV_IS_IN_SPI_FLASH
Vivi Libc43a8d2009-06-12 10:53:22 +0000103#define CONFIG_ENV_OFFSET 0x10000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400104#define CONFIG_ENV_SIZE 0x2000
Vivi Libc43a8d2009-06-12 10:53:22 +0000105#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger9171fc82008-03-30 15:46:13 -0400106#else
Mike Frysingercf6f4692008-06-01 09:09:48 -0400107#define CONFIG_ENV_IS_IN_FLASH
108#define CONFIG_ENV_OFFSET 0x4000
109#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
110#define CONFIG_ENV_SIZE 0x2000
111#define CONFIG_ENV_SECT_SIZE 0x2000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800112#endif
Mike Frysingercf6f4692008-06-01 09:09:48 -0400113#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
114#define ENV_IS_EMBEDDED
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800115#else
Mike Frysinger76d82182009-07-21 22:17:36 -0400116#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800117#endif
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400118#ifdef ENV_IS_EMBEDDED
119/* WARNING - the following is hand-optimized to fit within
120 * the sector before the environment sector. If it throws
121 * an error during compilation remove an object here to get
122 * it linked after the configuration sector.
123 */
124# define LDS_BOARD_TEXT \
Peter Tyserc6fb83d2010-04-12 22:28:13 -0500125 arch/blackfin/cpu/traps.o (.text .text.*); \
126 arch/blackfin/cpu/interrupt.o (.text .text.*); \
127 arch/blackfin/cpu/serial.o (.text .text.*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400128 common/dlmalloc.o (.text .text.*); \
Peter Tyser78acc472010-04-12 22:28:05 -0500129 lib/crc32.o (.text .text.*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400130 . = DEFINED(env_offset) ? env_offset : .; \
131 common/env_embedded.o (.text .text.*);
132#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800133
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800134
Jon Loeligerba2351f2007-07-04 22:31:49 -0500135/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400136 * I2C Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800137 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400138#define CONFIG_SOFT_I2C
Mike Frysingerbeb60e72010-06-08 16:22:44 -0400139#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
140#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
Mike Frysingercf6f4692008-06-01 09:09:48 -0400141
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800142
143/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400144 * Compact Flash / IDE / ATA Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800145 */
146
147/* Enabled below option for CF support */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400148/* #define CONFIG_STAMP_CF */
149#if defined(CONFIG_STAMP_CF)
150#define CONFIG_MISC_INIT_R
Aubrey Li8db13d62007-03-10 23:49:29 +0800151#define CONFIG_DOS_PARTITION 1
Aubrey Li8db13d62007-03-10 23:49:29 +0800152#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
153#undef CONFIG_IDE_LED /* no led for ide supported */
154#undef CONFIG_IDE_RESET /* no reset for ide supported */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800155
Mike Frysingercf6f4692008-06-01 09:09:48 -0400156#define CONFIG_SYS_IDE_MAXBUS 1
157#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
160#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800161
Mike Frysingercf6f4692008-06-01 09:09:48 -0400162#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
163#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
164#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_ATA_STRIDE 2
Mike Frysingercf6f4692008-06-01 09:09:48 -0400167
168#undef CONFIG_EBIU_AMBCTL1_VAL
169#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800170#endif
171
Mike Frysingercf6f4692008-06-01 09:09:48 -0400172
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800173/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400174 * Misc Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800175 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400176#define CONFIG_RTC_BFIN
177#define CONFIG_UART_CONSOLE 0
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800178
Mike Frysingercf6f4692008-06-01 09:09:48 -0400179/* FLASH/ETHERNET uses the same async bank */
180#define SHARED_RESOURCES 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800181
Mike Frysinger23fd9592008-10-11 22:40:22 -0400182/* define to enable boot progress via leds */
183/* #define CONFIG_SHOW_BOOT_PROGRESS */
184
185/* define to enable run status via led */
186/* #define CONFIG_STATUS_LED */
187#ifdef CONFIG_STATUS_LED
Mike Frysingera84774f2010-06-02 05:12:11 -0400188#define CONFIG_GPIO_LED
Mike Frysinger23fd9592008-10-11 22:40:22 -0400189#define CONFIG_BOARD_SPECIFIC_LED
Mike Frysingera84774f2010-06-02 05:12:11 -0400190/* use LED0 to indicate booting/alive */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400191#define STATUS_LED_BOOT 0
Mike Frysingera84774f2010-06-02 05:12:11 -0400192#define STATUS_LED_BIT GPIO_PF2
Mike Frysinger23fd9592008-10-11 22:40:22 -0400193#define STATUS_LED_STATE STATUS_LED_ON
194#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
Mike Frysingera84774f2010-06-02 05:12:11 -0400195/* use LED1 to indicate crash */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400196#define STATUS_LED_CRASH 1
Mike Frysingera84774f2010-06-02 05:12:11 -0400197#define STATUS_LED_BIT1 GPIO_PF3
Mike Frysinger23fd9592008-10-11 22:40:22 -0400198#define STATUS_LED_STATE1 STATUS_LED_ON
199#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
Mike Frysingera84774f2010-06-02 05:12:11 -0400200/* #define STATUS_LED_BIT2 GPIO_PF4 */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400201#endif
202
Mike Frysingercf6f4692008-06-01 09:09:48 -0400203/* define to enable splash screen support */
204/* #define CONFIG_VIDEO */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800205
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800206
207/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400208 * Pull in common ADI header for remaining command/environment setup
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800209 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400210#include <configs/bfin_adi_common.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -0400211
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800212#endif