blob: 911c906492b56c1392dc2c63db1f38a75ff15cec [file] [log] [blame]
Dan Malek35171dc2007-01-05 09:15:34 +01001/*
2 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
3 * Dan Malek <dan@embeddedalley.com>
4 * Copied from STx GP3.
5 * Updates for Silicon Tx GP3 SSA board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/* mpc8560ads board configuration file */
30/* please refer to doc/README.mpc85xx for more info */
31/* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
41#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
42#define CONFIG_CPM2 1 /* has CPM2 */
43#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
Kumar Galaf0600542008-06-11 00:44:10 -050044#define CONFIG_MPC8560 1
Dan Malek35171dc2007-01-05 09:15:34 +010045
Wolfgang Denkf1152f82007-07-06 02:50:19 +020046#define CONFIG_PCI /* PCI ethernet support */
47#define CONFIG_TSEC_ENET /* tsec ethernet support*/
48#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
Dan Malek35171dc2007-01-05 09:15:34 +010049#define CONFIG_ENV_OVERWRITE
Dan Malek35171dc2007-01-05 09:15:34 +010050
Kumar Gala572b13a2008-01-16 09:11:53 -060051#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Dan Malek35171dc2007-01-05 09:15:34 +010052
53/* sysclk for MPC85xx
54 */
55
Wolfgang Denkf1152f82007-07-06 02:50:19 +020056#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
Dan Malek35171dc2007-01-05 09:15:34 +010057
58/* Blinkin' LEDs for Robert :-)
59*/
60#define CONFIG_SHOW_ACTIVITY 1
61
62/*
63 * These can be toggled for performance analysis, otherwise use default.
64 */
Wolfgang Denkf1152f82007-07-06 02:50:19 +020065#define CONFIG_L2_CACHE /* toggle L2 cache */
66#define CONFIG_BTB /* toggle branch predition */
Dan Malek35171dc2007-01-05 09:15:34 +010067
Wolfgang Denk53677ef2008-05-20 16:00:29 +020068#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Dan Malek35171dc2007-01-05 09:15:34 +010069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
71#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
72#define CONFIG_SYS_MEMTEST_END 0x00400000
Dan Malek35171dc2007-01-05 09:15:34 +010073
74
Wolfgang Denkf1152f82007-07-06 02:50:19 +020075/* Localbus connector. There are many options that can be
Dan Malek35171dc2007-01-05 09:15:34 +010076 * connected here, including sdram or lots of flash.
77 * This address, however, is used to configure a 256M local bus
78 * window that includes the Config latch below.
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
81#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */
Dan Malek35171dc2007-01-05 09:15:34 +010082
83/* There are various flash options used, we configure for the largest,
84 * which is 64Mbytes. The CFI works fine and will discover the proper
85 * sizes.
86 */
Wolfgang Denkee152982007-05-31 17:20:09 +020087#ifdef CONFIG_STXSSA_4M
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
Wolfgang Denkee152982007-05-31 17:20:09 +020089#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
Wolfgang Denkee152982007-05-31 17:20:09 +020091#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */
93#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7)
Dan Malek35171dc2007-01-05 09:15:34 +010094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020096#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
98#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
99#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
Dan Malek35171dc2007-01-05 09:15:34 +0100100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Dan Malek35171dc2007-01-05 09:15:34 +0100102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_FLASH_PROTECTION
Dan Malek35171dc2007-01-05 09:15:34 +0100104
105/* The configuration latch is Chip Select 1.
106 * It's an 8-bit latch in the lower 8 bits of the word.
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
109#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
110#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
Dan Malek35171dc2007-01-05 09:15:34 +0100111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Dan Malek35171dc2007-01-05 09:15:34 +0100113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
115#define CONFIG_SYS_RAMBOOT
Dan Malek35171dc2007-01-05 09:15:34 +0100116#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#undef CONFIG_SYS_RAMBOOT
Dan Malek35171dc2007-01-05 09:15:34 +0100118#endif
119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#ifdef CONFIG_SYS_RAMBOOT
121#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
Dan Malek35171dc2007-01-05 09:15:34 +0100122#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Dan Malek35171dc2007-01-05 09:15:34 +0100124#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
126#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
127#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Dan Malek35171dc2007-01-05 09:15:34 +0100128
Kumar Gala0e7927d2008-08-27 01:04:07 -0500129/* DDR Setup */
130#define CONFIG_FSL_DDR1
131#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
132#define CONFIG_DDR_SPD
133#undef CONFIG_FSL_DDR_INTERACTIVE
Dan Malek35171dc2007-01-05 09:15:34 +0100134
Kumar Gala0e7927d2008-08-27 01:04:07 -0500135#undef CONFIG_DDR_ECC /* only for ECC DDR module */
136#undef CONFIG_DDR_DLL /* possible DLL fix needed */
137#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
Dan Malek35171dc2007-01-05 09:15:34 +0100138
Kumar Gala0e7927d2008-08-27 01:04:07 -0500139#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
142#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Dan Malek35171dc2007-01-05 09:15:34 +0100143
Kumar Gala0e7927d2008-08-27 01:04:07 -0500144#define CONFIG_NUM_DDR_CONTROLLERS 1
145#define CONFIG_DIMM_SLOTS_PER_CTLR 1
146#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
147
148/* I2C addresses of SPD EEPROMs */
149#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
Dan Malek35171dc2007-01-05 09:15:34 +0100150
151#undef CONFIG_CLOCKS_IN_MHZ
152
153/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
155#define CONFIG_SYS_OR2_PRELIM 0xfc006901
156#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
157#define CONFIG_SYS_LBC_LBCR 0x00000000
158#define CONFIG_SYS_LBC_LSRT 0x20000000
159#define CONFIG_SYS_LBC_MRTPR 0x20000000
160#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
161#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
162#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
163#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
164#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
Dan Malek35171dc2007-01-05 09:15:34 +0100165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_INIT_RAM_LOCK 1
167#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
168#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
Dan Malek35171dc2007-01-05 09:15:34 +0100169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
171#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
172#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Dan Malek35171dc2007-01-05 09:15:34 +0100173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
175#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dan Malek35171dc2007-01-05 09:15:34 +0100176
177/* Serial Port */
178#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_NS16550
180#define CONFIG_SYS_NS16550_SERIAL
181#define CONFIG_SYS_NS16550_REG_SIZE 1
182#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dan Malek35171dc2007-01-05 09:15:34 +0100183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_BAUDRATE_TABLE \
Dan Malek35171dc2007-01-05 09:15:34 +0100185 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
188#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Dan Malek35171dc2007-01-05 09:15:34 +0100189
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200190#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500191#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
193#ifdef CONFIG_SYS_HUSH_PARSER
194#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Dan Malek35171dc2007-01-05 09:15:34 +0100195#endif
196
Wolfgang Denke1893812007-10-12 15:49:39 +0200197/*
198 * I2C
199 */
Dan Malek35171dc2007-01-05 09:15:34 +0100200#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200201#define CONFIG_HARD_I2C /* I2C with hardware support*/
Dan Malek35171dc2007-01-05 09:15:34 +0100202#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
204#define CONFIG_SYS_I2C_SLAVE 0x7F
205#undef CONFIG_SYS_I2C_NOPROBES
206#define CONFIG_SYS_I2C_OFFSET 0x3000
Dan Malek35171dc2007-01-05 09:15:34 +0100207
Wolfgang Denke1893812007-10-12 15:49:39 +0200208/* I2C RTC */
209#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Wolfgang Denke1893812007-10-12 15:49:39 +0200211
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200212/* I2C EEPROM. AT24C32, we keep our environment in here.
Dan Malek35171dc2007-01-05 09:15:34 +0100213*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */
215#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
216#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
217#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Dan Malek35171dc2007-01-05 09:15:34 +0100218
219/*
220 * Standard 8555 PCI mapping.
221 * Addresses are mapped 1-1.
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
224#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
225#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
226#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
227#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
228#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Dan Malek35171dc2007-01-05 09:15:34 +0100229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
231#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
232#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
233#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
234#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
235#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Dan Malek35171dc2007-01-05 09:15:34 +0100236
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200237#if defined(CONFIG_PCI) /* PCI Ethernet card */
Grzegorz Bernacki38ad82d2007-09-11 15:42:11 +0200238#define CONFIG_MPC85XX_PCI2 1
Dan Malek35171dc2007-01-05 09:15:34 +0100239#define CONFIG_NET_MULTI
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200240#define CONFIG_PCI_PNP /* do pci plug-and-play */
Dan Malek35171dc2007-01-05 09:15:34 +0100241
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200242#define CONFIG_EEPRO100
243#define CONFIG_TULIP
Dan Malek35171dc2007-01-05 09:15:34 +0100244
245#if !defined(CONFIG_PCI_PNP)
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200246 #define PCI_ENET0_IOADDR 0xe0000000
247 #define PCI_ENET0_MEMADDR 0xe0000000
248 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Dan Malek35171dc2007-01-05 09:15:34 +0100249#endif
250
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200251#define CONFIG_PCI_SCAN_SHOW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Dan Malek35171dc2007-01-05 09:15:34 +0100253
254#endif /* CONFIG_PCI */
255
256#if defined(CONFIG_TSEC_ENET)
257
258#ifndef CONFIG_NET_MULTI
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200259#define CONFIG_NET_MULTI 1
Dan Malek35171dc2007-01-05 09:15:34 +0100260#endif
261
262#define CONFIG_MII 1 /* MII PHY management */
263
Kim Phillips255a35772007-05-16 16:52:19 -0500264#define CONFIG_TSEC1 1
265#define CONFIG_TSEC1_NAME "TSEC0"
266#define CONFIG_TSEC2 1
267#define CONFIG_TSEC2_NAME "TSEC1"
Dan Malek35171dc2007-01-05 09:15:34 +0100268
269#define TSEC1_PHY_ADDR 2
270#define TSEC2_PHY_ADDR 4
271#define TSEC1_PHYIDX 0
272#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500273#define TSEC1_FLAGS TSEC_GIGABIT
274#define TSEC2_FLAGS TSEC_GIGABIT
Dan Malek35171dc2007-01-05 09:15:34 +0100275#define CONFIG_ETHPRIME "TSEC0"
276
277#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
278
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200279#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
280#undef CONFIG_ETHER_NONE /* define if ether on something else */
281#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
Dan Malek35171dc2007-01-05 09:15:34 +0100282
283#if (CONFIG_ETHER_INDEX == 2)
284 /*
285 * - Rx-CLK is CLK13
286 * - Tx-CLK is CLK14
287 * - Select bus for bd/buffers
288 * - Full duplex
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
291 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
292 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
Dan Malek35171dc2007-01-05 09:15:34 +0100293#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
Dan Malek35171dc2007-01-05 09:15:34 +0100295#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296 #define CONFIG_SYS_FCC_PSMR 0
Dan Malek35171dc2007-01-05 09:15:34 +0100297#endif
298 #define FETH2_RST 0x01
299#elif (CONFIG_ETHER_INDEX == 3)
300 /* need more definitions here for FE3 */
301 #define FETH3_RST 0x80
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200302#endif /* CONFIG_ETHER_INDEX */
Dan Malek35171dc2007-01-05 09:15:34 +0100303
304/* MDIO is done through the TSEC0 control.
305*/
306#define CONFIG_MII /* MII PHY management */
307#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
308
309#endif
310
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200311/* Environment - default config is in flash, see below */
312#if 0 /* in EEPROM */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200313# define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200314# define CONFIG_ENV_OFFSET 0
315# define CONFIG_ENV_SIZE 2048
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200316#else /* in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200317# define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denkee152982007-05-31 17:20:09 +0200318# ifdef CONFIG_STXSSA_4M
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200319# define CONFIG_ENV_SECT_SIZE 0x20000
Wolfgang Denkee152982007-05-31 17:20:09 +0200320# else /* default configuration - 64 MiB flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200321# define CONFIG_ENV_SECT_SIZE 0x40000
Wolfgang Denkee152982007-05-31 17:20:09 +0200322# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200324# define CONFIG_ENV_SIZE 0x4000
325# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
326# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Dan Malek35171dc2007-01-05 09:15:34 +0100327#endif
328
Dan Malek35171dc2007-01-05 09:15:34 +0100329#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dan Malek35171dc2007-01-05 09:15:34 +0100331
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200332#define CONFIG_TIMESTAMP /* Print image info with ts */
333
Jon Loeliger2835e512007-06-13 13:22:08 -0500334
335/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500336 * BOOTP options
337 */
338#define CONFIG_BOOTP_BOOTFILESIZE
339#define CONFIG_BOOTP_BOOTPATH
340#define CONFIG_BOOTP_GATEWAY
341#define CONFIG_BOOTP_HOSTNAME
342
343
344/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500345 * Command line configuration.
346 */
347#include <config_cmd_default.h>
348
Wolfgang Denke1893812007-10-12 15:49:39 +0200349#define CONFIG_CMD_DATE
350#define CONFIG_CMD_DHCP
351#define CONFIG_CMD_EEPROM
Jon Loeliger2835e512007-06-13 13:22:08 -0500352#define CONFIG_CMD_I2C
Wolfgang Denke1893812007-10-12 15:49:39 +0200353#define CONFIG_CMD_NFS
354#define CONFIG_CMD_PING
355#define CONFIG_CMD_SNTP
Becky Bruce199e2622010-06-17 11:37:25 -0500356#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500357
358#if defined(CONFIG_PCI)
359 #define CONFIG_CMD_PCI
Dan Malek35171dc2007-01-05 09:15:34 +0100360#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500361
362#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
363 #define CONFIG_CMD_MII
364#endif
365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500367 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500368 #undef CONFIG_CMD_LOADS
369#else
370 #define CONFIG_CMD_ELF
371#endif
372
Dan Malek35171dc2007-01-05 09:15:34 +0100373
374#undef CONFIG_WATCHDOG /* watchdog disabled */
375
376/*
377 * Miscellaneous configurable options
378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_LONGHELP /* undef to save memory */
380#define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */
Jon Loeligeref0df522007-07-04 22:31:07 -0500381#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dan Malek35171dc2007-01-05 09:15:34 +0100383#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dan Malek35171dc2007-01-05 09:15:34 +0100385#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
387#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
388#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
389#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
390#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Dan Malek35171dc2007-01-05 09:15:34 +0100391
392/*
393 * For booting Linux, the board info and command line data
394 * have to be in the first 8 MB of memory, since this is
395 * the maximum mapped by the Linux kernel during initialization.
396 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Dan Malek35171dc2007-01-05 09:15:34 +0100398
Dan Malek35171dc2007-01-05 09:15:34 +0100399/*
400 * Internal Definitions
401 *
402 * Boot Flags
403 */
404#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
405#define BOOTFLAG_WARM 0x02 /* Software reboot */
406
Jon Loeligeref0df522007-07-04 22:31:07 -0500407#if defined(CONFIG_CMD_KGDB)
Dan Malek35171dc2007-01-05 09:15:34 +0100408#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
409#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
410#endif
411
412/*Note: change below for your network setting!!! */
413#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500414#define CONFIG_HAS_ETH0
Dan Malek35171dc2007-01-05 09:15:34 +0100415#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
416#define CONFIG_HAS_ETH1
417#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
418#define CONFIG_HAS_ETH2
419#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
420#endif
421
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200422/*
423 * Environment in EEPROM is compatible with different flash sector sizes,
424 * but only little space is available, so we use a very simple setup.
425 * With environment in flash, we use a more powerful default configuration.
426 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200427#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200428
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200429#define CONFIG_BAUDRATE 38400
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200430
431#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
432#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
433#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200434#define CONFIG_SERVERIP 192.168.85.1
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200435#define CONFIG_IPADDR 192.168.85.60
Dan Malek35171dc2007-01-05 09:15:34 +0100436#define CONFIG_GATEWAYIP 192.168.85.1
437#define CONFIG_NETMASK 255.255.255.0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200438#define CONFIG_HOSTNAME STX_SSA
439#define CONFIG_ROOTPATH /gppproot
440#define CONFIG_BOOTFILE uImage
Dan Malek35171dc2007-01-05 09:15:34 +0100441#define CONFIG_LOADADDR 0x1000000
442
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200443#else /* ENV IS IN FLASH -- use a full-blown envionment */
444
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200445#define CONFIG_BAUDRATE 115200
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200446
447#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
448
449#define CONFIG_PREBOOT "echo;" \
450 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
451 "echo"
452
453#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
454
455#define CONFIG_EXTRA_ENV_SETTINGS \
456 "hostname=gp3ssa\0" \
457 "bootfile=/tftpboot/gp3ssa/uImage\0" \
458 "loadaddr=400000\0" \
459 "netdev=eth0\0" \
460 "consdev=ttyS1\0" \
461 "nfsargs=setenv bootargs root=/dev/nfs rw " \
462 "nfsroot=$serverip:$rootpath\0" \
463 "ramargs=setenv bootargs root=/dev/ram rw\0" \
464 "addip=setenv bootargs $bootargs " \
465 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
466 ":$hostname:$netdev:off panic=1\0" \
467 "addcons=setenv bootargs $bootargs " \
468 "console=$consdev,$baudrate\0" \
469 "flash_nfs=run nfsargs addip addcons;" \
470 "bootm $kernel_addr\0" \
471 "flash_self=run ramargs addip addcons;" \
472 "bootm $kernel_addr $ramdisk_addr\0" \
473 "net_nfs=tftp $loadaddr $bootfile;" \
474 "run nfsargs addip addcons;bootm\0" \
475 "rootpath=/opt/eldk/ppc_85xx\0" \
476 "kernel_addr=FC000000\0" \
477 "ramdisk_addr=FC200000\0" \
478 ""
479#define CONFIG_BOOTCOMMAND "run flash_self"
480
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200481#endif /* CONFIG_ENV_IS_IN_EEPROM */
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200482
Dan Malek35171dc2007-01-05 09:15:34 +0100483#endif /* __CONFIG_H */