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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkedc48b62002-09-08 17:56:50 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkedc48b62002-09-08 17:56:50 +00005 */
6
7/* for now: just dummy functions to satisfy the linker */
8
wdenk8ed96042005-01-09 23:16:25 +00009#include <common.h>
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070010#include <malloc.h>
wdenk8ed96042005-01-09 23:16:25 +000011
Wu, Josh633b6cc2015-07-27 11:40:17 +080012/*
13 * Flush range from all levels of d-cache/unified-cache.
14 * Affects the range [start, start + size - 1].
15 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020016__weak void flush_cache(unsigned long start, unsigned long size)
wdenkedc48b62002-09-08 17:56:50 +000017{
Wu, Josh633b6cc2015-07-27 11:40:17 +080018 flush_dcache_range(start, start + size);
wdenkedc48b62002-09-08 17:56:50 +000019}
Aneesh Ve05f0072011-06-16 23:30:50 +000020
21/*
22 * Default implementation:
23 * do a range flush for the entire range
24 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020025__weak void flush_dcache_all(void)
Aneesh Ve05f0072011-06-16 23:30:50 +000026{
27 flush_cache(0, ~0);
28}
Aneesh Vcba4b182011-08-16 04:33:05 +000029
30/*
31 * Default implementation of enable_caches()
32 * Real implementation should be in platform code
33 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020034__weak void enable_caches(void)
Aneesh Vcba4b182011-08-16 04:33:05 +000035{
36 puts("WARNING: Caches not enabled\n");
37}
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070038
Wu, Josh387871a2015-07-27 11:40:16 +080039__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
40{
41 /* An empty stub, real implementation should be in platform code */
42}
43__weak void flush_dcache_range(unsigned long start, unsigned long stop)
44{
45 /* An empty stub, real implementation should be in platform code */
46}
47
Simon Glass397b5692016-06-19 19:43:01 -060048int check_cache_range(unsigned long start, unsigned long stop)
49{
50 int ok = 1;
51
52 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
53 ok = 0;
54
55 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
56 ok = 0;
57
58 if (!ok) {
Simon Glassbcc53bf2016-06-19 19:43:05 -060059 warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
60 start, stop);
Simon Glass397b5692016-06-19 19:43:01 -060061 }
62
63 return ok;
64}
65
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070066#ifdef CONFIG_SYS_NONCACHED_MEMORY
67/*
68 * Reserve one MMU section worth of address space below the malloc() area that
69 * will be mapped uncached.
70 */
71static unsigned long noncached_start;
72static unsigned long noncached_end;
73static unsigned long noncached_next;
74
75void noncached_init(void)
76{
77 phys_addr_t start, end;
78 size_t size;
79
80 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
81 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
82 start = end - size;
83
84 debug("mapping memory %pa-%pa non-cached\n", &start, &end);
85
86 noncached_start = start;
87 noncached_end = end;
88 noncached_next = start;
89
90#ifndef CONFIG_SYS_DCACHE_OFF
91 mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
92#endif
93}
94
95phys_addr_t noncached_alloc(size_t size, size_t align)
96{
97 phys_addr_t next = ALIGN(noncached_next, align);
98
99 if (next >= noncached_end || (noncached_end - next) < size)
100 return 0;
101
102 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
103 noncached_next = next + size;
104
105 return next;
106}
107#endif /* CONFIG_SYS_NONCACHED_MEMORY */
Albert ARIBAUD62e92072015-10-23 18:06:40 +0200108
Tom Rini3a649402017-03-18 09:01:44 -0400109#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
Albert ARIBAUD62e92072015-10-23 18:06:40 +0200110void invalidate_l2_cache(void)
111{
112 unsigned int val = 0;
113
114 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
115 : : "r" (val) : "cc");
116 isb();
117}
118#endif