Bin Meng | 117a433 | 2018-09-26 06:55:06 -0700 | [diff] [blame] | 1 | menu "RISC-V architecture" |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 2 | depends on RISCV |
| 3 | |
| 4 | config SYS_ARCH |
| 5 | default "riscv" |
| 6 | |
| 7 | choice |
| 8 | prompt "Target select" |
| 9 | optional |
| 10 | |
Randolph | b68bf22 | 2023-09-25 17:24:51 +0800 | [diff] [blame] | 11 | config TARGET_ANDES_AE350 |
| 12 | bool "Support Andes ae350" |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 13 | |
Padmarao Begari | 3949482 | 2019-05-28 15:47:51 +0530 | [diff] [blame] | 14 | config TARGET_MICROCHIP_ICICLE |
| 15 | bool "Support Microchip PolarFire-SoC Icicle Board" |
| 16 | |
Kongyang Liu | 0dc6ee6 | 2024-01-28 15:05:25 +0800 | [diff] [blame^] | 17 | config TARGET_MILKV_DUO |
| 18 | bool "Support Milk-v Duo Board" |
| 19 | |
Samuel Holland | a6a77e4 | 2023-10-31 00:32:12 -0500 | [diff] [blame] | 20 | config TARGET_OPENPITON_RISCV64 |
| 21 | bool "Support RISC-V cores on OpenPiton SoC" |
| 22 | |
Bin Meng | 510e379 | 2018-09-26 06:55:21 -0700 | [diff] [blame] | 23 | config TARGET_QEMU_VIRT |
| 24 | bool "Support QEMU Virt Board" |
| 25 | |
Bin Meng | ae2d950 | 2021-03-17 11:10:58 +0800 | [diff] [blame] | 26 | config TARGET_SIFIVE_UNLEASHED |
| 27 | bool "Support SiFive Unleashed Board" |
Anup Patel | 3fda026 | 2019-02-25 08:15:19 +0000 | [diff] [blame] | 28 | |
Green Wan | 70415e1 | 2021-05-27 06:52:13 -0700 | [diff] [blame] | 29 | config TARGET_SIFIVE_UNMATCHED |
| 30 | bool "Support SiFive Unmatched Board" |
Tom Rini | ab92b38 | 2021-08-26 11:47:59 -0400 | [diff] [blame] | 31 | select SYS_CACHE_SHIFT_6 |
Green Wan | 70415e1 | 2021-05-27 06:52:13 -0700 | [diff] [blame] | 32 | |
Samuel Holland | a6a77e4 | 2023-10-31 00:32:12 -0500 | [diff] [blame] | 33 | config TARGET_SIPEED_MAIX |
| 34 | bool "Support Sipeed Maix Board" |
| 35 | select SYS_CACHE_SHIFT_6 |
| 36 | |
Yanhong Wang | 331ad93 | 2023-03-29 11:42:20 +0800 | [diff] [blame] | 37 | config TARGET_STARFIVE_VISIONFIVE2 |
| 38 | bool "Support StarFive VisionFive2 Board" |
Heinrich Schuchardt | 16dbe3d | 2023-09-07 13:21:28 +0200 | [diff] [blame] | 39 | select BOARD_LATE_INIT |
Yanhong Wang | 331ad93 | 2023-03-29 11:42:20 +0800 | [diff] [blame] | 40 | |
Yixun Lan | 5f3a7fd | 2023-07-08 19:24:32 +0800 | [diff] [blame] | 41 | config TARGET_TH1520_LPI4A |
| 42 | bool "Support Sipeed's TH1520 Lichee PI 4A Board" |
| 43 | select SYS_CACHE_SHIFT_6 |
| 44 | |
Michal Simek | 7576ab2 | 2023-11-06 12:56:47 +0100 | [diff] [blame] | 45 | config TARGET_XILINX_MBV |
| 46 | bool "Support AMD/Xilinx MicroBlaze V" |
| 47 | |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 48 | endchoice |
| 49 | |
Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 50 | config SYS_ICACHE_OFF |
| 51 | bool "Do not enable icache" |
Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 52 | help |
| 53 | Do not enable instruction cache in U-Boot. |
| 54 | |
Trevor Woerner | 1001502 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 55 | config SPL_SYS_ICACHE_OFF |
| 56 | bool "Do not enable icache in SPL" |
| 57 | depends on SPL |
| 58 | default SYS_ICACHE_OFF |
| 59 | help |
| 60 | Do not enable instruction cache in SPL. |
| 61 | |
Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 62 | config SYS_DCACHE_OFF |
| 63 | bool "Do not enable dcache" |
Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 64 | help |
| 65 | Do not enable data cache in U-Boot. |
| 66 | |
Trevor Woerner | 1001502 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 67 | config SPL_SYS_DCACHE_OFF |
| 68 | bool "Do not enable dcache in SPL" |
| 69 | depends on SPL |
| 70 | default SYS_DCACHE_OFF |
| 71 | help |
| 72 | Do not enable data cache in SPL. |
| 73 | |
Shengyu Qu | d365f66 | 2023-08-09 21:11:31 +0800 | [diff] [blame] | 74 | config SPL_ZERO_MEM_BEFORE_USE |
| 75 | bool "Zero memory before use" |
| 76 | depends on SPL |
Shengyu Qu | d365f66 | 2023-08-09 21:11:31 +0800 | [diff] [blame] | 77 | help |
| 78 | Zero stack/GD/malloc area in SPL before using them, this is needed for |
| 79 | Sifive core devices that uses L2 cache to store SPL. |
| 80 | |
Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 81 | # board-specific options below |
Leo Yu-Chi Liang | 8900e2b | 2023-02-14 20:42:49 +0800 | [diff] [blame] | 82 | source "board/AndesTech/ae350/Kconfig" |
Bin Meng | 510e379 | 2018-09-26 06:55:21 -0700 | [diff] [blame] | 83 | source "board/emulation/qemu-riscv/Kconfig" |
Padmarao Begari | 3949482 | 2019-05-28 15:47:51 +0530 | [diff] [blame] | 84 | source "board/microchip/mpfs_icicle/Kconfig" |
Samuel Holland | a6a77e4 | 2023-10-31 00:32:12 -0500 | [diff] [blame] | 85 | source "board/openpiton/riscv64/Kconfig" |
Bin Meng | ae2d950 | 2021-03-17 11:10:58 +0800 | [diff] [blame] | 86 | source "board/sifive/unleashed/Kconfig" |
Green Wan | 70415e1 | 2021-05-27 06:52:13 -0700 | [diff] [blame] | 87 | source "board/sifive/unmatched/Kconfig" |
Sean Anderson | a7c81fc | 2020-06-24 06:41:25 -0400 | [diff] [blame] | 88 | source "board/sipeed/maix/Kconfig" |
Kongyang Liu | 0dc6ee6 | 2024-01-28 15:05:25 +0800 | [diff] [blame^] | 89 | source "board/sophgo/milkv_duo/Kconfig" |
Yanhong Wang | 331ad93 | 2023-03-29 11:42:20 +0800 | [diff] [blame] | 90 | source "board/starfive/visionfive2/Kconfig" |
Samuel Holland | a6a77e4 | 2023-10-31 00:32:12 -0500 | [diff] [blame] | 91 | source "board/thead/th1520_lpi4a/Kconfig" |
Michal Simek | 7576ab2 | 2023-11-06 12:56:47 +0100 | [diff] [blame] | 92 | source "board/xilinx/mbv/Kconfig" |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 93 | |
Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 94 | # platform-specific options below |
Leo Yu-Chi Liang | 8900e2b | 2023-02-14 20:42:49 +0800 | [diff] [blame] | 95 | source "arch/riscv/cpu/andesv5/Kconfig" |
Pragnesh Patel | 7c45fc9 | 2020-05-29 11:33:34 +0530 | [diff] [blame] | 96 | source "arch/riscv/cpu/fu540/Kconfig" |
Green Wan | a74e9d8 | 2021-05-27 06:52:07 -0700 | [diff] [blame] | 97 | source "arch/riscv/cpu/fu740/Kconfig" |
Anup Patel | fdff1f9 | 2019-02-25 08:14:10 +0000 | [diff] [blame] | 98 | source "arch/riscv/cpu/generic/Kconfig" |
Yanhong Wang | 331ad93 | 2023-03-29 11:42:20 +0800 | [diff] [blame] | 99 | source "arch/riscv/cpu/jh7110/Kconfig" |
Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 100 | |
| 101 | # architecture-specific options below |
| 102 | |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 103 | choice |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 104 | prompt "Base ISA" |
| 105 | default ARCH_RV32I |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 106 | |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 107 | config ARCH_RV32I |
| 108 | bool "RV32I" |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 109 | select 32BIT |
| 110 | help |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 111 | Choose this option to target the RV32I base integer instruction set. |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 112 | |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 113 | config ARCH_RV64I |
| 114 | bool "RV64I" |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 115 | select 64BIT |
Lukas Auer | 7115856 | 2018-11-22 11:26:13 +0100 | [diff] [blame] | 116 | select PHYS_64BIT |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 117 | help |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 118 | Choose this option to target the RV64I base integer instruction set. |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 119 | |
| 120 | endchoice |
| 121 | |
Lukas Auer | 8176ea4 | 2018-12-12 06:12:23 -0800 | [diff] [blame] | 122 | choice |
| 123 | prompt "Code Model" |
| 124 | default CMODEL_MEDLOW |
| 125 | |
| 126 | config CMODEL_MEDLOW |
| 127 | bool "medium low code model" |
| 128 | help |
| 129 | U-Boot and its statically defined symbols must lie within a single 2 GiB |
| 130 | address range and must lie between absolute addresses -2 GiB and +2 GiB. |
| 131 | |
| 132 | config CMODEL_MEDANY |
| 133 | bool "medium any code model" |
| 134 | help |
| 135 | U-Boot and its statically defined symbols must be within any single 2 GiB |
| 136 | address range. |
| 137 | |
| 138 | endchoice |
| 139 | |
Anup Patel | 3cfc825 | 2018-12-12 06:12:29 -0800 | [diff] [blame] | 140 | choice |
| 141 | prompt "Run Mode" |
| 142 | default RISCV_MMODE |
| 143 | |
| 144 | config RISCV_MMODE |
| 145 | bool "Machine" |
| 146 | help |
| 147 | Choose this option to build U-Boot for RISC-V M-Mode. |
| 148 | |
| 149 | config RISCV_SMODE |
| 150 | bool "Supervisor" |
Heinrich Schuchardt | e637e45 | 2023-09-23 01:35:26 +0200 | [diff] [blame] | 151 | imply DEBUG_UART |
Anup Patel | 3cfc825 | 2018-12-12 06:12:29 -0800 | [diff] [blame] | 152 | help |
| 153 | Choose this option to build U-Boot for RISC-V S-Mode. |
| 154 | |
| 155 | endchoice |
| 156 | |
Lukas Auer | fbfd92b | 2019-08-21 21:14:43 +0200 | [diff] [blame] | 157 | choice |
| 158 | prompt "SPL Run Mode" |
| 159 | default SPL_RISCV_MMODE |
| 160 | depends on SPL |
| 161 | |
| 162 | config SPL_RISCV_MMODE |
| 163 | bool "Machine" |
| 164 | help |
| 165 | Choose this option to build U-Boot SPL for RISC-V M-Mode. |
| 166 | |
| 167 | config SPL_RISCV_SMODE |
| 168 | bool "Supervisor" |
| 169 | help |
| 170 | Choose this option to build U-Boot SPL for RISC-V S-Mode. |
| 171 | |
| 172 | endchoice |
| 173 | |
Lukas Auer | d57ffa6 | 2018-11-22 11:26:14 +0100 | [diff] [blame] | 174 | config RISCV_ISA_C |
| 175 | bool "Emit compressed instructions" |
| 176 | default y |
| 177 | help |
| 178 | Adds "C" to the ISA subsets that the toolchain is allowed to emit |
| 179 | when building U-Boot, which results in compressed instructions in the |
| 180 | U-Boot binary. |
| 181 | |
Heinrich Schuchardt | e67f34f | 2022-10-12 14:59:51 +0200 | [diff] [blame] | 182 | config RISCV_ISA_F |
| 183 | bool "Standard extension for Single-Precision Floating Point" |
| 184 | default y |
| 185 | help |
| 186 | Adds "F" to the ISA string passed to the compiler. |
| 187 | |
| 188 | config RISCV_ISA_D |
| 189 | bool "Standard extension for Double-Precision Floating Point" |
| 190 | depends on RISCV_ISA_F |
| 191 | default y |
| 192 | help |
| 193 | Adds "D" to the ISA string passed to the compiler and changes the |
| 194 | riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to |
| 195 | lp64d. |
| 196 | |
Yu Chien Peter Lin | bc5a504 | 2023-08-09 18:49:30 +0800 | [diff] [blame] | 197 | config RISCV_ISA_ZBB |
| 198 | bool "Zbb extension support for bit manipulation instructions" |
| 199 | help |
| 200 | Adds ZBB extension (basic bit manipulation) to the ISA subsets |
| 201 | that the toolchain is allowed to emit when building U-Boot. |
| 202 | The Zbb extension provides instructions to accelerate a number |
| 203 | of bit-specific operations (count bit population, sign extending, |
| 204 | bitrotation, etc) and enables optimized string routines. |
| 205 | |
| 206 | menu "Use assembly optimized implementation of string routines" |
| 207 | |
| 208 | config USE_ARCH_STRLEN |
| 209 | bool "Use an assembly optimized implementation of strlen" |
| 210 | default y |
| 211 | depends on RISCV_ISA_ZBB |
| 212 | help |
| 213 | Enable the generation of an optimized version of strlen using |
| 214 | Zbb extension. |
| 215 | |
| 216 | config SPL_USE_ARCH_STRLEN |
| 217 | bool "Use an assembly optimized implementation of strlen for SPL" |
| 218 | default y if USE_ARCH_STRLEN |
| 219 | depends on RISCV_ISA_ZBB |
| 220 | depends on SPL |
| 221 | help |
| 222 | Enable the generation of an optimized version of strlen using |
| 223 | Zbb extension. |
| 224 | |
| 225 | config TPL_USE_ARCH_STRLEN |
| 226 | bool "Use an assembly optimized implementation of strlen for TPL" |
| 227 | default y if USE_ARCH_STRLEN |
| 228 | depends on RISCV_ISA_ZBB |
| 229 | depends on TPL |
| 230 | help |
| 231 | Enable the generation of an optimized version of strlen using |
| 232 | Zbb extension. |
| 233 | |
| 234 | config USE_ARCH_STRCMP |
| 235 | bool "Use an assembly optimized implementation of strcmp" |
| 236 | default y |
| 237 | depends on RISCV_ISA_ZBB |
| 238 | help |
| 239 | Enable the generation of an optimized version of strcmp using |
| 240 | Zbb extension. |
| 241 | |
| 242 | config SPL_USE_ARCH_STRCMP |
| 243 | bool "Use an assembly optimized implementation of strcmp for SPL" |
| 244 | default y if USE_ARCH_STRCMP |
| 245 | depends on RISCV_ISA_ZBB |
| 246 | depends on SPL |
| 247 | help |
| 248 | Enable the generation of an optimized version of strcmp using |
| 249 | Zbb extension. |
| 250 | |
| 251 | config TPL_USE_ARCH_STRCMP |
| 252 | bool "Use an assembly optimized implementation of strcmp for TPL" |
| 253 | default y if USE_ARCH_STRCMP |
| 254 | depends on RISCV_ISA_ZBB |
| 255 | depends on TPL |
| 256 | help |
| 257 | Enable the generation of an optimized version of strcmp using |
| 258 | Zbb extension. |
| 259 | |
| 260 | config USE_ARCH_STRNCMP |
| 261 | bool "Use an assembly optimized implementation of strncmp" |
| 262 | default y |
| 263 | depends on RISCV_ISA_ZBB |
| 264 | help |
| 265 | Enable the generation of an optimized version of strncmp using |
| 266 | Zbb extension. |
| 267 | |
| 268 | config SPL_USE_ARCH_STRNCMP |
| 269 | bool "Use an assembly optimized implementation of strncmp for SPL" |
| 270 | default y if USE_ARCH_STRNCMP |
| 271 | depends on RISCV_ISA_ZBB |
| 272 | depends on SPL |
| 273 | help |
| 274 | Enable the generation of an optimized version of strncmp using |
| 275 | Zbb extension. |
| 276 | |
| 277 | config TPL_USE_ARCH_STRNCMP |
| 278 | bool "Use an assembly optimized implementation of strncmp for TPL" |
| 279 | default y if USE_ARCH_STRNCMP |
| 280 | depends on RISCV_ISA_ZBB |
| 281 | depends on TPL |
| 282 | help |
| 283 | Enable the generation of an optimized version of strncmp using |
| 284 | Zbb extension. |
| 285 | |
| 286 | endmenu |
| 287 | |
Lukas Auer | d57ffa6 | 2018-11-22 11:26:14 +0100 | [diff] [blame] | 288 | config RISCV_ISA_A |
| 289 | def_bool y |
| 290 | |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 291 | config 32BIT |
| 292 | bool |
| 293 | |
| 294 | config 64BIT |
| 295 | bool |
| 296 | |
Padmarao Begari | 5af3574 | 2021-01-15 08:20:35 +0530 | [diff] [blame] | 297 | config DMA_ADDR_T_64BIT |
| 298 | bool |
| 299 | default y if 64BIT |
| 300 | |
Bin Meng | 9675d92 | 2023-06-21 23:11:46 +0800 | [diff] [blame] | 301 | config RISCV_ACLINT |
Bin Meng | 644a3cd | 2018-12-12 06:12:30 -0800 | [diff] [blame] | 302 | bool |
Bin Meng | a6d7e8c | 2021-05-11 20:04:12 +0800 | [diff] [blame] | 303 | depends on RISCV_MMODE |
Bin Meng | 7f1a30f | 2023-06-21 23:11:45 +0800 | [diff] [blame] | 304 | select REGMAP |
| 305 | select SYSCON |
Bin Meng | a6d7e8c | 2021-05-11 20:04:12 +0800 | [diff] [blame] | 306 | help |
Bin Meng | 9675d92 | 2023-06-21 23:11:46 +0800 | [diff] [blame] | 307 | The RISC-V ACLINT block holds memory-mapped control and status registers |
Bin Meng | a6d7e8c | 2021-05-11 20:04:12 +0800 | [diff] [blame] | 308 | associated with software and timer interrupts. |
| 309 | |
Bin Meng | 9675d92 | 2023-06-21 23:11:46 +0800 | [diff] [blame] | 310 | config SPL_RISCV_ACLINT |
Bin Meng | a6d7e8c | 2021-05-11 20:04:12 +0800 | [diff] [blame] | 311 | bool |
| 312 | depends on SPL_RISCV_MMODE |
Bin Meng | 7f1a30f | 2023-06-21 23:11:45 +0800 | [diff] [blame] | 313 | select SPL_REGMAP |
| 314 | select SPL_SYSCON |
Bin Meng | 644a3cd | 2018-12-12 06:12:30 -0800 | [diff] [blame] | 315 | help |
Bin Meng | 9675d92 | 2023-06-21 23:11:46 +0800 | [diff] [blame] | 316 | The RISC-V ACLINT block holds memory-mapped control and status registers |
Bin Meng | 644a3cd | 2018-12-12 06:12:30 -0800 | [diff] [blame] | 317 | associated with software and timer interrupts. |
| 318 | |
Zong Li | 213ed17 | 2021-09-01 15:01:41 +0800 | [diff] [blame] | 319 | config SIFIVE_CACHE |
| 320 | bool |
| 321 | help |
| 322 | This enables the operations to configure SiFive cache |
| 323 | |
Yu Chien Peter Lin | a5dfa3b | 2022-10-25 23:03:50 +0800 | [diff] [blame] | 324 | config ANDES_PLICSW |
Rick Chen | 0d38946 | 2019-04-02 15:56:39 +0800 | [diff] [blame] | 325 | bool |
Lukas Auer | fbfd92b | 2019-08-21 21:14:43 +0200 | [diff] [blame] | 326 | depends on RISCV_MMODE || SPL_RISCV_MMODE |
Rick Chen | 0d38946 | 2019-04-02 15:56:39 +0800 | [diff] [blame] | 327 | select REGMAP |
| 328 | select SYSCON |
Lukas Auer | fbfd92b | 2019-08-21 21:14:43 +0200 | [diff] [blame] | 329 | select SPL_REGMAP if SPL |
| 330 | select SPL_SYSCON if SPL |
Rick Chen | 0d38946 | 2019-04-02 15:56:39 +0800 | [diff] [blame] | 331 | help |
Yu Chien Peter Lin | a5dfa3b | 2022-10-25 23:03:50 +0800 | [diff] [blame] | 332 | The Andes PLICSW block holds memory-mapped claim and pending |
| 333 | registers associated with software interrupt. |
Rick Chen | 0d38946 | 2019-04-02 15:56:39 +0800 | [diff] [blame] | 334 | |
Lukas Auer | fa33f08 | 2019-03-17 19:28:32 +0100 | [diff] [blame] | 335 | config SMP |
| 336 | bool "Symmetric Multi-Processing" |
Bin Meng | 6fa022e | 2020-04-16 08:09:31 -0700 | [diff] [blame] | 337 | depends on SBI_V01 || !RISCV_SMODE |
Lukas Auer | fa33f08 | 2019-03-17 19:28:32 +0100 | [diff] [blame] | 338 | help |
| 339 | This enables support for systems with more than one CPU. If |
| 340 | you say N here, U-Boot will run on single and multiprocessor |
| 341 | machines, but will use only one CPU of a multiprocessor |
| 342 | machine. If you say Y here, U-Boot will run on many, but not |
| 343 | all, single processor machines. |
| 344 | |
Bin Meng | 191636e | 2020-04-16 08:09:30 -0700 | [diff] [blame] | 345 | config SPL_SMP |
| 346 | bool "Symmetric Multi-Processing in SPL" |
| 347 | depends on SPL && SPL_RISCV_MMODE |
| 348 | default y |
| 349 | help |
| 350 | This enables support for systems with more than one CPU in SPL. |
| 351 | If you say N here, U-Boot SPL will run on single and multiprocessor |
| 352 | machines, but will use only one CPU of a multiprocessor |
| 353 | machine. If you say Y here, U-Boot SPL will run on many, but not |
| 354 | all, single processor machines. |
| 355 | |
Lukas Auer | fa33f08 | 2019-03-17 19:28:32 +0100 | [diff] [blame] | 356 | config NR_CPUS |
| 357 | int "Maximum number of CPUs (2-32)" |
| 358 | range 2 32 |
Bin Meng | 191636e | 2020-04-16 08:09:30 -0700 | [diff] [blame] | 359 | depends on SMP || SPL_SMP |
Lukas Auer | fa33f08 | 2019-03-17 19:28:32 +0100 | [diff] [blame] | 360 | default 8 |
| 361 | help |
| 362 | On multiprocessor machines, U-Boot sets up a stack for each CPU. |
| 363 | Stack memory is pre-allocated. U-Boot must therefore know the |
| 364 | maximum number of CPUs that may be present. |
| 365 | |
Bin Meng | f58fc34 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 366 | config SBI |
| 367 | bool |
| 368 | default y if RISCV_SMODE || SPL_RISCV_SMODE |
| 369 | |
Bin Meng | ff0fa6c | 2020-04-16 08:09:32 -0700 | [diff] [blame] | 370 | choice |
| 371 | prompt "SBI support" |
Bin Meng | fa16ec2 | 2020-04-16 08:09:33 -0700 | [diff] [blame] | 372 | default SBI_V02 |
Bin Meng | ff0fa6c | 2020-04-16 08:09:32 -0700 | [diff] [blame] | 373 | |
Bin Meng | 1b3c8d6 | 2020-03-09 19:35:30 -0700 | [diff] [blame] | 374 | config SBI_V01 |
| 375 | bool "SBI v0.1 support" |
Bin Meng | 1b3c8d6 | 2020-03-09 19:35:30 -0700 | [diff] [blame] | 376 | depends on SBI |
| 377 | help |
| 378 | This config allows kernel to use SBI v0.1 APIs. This will be |
| 379 | deprecated in future once legacy M-mode software are no longer in use. |
| 380 | |
Bin Meng | ff0fa6c | 2020-04-16 08:09:32 -0700 | [diff] [blame] | 381 | config SBI_V02 |
Heinrich Schuchardt | 5c89467 | 2022-11-08 15:53:12 +0100 | [diff] [blame] | 382 | bool "SBI v0.2 or later support" |
Bin Meng | ff0fa6c | 2020-04-16 08:09:32 -0700 | [diff] [blame] | 383 | depends on SBI |
| 384 | help |
Heinrich Schuchardt | 5c89467 | 2022-11-08 15:53:12 +0100 | [diff] [blame] | 385 | The SBI specification introduced the concept of extensions in version |
| 386 | v0.2. With this configuration option U-Boot can detect and use SBI |
| 387 | extensions. With the HSM extension introduced in SBI 0.2, only a |
| 388 | single hart needs to boot and enter the operating system. The booting |
| 389 | hart can bring up secondary harts one by one afterwards. |
Bin Meng | ff0fa6c | 2020-04-16 08:09:32 -0700 | [diff] [blame] | 390 | |
Heinrich Schuchardt | 5c89467 | 2022-11-08 15:53:12 +0100 | [diff] [blame] | 391 | Choose this option if OpenSBI release v0.7 or above is used together |
Bin Meng | ff0fa6c | 2020-04-16 08:09:32 -0700 | [diff] [blame] | 392 | with U-Boot. |
| 393 | |
| 394 | endchoice |
| 395 | |
Lukas Auer | f152feb | 2019-03-17 19:28:34 +0100 | [diff] [blame] | 396 | config SBI_IPI |
| 397 | bool |
Bin Meng | f58fc34 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 398 | depends on SBI |
Lukas Auer | fbfd92b | 2019-08-21 21:14:43 +0200 | [diff] [blame] | 399 | default y if RISCV_SMODE || SPL_RISCV_SMODE |
Lukas Auer | f152feb | 2019-03-17 19:28:34 +0100 | [diff] [blame] | 400 | depends on SMP |
| 401 | |
Rick Chen | bdce389 | 2019-04-30 13:49:33 +0800 | [diff] [blame] | 402 | config XIP |
| 403 | bool "XIP mode" |
| 404 | help |
| 405 | XIP (eXecute In Place) is a method for executing code directly |
| 406 | from a NOR flash memory without copying the code to ram. |
| 407 | Say yes here if U-Boot boots from flash directly. |
| 408 | |
Nikita Shubin | c2bdf02 | 2022-09-02 11:47:39 +0300 | [diff] [blame] | 409 | config SPL_XIP |
| 410 | bool "Enable XIP mode for SPL" |
| 411 | help |
| 412 | If SPL starts in read-only memory (XIP for example) then we shouldn't |
| 413 | rely on lock variables (for example hart_lottery and available_harts_lock), |
| 414 | this affects only SPL, other stages should proceed as non-XIP. |
| 415 | |
Rick Chen | e0465f8 | 2022-09-21 14:34:54 +0800 | [diff] [blame] | 416 | config AVAILABLE_HARTS |
| 417 | bool "Send IPI by available harts" |
| 418 | default y |
| 419 | help |
| 420 | By default, IPI sending mechanism will depend on available_harts. |
| 421 | If disable this, it will send IPI by CPUs node numbers of device tree. |
| 422 | |
Sean Anderson | fd1f6e9 | 2019-12-25 00:27:44 -0500 | [diff] [blame] | 423 | config SHOW_REGS |
| 424 | bool "Show registers on unhandled exception" |
| 425 | |
Sean Anderson | b8bc120 | 2020-06-24 06:41:19 -0400 | [diff] [blame] | 426 | config RISCV_PRIV_1_9 |
| 427 | bool "Use version 1.9 of the RISC-V priviledged specification" |
| 428 | help |
| 429 | Older versions of the RISC-V priviledged specification had |
| 430 | separate counter enable CSRs for each privilege mode. Writing |
| 431 | to the unified mcounteren CSR on a processor implementing the |
| 432 | old specification will result in an illegal instruction |
| 433 | exception. In addition to counter CSR changes, the way virtual |
| 434 | memory is configured was also changed. |
| 435 | |
Lukas Auer | 3dea63c | 2019-03-17 19:28:37 +0100 | [diff] [blame] | 436 | config STACK_SIZE_SHIFT |
| 437 | int |
Lukas Auer | 6b20dc1 | 2019-10-20 20:53:47 +0200 | [diff] [blame] | 438 | default 14 |
Lukas Auer | 3dea63c | 2019-03-17 19:28:37 +0100 | [diff] [blame] | 439 | |
Bin Meng | 1c17e55 | 2020-06-25 18:16:08 -0700 | [diff] [blame] | 440 | config OF_BOARD_FIXUP |
Sean Anderson | 32cef69 | 2020-09-05 09:22:11 -0400 | [diff] [blame] | 441 | default y if OF_SEPARATE && RISCV_SMODE |
Bin Meng | 1c17e55 | 2020-06-25 18:16:08 -0700 | [diff] [blame] | 442 | |
Bin Meng | 8941927 | 2021-05-13 16:46:18 +0800 | [diff] [blame] | 443 | menu "Use assembly optimized implementation of memory routines" |
| 444 | |
Heinrich Schuchardt | 8f0dc4c | 2021-03-27 12:37:04 +0100 | [diff] [blame] | 445 | config USE_ARCH_MEMCPY |
| 446 | bool "Use an assembly optimized implementation of memcpy" |
| 447 | default y |
| 448 | help |
| 449 | Enable the generation of an optimized version of memcpy. |
| 450 | Such an implementation may be faster under some conditions |
| 451 | but may increase the binary size. |
| 452 | |
| 453 | config SPL_USE_ARCH_MEMCPY |
| 454 | bool "Use an assembly optimized implementation of memcpy for SPL" |
| 455 | default y if USE_ARCH_MEMCPY |
| 456 | depends on SPL |
| 457 | help |
| 458 | Enable the generation of an optimized version of memcpy. |
| 459 | Such an implementation may be faster under some conditions |
| 460 | but may increase the binary size. |
| 461 | |
| 462 | config TPL_USE_ARCH_MEMCPY |
| 463 | bool "Use an assembly optimized implementation of memcpy for TPL" |
| 464 | default y if USE_ARCH_MEMCPY |
| 465 | depends on TPL |
| 466 | help |
| 467 | Enable the generation of an optimized version of memcpy. |
| 468 | Such an implementation may be faster under some conditions |
| 469 | but may increase the binary size. |
| 470 | |
| 471 | config USE_ARCH_MEMMOVE |
| 472 | bool "Use an assembly optimized implementation of memmove" |
| 473 | default y |
| 474 | help |
| 475 | Enable the generation of an optimized version of memmove. |
| 476 | Such an implementation may be faster under some conditions |
| 477 | but may increase the binary size. |
| 478 | |
| 479 | config SPL_USE_ARCH_MEMMOVE |
| 480 | bool "Use an assembly optimized implementation of memmove for SPL" |
| 481 | default y if USE_ARCH_MEMCPY |
| 482 | depends on SPL |
| 483 | help |
| 484 | Enable the generation of an optimized version of memmove. |
| 485 | Such an implementation may be faster under some conditions |
| 486 | but may increase the binary size. |
| 487 | |
| 488 | config TPL_USE_ARCH_MEMMOVE |
| 489 | bool "Use an assembly optimized implementation of memmove for TPL" |
| 490 | default y if USE_ARCH_MEMCPY |
| 491 | depends on TPL |
| 492 | help |
| 493 | Enable the generation of an optimized version of memmove. |
| 494 | Such an implementation may be faster under some conditions |
| 495 | but may increase the binary size. |
| 496 | |
| 497 | config USE_ARCH_MEMSET |
| 498 | bool "Use an assembly optimized implementation of memset" |
| 499 | default y |
| 500 | help |
| 501 | Enable the generation of an optimized version of memset. |
| 502 | Such an implementation may be faster under some conditions |
| 503 | but may increase the binary size. |
| 504 | |
| 505 | config SPL_USE_ARCH_MEMSET |
| 506 | bool "Use an assembly optimized implementation of memset for SPL" |
| 507 | default y if USE_ARCH_MEMSET |
| 508 | depends on SPL |
| 509 | help |
| 510 | Enable the generation of an optimized version of memset. |
| 511 | Such an implementation may be faster under some conditions |
| 512 | but may increase the binary size. |
| 513 | |
| 514 | config TPL_USE_ARCH_MEMSET |
| 515 | bool "Use an assembly optimized implementation of memset for TPL" |
| 516 | default y if USE_ARCH_MEMSET |
| 517 | depends on TPL |
| 518 | help |
| 519 | Enable the generation of an optimized version of memset. |
| 520 | Such an implementation may be faster under some conditions |
| 521 | but may increase the binary size. |
| 522 | |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 523 | endmenu |
Bin Meng | 8941927 | 2021-05-13 16:46:18 +0800 | [diff] [blame] | 524 | |
Randolph | e09a228 | 2023-10-12 14:35:04 +0800 | [diff] [blame] | 525 | config SPL_LOAD_FIT_OPENSBI_OS_BOOT |
| 526 | bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT" |
| 527 | depends on SPL_LOAD_FIT |
| 528 | help |
| 529 | Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly. |
| 530 | This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper |
| 531 | -> linux to u-boot SPL -> OpenSBI -> linux. |
| 532 | |
Bin Meng | 8941927 | 2021-05-13 16:46:18 +0800 | [diff] [blame] | 533 | endmenu |