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wdenkf9087a32002-11-03 00:30:25 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
wdenk384ae022002-11-05 00:17:55 +00009 * (C) Copyright 2002
wdenk8bde7f72003-06-27 21:31:46 +000010 * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
wdenk384ae022002-11-05 00:17:55 +000011 *
wdenkb98fff12004-02-09 20:51:26 +000012 * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
13 * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
14 *
wdenkf9087a32002-11-03 00:30:25 +000015 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkb98fff12004-02-09 20:51:26 +000025 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkf9087a32002-11-03 00:30:25 +000026 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <common.h>
wdenk384ae022002-11-05 00:17:55 +000035#include <asm/arch/pxa-regs.h>
wdenkf9087a32002-11-03 00:30:25 +000036
37#define FLASH_BANK_SIZE 0x02000000
wdenkb98fff12004-02-09 20:51:26 +000038#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */
wdenkf9087a32002-11-03 00:30:25 +000039
wdenkb98fff12004-02-09 20:51:26 +000040flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
wdenkf9087a32002-11-03 00:30:25 +000041
42
wdenk384ae022002-11-05 00:17:55 +000043/**
44 * flash_init: - initialize data structures for flash chips
45 *
46 * @return: size of the flash
wdenkf9087a32002-11-03 00:30:25 +000047 */
48
49ulong flash_init(void)
50{
wdenk47cd00f2003-03-06 13:39:27 +000051 int i, j;
52 ulong size = 0;
wdenkf9087a32002-11-03 00:30:25 +000053
wdenk384ae022002-11-05 00:17:55 +000054 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
wdenk47cd00f2003-03-06 13:39:27 +000055 ulong flashbase = 0;
56 flash_info[i].flash_id =
wdenkb98fff12004-02-09 20:51:26 +000057 (INTEL_MANUFACT & FLASH_VENDMASK) |
58 (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
wdenk47cd00f2003-03-06 13:39:27 +000059 flash_info[i].size = FLASH_BANK_SIZE;
60 flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
61 memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
wdenkf9087a32002-11-03 00:30:25 +000062
wdenk384ae022002-11-05 00:17:55 +000063 switch (i) {
wdenkb98fff12004-02-09 20:51:26 +000064 case 0:
65 flashbase = PHYS_FLASH_1;
66 break;
67 default:
68 panic("configured too many flash banks!\n");
69 break;
wdenk47cd00f2003-03-06 13:39:27 +000070 }
wdenk384ae022002-11-05 00:17:55 +000071 for (j = 0; j < flash_info[i].sector_count; j++) {
wdenk47cd00f2003-03-06 13:39:27 +000072 flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
73 }
74 size += flash_info[i].size;
wdenkf9087a32002-11-03 00:30:25 +000075 }
wdenkf9087a32002-11-03 00:30:25 +000076
wdenk384ae022002-11-05 00:17:55 +000077 /* Protect monitor and environment sectors */
wdenk47cd00f2003-03-06 13:39:27 +000078 flash_protect(FLAG_PROTECT_SET,
79 CFG_FLASH_BASE,
wdenk3b57fe02003-05-30 12:48:29 +000080 CFG_FLASH_BASE + monitor_flash_len - 1,
wdenk47cd00f2003-03-06 13:39:27 +000081 &flash_info[0]);
wdenkf9087a32002-11-03 00:30:25 +000082
wdenk47cd00f2003-03-06 13:39:27 +000083 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020084 CONFIG_ENV_ADDR,
85 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
wdenk47cd00f2003-03-06 13:39:27 +000086 &flash_info[0]);
wdenkf9087a32002-11-03 00:30:25 +000087
wdenk47cd00f2003-03-06 13:39:27 +000088 return size;
wdenkf9087a32002-11-03 00:30:25 +000089}
90
wdenk384ae022002-11-05 00:17:55 +000091
92/**
93 * flash_print_info: - print information about the flash situation
wdenkf9087a32002-11-03 00:30:25 +000094 */
wdenk384ae022002-11-05 00:17:55 +000095
wdenkf9087a32002-11-03 00:30:25 +000096void flash_print_info (flash_info_t *info)
97{
wdenk47cd00f2003-03-06 13:39:27 +000098 int i, j;
wdenkf9087a32002-11-03 00:30:25 +000099
wdenk384ae022002-11-05 00:17:55 +0000100 for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
101
102 switch (info->flash_id & FLASH_VENDMASK) {
wdenkb98fff12004-02-09 20:51:26 +0000103 case (INTEL_MANUFACT & FLASH_VENDMASK):
104 printf ("Intel: ");
105 break;
106 default:
107 printf ("Unknown Vendor ");
108 break;
wdenk47cd00f2003-03-06 13:39:27 +0000109 }
wdenkf9087a32002-11-03 00:30:25 +0000110
wdenk384ae022002-11-05 00:17:55 +0000111 switch (info->flash_id & FLASH_TYPEMASK) {
wdenkb98fff12004-02-09 20:51:26 +0000112 case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
113 printf("28F128J3 (128Mbit)\n");
114 break;
115 default:
116 printf("Unknown Chip Type\n");
117 return;
wdenk47cd00f2003-03-06 13:39:27 +0000118 }
wdenkf9087a32002-11-03 00:30:25 +0000119
wdenk8bde7f72003-06-27 21:31:46 +0000120 printf(" Size: %ld MB in %d Sectors\n",
wdenk47cd00f2003-03-06 13:39:27 +0000121 info->size >> 20, info->sector_count);
wdenkf9087a32002-11-03 00:30:25 +0000122
wdenk47cd00f2003-03-06 13:39:27 +0000123 printf(" Sector Start Addresses:");
wdenk384ae022002-11-05 00:17:55 +0000124 for (i = 0; i < info->sector_count; i++) {
wdenkb98fff12004-02-09 20:51:26 +0000125 if ((i % 5) == 0) printf ("\n ");
wdenk8bde7f72003-06-27 21:31:46 +0000126
wdenk47cd00f2003-03-06 13:39:27 +0000127 printf (" %08lX%s", info->start[i],
wdenkb98fff12004-02-09 20:51:26 +0000128 info->protect[i] ? " (RO)" : " ");
wdenk47cd00f2003-03-06 13:39:27 +0000129 }
130 printf ("\n");
131 info++;
132 }
wdenkf9087a32002-11-03 00:30:25 +0000133}
134
wdenk384ae022002-11-05 00:17:55 +0000135
136/**
137 * flash_erase: - erase flash sectors
wdenkf9087a32002-11-03 00:30:25 +0000138 */
139
wdenk47cd00f2003-03-06 13:39:27 +0000140int flash_erase(flash_info_t *info, int s_first, int s_last)
wdenkf9087a32002-11-03 00:30:25 +0000141{
wdenk47cd00f2003-03-06 13:39:27 +0000142 int flag, prot, sect;
143 int rc = ERR_OK;
wdenkf9087a32002-11-03 00:30:25 +0000144
wdenk47cd00f2003-03-06 13:39:27 +0000145 if (info->flash_id == FLASH_UNKNOWN)
146 return ERR_UNKNOWN_FLASH_TYPE;
wdenkf9087a32002-11-03 00:30:25 +0000147
wdenk47cd00f2003-03-06 13:39:27 +0000148 if ((s_first < 0) || (s_first > s_last)) {
149 return ERR_INVAL;
150 }
wdenkf9087a32002-11-03 00:30:25 +0000151
wdenk384ae022002-11-05 00:17:55 +0000152 if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
wdenk47cd00f2003-03-06 13:39:27 +0000153 return ERR_UNKNOWN_FLASH_VENDOR;
wdenk8bde7f72003-06-27 21:31:46 +0000154
wdenk47cd00f2003-03-06 13:39:27 +0000155 prot = 0;
156 for (sect=s_first; sect<=s_last; ++sect) {
wdenk384ae022002-11-05 00:17:55 +0000157 if (info->protect[sect]) prot++;
wdenkf9087a32002-11-03 00:30:25 +0000158 }
wdenk384ae022002-11-05 00:17:55 +0000159
160 if (prot) return ERR_PROTECTED;
wdenkf9087a32002-11-03 00:30:25 +0000161
wdenk47cd00f2003-03-06 13:39:27 +0000162 /*
163 * Disable interrupts which might cause a timeout
164 * here. Remember that our exception vectors are
165 * at address 0 in the flash, and we don't want a
166 * (ticker) exception to happen while the flash
167 * chip is in programming mode.
168 */
wdenkf9087a32002-11-03 00:30:25 +0000169
wdenk47cd00f2003-03-06 13:39:27 +0000170 flag = disable_interrupts();
wdenkf9087a32002-11-03 00:30:25 +0000171
wdenk47cd00f2003-03-06 13:39:27 +0000172 /* Start erase on unprotected sectors */
173 for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
wdenkf9087a32002-11-03 00:30:25 +0000174
wdenk47cd00f2003-03-06 13:39:27 +0000175 printf("Erasing sector %2d ... ", sect);
wdenkf9087a32002-11-03 00:30:25 +0000176
wdenk47cd00f2003-03-06 13:39:27 +0000177 /* arm simple, non interrupt dependent timer */
178 reset_timer_masked();
179
wdenkb98fff12004-02-09 20:51:26 +0000180 if (info->protect[sect] == 0) { /* not protected */
wdenk384ae022002-11-05 00:17:55 +0000181 u32 * volatile addr = (u32 * volatile)(info->start[sect]);
wdenkf9087a32002-11-03 00:30:25 +0000182
wdenkb98fff12004-02-09 20:51:26 +0000183 /* erase sector: */
wdenk384ae022002-11-05 00:17:55 +0000184 /* The strata flashs are aligned side by side on */
185 /* the data bus, so we have to write the commands */
wdenkb98fff12004-02-09 20:51:26 +0000186 /* to both chips here: */
wdenkf9087a32002-11-03 00:30:25 +0000187
wdenk384ae022002-11-05 00:17:55 +0000188 *addr = 0x00200020; /* erase setup */
189 *addr = 0x00D000D0; /* erase confirm */
190
191 while ((*addr & 0x00800080) != 0x00800080) {
wdenk47cd00f2003-03-06 13:39:27 +0000192 if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
wdenk384ae022002-11-05 00:17:55 +0000193 *addr = 0x00B000B0; /* suspend erase*/
194 *addr = 0x00FF00FF; /* read mode */
wdenk47cd00f2003-03-06 13:39:27 +0000195 rc = ERR_TIMOUT;
196 goto outahere;
197 }
198 }
wdenk384ae022002-11-05 00:17:55 +0000199 *addr = 0x00500050; /* clear status register cmd. */
wdenkb98fff12004-02-09 20:51:26 +0000200 *addr = 0x00FF00FF; /* reset to read mode */
wdenk47cd00f2003-03-06 13:39:27 +0000201 }
wdenk47cd00f2003-03-06 13:39:27 +0000202 printf("ok.\n");
203 }
wdenk384ae022002-11-05 00:17:55 +0000204 if (ctrlc()) printf("User Interrupt!\n");
wdenkf9087a32002-11-03 00:30:25 +0000205
wdenkb98fff12004-02-09 20:51:26 +0000206outahere:
wdenk47cd00f2003-03-06 13:39:27 +0000207 /* allow flash to settle - wait 10 ms */
208 udelay_masked(10000);
wdenkf9087a32002-11-03 00:30:25 +0000209
wdenk384ae022002-11-05 00:17:55 +0000210 if (flag) enable_interrupts();
wdenkf9087a32002-11-03 00:30:25 +0000211
wdenk47cd00f2003-03-06 13:39:27 +0000212 return rc;
wdenkf9087a32002-11-03 00:30:25 +0000213}
214
wdenk384ae022002-11-05 00:17:55 +0000215/**
wdenkb98fff12004-02-09 20:51:26 +0000216 * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
wdenkf9087a32002-11-03 00:30:25 +0000217 */
218
wdenkb98fff12004-02-09 20:51:26 +0000219static int write_long (flash_info_t *info, ulong dest, ulong data)
wdenkf9087a32002-11-03 00:30:25 +0000220{
wdenk47cd00f2003-03-06 13:39:27 +0000221 u32 * volatile addr = (u32 * volatile)dest, val;
222 int rc = ERR_OK;
223 int flag;
wdenkf9087a32002-11-03 00:30:25 +0000224
wdenkb98fff12004-02-09 20:51:26 +0000225 /* read array command - just for the case... */
226 *addr = 0x00FF00FF;
227
wdenk384ae022002-11-05 00:17:55 +0000228 /* Check if Flash is (sufficiently) erased */
229 if ((*addr & data) != data) return ERR_NOT_ERASED;
wdenkf9087a32002-11-03 00:30:25 +0000230
wdenk47cd00f2003-03-06 13:39:27 +0000231 /*
232 * Disable interrupts which might cause a timeout
233 * here. Remember that our exception vectors are
234 * at address 0 in the flash, and we don't want a
235 * (ticker) exception to happen while the flash
236 * chip is in programming mode.
237 */
238 flag = disable_interrupts();
wdenkf9087a32002-11-03 00:30:25 +0000239
wdenk47cd00f2003-03-06 13:39:27 +0000240 /* clear status register command */
wdenkb98fff12004-02-09 20:51:26 +0000241 *addr = 0x00500050;
wdenkf9087a32002-11-03 00:30:25 +0000242
wdenk47cd00f2003-03-06 13:39:27 +0000243 /* program set-up command */
wdenkb98fff12004-02-09 20:51:26 +0000244 *addr = 0x00400040;
wdenkf9087a32002-11-03 00:30:25 +0000245
wdenk47cd00f2003-03-06 13:39:27 +0000246 /* latch address/data */
247 *addr = data;
wdenkf9087a32002-11-03 00:30:25 +0000248
wdenk47cd00f2003-03-06 13:39:27 +0000249 /* arm simple, non interrupt dependent timer */
250 reset_timer_masked();
wdenkf9087a32002-11-03 00:30:25 +0000251
wdenk47cd00f2003-03-06 13:39:27 +0000252 /* wait while polling the status register */
wdenkb98fff12004-02-09 20:51:26 +0000253 while(((val = *addr) & 0x00800080) != 0x00800080) {
wdenk47cd00f2003-03-06 13:39:27 +0000254 if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
255 rc = ERR_TIMOUT;
wdenkb98fff12004-02-09 20:51:26 +0000256 /* suspend program command */
257 *addr = 0x00B000B0;
wdenk47cd00f2003-03-06 13:39:27 +0000258 goto outahere;
259 }
wdenkf9087a32002-11-03 00:30:25 +0000260 }
wdenkf9087a32002-11-03 00:30:25 +0000261
wdenkb98fff12004-02-09 20:51:26 +0000262 /* check for errors */
263 if(val & 0x001A001A) {
wdenk47cd00f2003-03-06 13:39:27 +0000264 printf("\nFlash write error %02x at address %08lx\n",
265 (int)val, (unsigned long)dest);
wdenkb98fff12004-02-09 20:51:26 +0000266 if(val & 0x00080008) {
wdenk47cd00f2003-03-06 13:39:27 +0000267 printf("Voltage range error.\n");
268 rc = ERR_PROG_ERROR;
269 goto outahere;
270 }
wdenkb98fff12004-02-09 20:51:26 +0000271 if(val & 0x00020002) {
wdenk47cd00f2003-03-06 13:39:27 +0000272 printf("Device protect error.\n");
273 rc = ERR_PROTECTED;
274 goto outahere;
275 }
wdenkb98fff12004-02-09 20:51:26 +0000276 if(val & 0x00100010) {
wdenk47cd00f2003-03-06 13:39:27 +0000277 printf("Programming error.\n");
278 rc = ERR_PROG_ERROR;
279 goto outahere;
280 }
281 rc = ERR_PROG_ERROR;
282 goto outahere;
283 }
wdenkf9087a32002-11-03 00:30:25 +0000284
wdenkb98fff12004-02-09 20:51:26 +0000285outahere:
286 /* read array command */
287 *addr = 0x00FF00FF;
wdenk384ae022002-11-05 00:17:55 +0000288 if (flag) enable_interrupts();
wdenkf9087a32002-11-03 00:30:25 +0000289
wdenk47cd00f2003-03-06 13:39:27 +0000290 return rc;
wdenkf9087a32002-11-03 00:30:25 +0000291}
292
wdenk384ae022002-11-05 00:17:55 +0000293
294/**
295 * write_buf: - Copy memory to flash.
wdenk8bde7f72003-06-27 21:31:46 +0000296 *
297 * @param info:
wdenk384ae022002-11-05 00:17:55 +0000298 * @param src: source of copy transaction
wdenkb98fff12004-02-09 20:51:26 +0000299 * @param addr: where to copy to
300 * @param cnt: number of bytes to copy
wdenk384ae022002-11-05 00:17:55 +0000301 *
302 * @return error code
wdenkf9087a32002-11-03 00:30:25 +0000303 */
304
wdenkb98fff12004-02-09 20:51:26 +0000305/* "long" version, uses 32bit words */
wdenkf9087a32002-11-03 00:30:25 +0000306int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
307{
wdenk47cd00f2003-03-06 13:39:27 +0000308 ulong cp, wp;
wdenkb98fff12004-02-09 20:51:26 +0000309 ulong data;
wdenk47cd00f2003-03-06 13:39:27 +0000310 int l;
311 int i, rc;
wdenkf9087a32002-11-03 00:30:25 +0000312
wdenkb98fff12004-02-09 20:51:26 +0000313 wp = (addr & ~3); /* get lower word aligned address */
wdenkf9087a32002-11-03 00:30:25 +0000314
wdenk47cd00f2003-03-06 13:39:27 +0000315 /*
316 * handle unaligned start bytes
317 */
318 if ((l = addr - wp) != 0) {
319 data = 0;
320 for (i=0, cp=wp; i<l; ++i, ++cp) {
wdenkb98fff12004-02-09 20:51:26 +0000321 data = (data >> 8) | (*(uchar *)cp << 24);
wdenk47cd00f2003-03-06 13:39:27 +0000322 }
wdenkb98fff12004-02-09 20:51:26 +0000323 for (; i<4 && cnt>0; ++i) {
324 data = (data >> 8) | (*src++ << 24);
wdenk47cd00f2003-03-06 13:39:27 +0000325 --cnt;
326 ++cp;
327 }
wdenkb98fff12004-02-09 20:51:26 +0000328 for (; cnt==0 && i<4; ++i, ++cp) {
329 data = (data >> 8) | (*(uchar *)cp << 24);
wdenk47cd00f2003-03-06 13:39:27 +0000330 }
331
wdenkb98fff12004-02-09 20:51:26 +0000332 if ((rc = write_long(info, wp, data)) != 0) {
wdenk47cd00f2003-03-06 13:39:27 +0000333 return (rc);
334 }
wdenkb98fff12004-02-09 20:51:26 +0000335 wp += 4;
wdenkf9087a32002-11-03 00:30:25 +0000336 }
337
wdenk47cd00f2003-03-06 13:39:27 +0000338 /*
339 * handle word aligned part
340 */
wdenkb98fff12004-02-09 20:51:26 +0000341 while (cnt >= 4) {
342 data = *((ulong*)src);
343 if ((rc = write_long(info, wp, data)) != 0) {
wdenk47cd00f2003-03-06 13:39:27 +0000344 return (rc);
345 }
wdenkb98fff12004-02-09 20:51:26 +0000346 src += 4;
347 wp += 4;
348 cnt -= 4;
wdenkf9087a32002-11-03 00:30:25 +0000349 }
wdenkf9087a32002-11-03 00:30:25 +0000350
wdenk384ae022002-11-05 00:17:55 +0000351 if (cnt == 0) return ERR_OK;
wdenkf9087a32002-11-03 00:30:25 +0000352
wdenk47cd00f2003-03-06 13:39:27 +0000353 /*
354 * handle unaligned tail bytes
355 */
356 data = 0;
wdenkb98fff12004-02-09 20:51:26 +0000357 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
358 data = (data >> 8) | (*src++ << 24);
wdenk47cd00f2003-03-06 13:39:27 +0000359 --cnt;
360 }
wdenkb98fff12004-02-09 20:51:26 +0000361 for (; i<4; ++i, ++cp) {
362 data = (data >> 8) | (*(uchar *)cp << 24);
wdenk47cd00f2003-03-06 13:39:27 +0000363 }
wdenkf9087a32002-11-03 00:30:25 +0000364
wdenkb98fff12004-02-09 20:51:26 +0000365 return write_long(info, wp, data);
wdenkf9087a32002-11-03 00:30:25 +0000366}