| Prabhakar Kushwaha | 41d9101 | 2013-01-14 18:26:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Prabhakar Kushwaha | 41d9101 | 2013-01-14 18:26:57 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/fsl_law.h> |
| 9 | #include <asm/mmu.h> |
| 10 | |
| 11 | struct law_entry law_table[] = { |
| Prabhakar Kushwaha | 41d9101 | 2013-01-14 18:26:57 +0000 | [diff] [blame] | 12 | SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC), |
| Prabhakar Kushwaha | 83e0c2b | 2013-04-16 13:28:40 +0530 | [diff] [blame] | 13 | #ifdef CONFIG_SYS_NAND_BASE_PHYS |
| Prabhakar Kushwaha | 41d9101 | 2013-01-14 18:26:57 +0000 | [diff] [blame] | 14 | SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), |
| Prabhakar Kushwaha | 83e0c2b | 2013-04-16 13:28:40 +0530 | [diff] [blame] | 15 | #endif |
| 16 | #ifdef CONFIG_SYS_FPGA_BASE_PHYS |
| Prabhakar Kushwaha | 41d9101 | 2013-01-14 18:26:57 +0000 | [diff] [blame] | 17 | SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), |
| Prabhakar Kushwaha | 83e0c2b | 2013-04-16 13:28:40 +0530 | [diff] [blame] | 18 | #endif |
| Priyanka Jain | 64501c6 | 2013-07-02 09:21:04 +0530 | [diff] [blame] | 19 | SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, |
| 20 | LAW_TRGT_IF_DSP_CCSR), |
| 21 | SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, |
| 22 | LAW_TRGT_IF_OCN_DSP), |
| 23 | SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, |
| 24 | LAW_TRGT_IF_CLASS_DSP), |
| 25 | SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, |
| 26 | LAW_TRGT_IF_CLASS_DSP) |
| Prabhakar Kushwaha | 41d9101 | 2013-01-14 18:26:57 +0000 | [diff] [blame] | 27 | }; |
| 28 | |
| 29 | int num_law_entries = ARRAY_SIZE(law_table); |