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wdenk6f213472003-08-29 22:00:43 +00001/*
wdenk63e73c92004-02-23 22:22:28 +00002 * (C) Copyright 2003
3 * Texas Instruments <www.ti.com>
4 *
wdenk6f213472003-08-29 22:00:43 +00005 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2002
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Alex Zuepke <azu@sysgo.de>
12 *
wdenk3d3befa2004-03-14 15:06:13 +000013 * (C) Copyright 2002-2004
wdenk6f213472003-08-29 22:00:43 +000014 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
15 *
wdenk3d3befa2004-03-14 15:06:13 +000016 * (C) Copyright 2004
17 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
18 *
wdenk6f213472003-08-29 22:00:43 +000019 * See file CREDITS for list of people who contributed to this
20 * project.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk101e8df2005-04-04 12:08:28 +000029 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk6f213472003-08-29 22:00:43 +000030 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 * MA 02111-1307 USA
36 */
37
38#include <common.h>
39#include <arm925t.h>
wdenk6f213472003-08-29 22:00:43 +000040
41#include <asm/proc-armv/ptrace.h>
42
wdenk6f213472003-08-29 22:00:43 +000043#define TIMER_LOAD_VAL 0xffffffff
44
45/* macro to read the 32 bit timer */
wdenk3d3befa2004-03-14 15:06:13 +000046#ifdef CONFIG_OMAP
wdenk6f213472003-08-29 22:00:43 +000047#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
wdenk3d3befa2004-03-14 15:06:13 +000048#endif
49#ifdef CONFIG_INTEGRATOR
50#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
51#endif
52#ifdef CONFIG_VERSATILE
53#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
54#endif
wdenk6f213472003-08-29 22:00:43 +000055
56#ifdef CONFIG_USE_IRQ
57/* enable IRQ interrupts */
58void enable_interrupts (void)
59{
60 unsigned long temp;
61 __asm__ __volatile__("mrs %0, cpsr\n"
wdenk63e73c92004-02-23 22:22:28 +000062 "bic %0, %0, #0x80\n"
63 "msr cpsr_c, %0"
64 : "=r" (temp)
65 :
66 : "memory");
wdenk6f213472003-08-29 22:00:43 +000067}
68
wdenk63e73c92004-02-23 22:22:28 +000069
wdenk6f213472003-08-29 22:00:43 +000070/*
71 * disable IRQ/FIQ interrupts
72 * returns true if interrupts had been enabled before we disabled them
73 */
74int disable_interrupts (void)
75{
76 unsigned long old,temp;
77 __asm__ __volatile__("mrs %0, cpsr\n"
wdenk63e73c92004-02-23 22:22:28 +000078 "orr %1, %0, #0xc0\n"
79 "msr cpsr_c, %1"
80 : "=r" (old), "=r" (temp)
81 :
82 : "memory");
wdenk6f213472003-08-29 22:00:43 +000083 return (old & 0x80) == 0;
84}
85#else
86void enable_interrupts (void)
87{
88 return;
89}
90int disable_interrupts (void)
91{
92 return 0;
93}
94#endif
95
96
wdenk6f213472003-08-29 22:00:43 +000097void bad_mode (void)
98{
99 panic ("Resetting CPU ...\n");
100 reset_cpu (0);
101}
102
103void show_regs (struct pt_regs *regs)
104{
105 unsigned long flags;
106 const char *processor_modes[] = {
107 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
108 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
109 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
110 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
111 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
112 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
113 "UK8_32", "UK9_32", "UK10_32", "UND_32",
114 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
115 };
116
117 flags = condition_codes (regs);
118
wdenk101e8df2005-04-04 12:08:28 +0000119 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
120 "sp : %08lx ip : %08lx fp : %08lx\n",
wdenk6f213472003-08-29 22:00:43 +0000121 instruction_pointer (regs),
122 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
wdenk101e8df2005-04-04 12:08:28 +0000123 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
wdenk6f213472003-08-29 22:00:43 +0000124 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
wdenk101e8df2005-04-04 12:08:28 +0000125 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
wdenk6f213472003-08-29 22:00:43 +0000126 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
wdenk101e8df2005-04-04 12:08:28 +0000127 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
wdenk6f213472003-08-29 22:00:43 +0000128 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
129 printf ("Flags: %c%c%c%c",
130 flags & CC_N_BIT ? 'N' : 'n',
131 flags & CC_Z_BIT ? 'Z' : 'z',
132 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
133 printf (" IRQs %s FIQs %s Mode %s%s\n",
134 interrupts_enabled (regs) ? "on" : "off",
135 fast_interrupts_enabled (regs) ? "on" : "off",
136 processor_modes[processor_mode (regs)],
137 thumb_mode (regs) ? " (T)" : "");
138}
139
140void do_undefined_instruction (struct pt_regs *pt_regs)
141{
142 printf ("undefined instruction\n");
143 show_regs (pt_regs);
144 bad_mode ();
145}
146
147void do_software_interrupt (struct pt_regs *pt_regs)
148{
149 printf ("software interrupt\n");
150 show_regs (pt_regs);
151 bad_mode ();
152}
153
154void do_prefetch_abort (struct pt_regs *pt_regs)
155{
156 printf ("prefetch abort\n");
157 show_regs (pt_regs);
158 bad_mode ();
159}
160
161void do_data_abort (struct pt_regs *pt_regs)
162{
163 printf ("data abort\n");
164 show_regs (pt_regs);
165 bad_mode ();
166}
167
168void do_not_used (struct pt_regs *pt_regs)
169{
170 printf ("not used\n");
171 show_regs (pt_regs);
172 bad_mode ();
173}
174
175void do_fiq (struct pt_regs *pt_regs)
176{
177 printf ("fast interrupt request\n");
178 show_regs (pt_regs);
179 bad_mode ();
180}
181
182void do_irq (struct pt_regs *pt_regs)
183{
184 printf ("interrupt request\n");
185 show_regs (pt_regs);
186 bad_mode ();
187}
188
189static ulong timestamp;
190static ulong lastdec;
191
192/* nothing really to do with interrupts, just starts up a counter. */
193int interrupt_init (void)
194{
wdenk3d3befa2004-03-14 15:06:13 +0000195#ifdef CONFIG_OMAP
wdenk6f213472003-08-29 22:00:43 +0000196 int32_t val;
197
wdenk63e73c92004-02-23 22:22:28 +0000198 /* Start the decrementer ticking down from 0xffffffff */
wdenk6f213472003-08-29 22:00:43 +0000199 *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
wdenk63e73c92004-02-23 22:22:28 +0000200 val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
wdenk6f213472003-08-29 22:00:43 +0000201 *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
wdenk3d3befa2004-03-14 15:06:13 +0000202#endif /* CONFIG_OMAP */
203#ifdef CONFIG_INTEGRATOR
204 /* Load timer with initial value */
205 *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
206 /* Set timer to be enabled, free-running, no interrupts, 256 divider */
207 *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
208#endif /* CONFIG_INTEGRATOR */
209#ifdef CONFIG_VERSATILE
210 *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */
211 *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */
212 *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
wdenk3d3befa2004-03-14 15:06:13 +0000213#endif /* CONFIG_VERSATILE */
wdenk63e73c92004-02-23 22:22:28 +0000214
215 /* init the timestamp and lastdec value */
216 reset_timer_masked();
217
wdenk6f213472003-08-29 22:00:43 +0000218 return (0);
219}
220
221/*
222 * timer without interrupts
223 */
224
225void reset_timer (void)
226{
227 reset_timer_masked ();
228}
229
230ulong get_timer (ulong base)
231{
232 return get_timer_masked () - base;
233}
234
235void set_timer (ulong t)
236{
237 timestamp = t;
238}
239
wdenk63e73c92004-02-23 22:22:28 +0000240/* delay x useconds AND perserve advance timstamp value */
wdenk6f213472003-08-29 22:00:43 +0000241void udelay (unsigned long usec)
242{
wdenk63e73c92004-02-23 22:22:28 +0000243 ulong tmo, tmp;
wdenk6f213472003-08-29 22:00:43 +0000244
wdenk101e8df2005-04-04 12:08:28 +0000245 if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
246 tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
247 tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
248 tmo /= 1000; /* finish normalize. */
249 }else{ /* else small number, don't kill it prior to HZ multiply */
wdenk63e73c92004-02-23 22:22:28 +0000250 tmo = usec * CFG_HZ;
251 tmo /= (1000*1000);
wdenk6f213472003-08-29 22:00:43 +0000252 }
wdenk6f213472003-08-29 22:00:43 +0000253
wdenk63e73c92004-02-23 22:22:28 +0000254 tmp = get_timer (0); /* get current timestamp */
wdenk101e8df2005-04-04 12:08:28 +0000255 if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
wdenk63e73c92004-02-23 22:22:28 +0000256 reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
257 else
258 tmo += tmp; /* else, set advancing stamp wake up time */
259
260 while (get_timer_masked () < tmo)/* loop till event */
wdenk6f213472003-08-29 22:00:43 +0000261 /*NOP*/;
wdenk6f213472003-08-29 22:00:43 +0000262}
263
264void reset_timer_masked (void)
265{
266 /* reset time */
wdenk63e73c92004-02-23 22:22:28 +0000267 lastdec = READ_TIMER; /* capure current decrementer value time */
wdenk101e8df2005-04-04 12:08:28 +0000268 timestamp = 0; /* start "advancing" time stamp from 0 */
wdenk6f213472003-08-29 22:00:43 +0000269}
270
271ulong get_timer_masked (void)
272{
273 ulong now = READ_TIMER; /* current tick value */
274
wdenk63e73c92004-02-23 22:22:28 +0000275 if (lastdec >= now) { /* normal mode (non roll) */
wdenk6f213472003-08-29 22:00:43 +0000276 /* normal mode */
wdenk63e73c92004-02-23 22:22:28 +0000277 timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
278 } else { /* we have overflow of the count down timer */
279 /* nts = ts + ld + (TLV - now)
280 * ts=old stamp, ld=time that passed before passing through -1
281 * (TLV-now) amount of time after passing though -1
282 * nts = new "advancing time stamp"...it could also roll and cause problems.
283 */
wdenk6f213472003-08-29 22:00:43 +0000284 timestamp += lastdec + TIMER_LOAD_VAL - now;
285 }
286 lastdec = now;
287
288 return timestamp;
289}
290
wdenk63e73c92004-02-23 22:22:28 +0000291/* waits specified delay value and resets timestamp */
wdenk6f213472003-08-29 22:00:43 +0000292void udelay_masked (unsigned long usec)
293{
wdenk42dfe7a2004-03-14 22:25:36 +0000294 ulong tmo;
wdenk101e8df2005-04-04 12:08:28 +0000295 ulong endtime;
296 signed long diff;
wdenk6f213472003-08-29 22:00:43 +0000297
wdenk101e8df2005-04-04 12:08:28 +0000298 if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
299 tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
300 tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
301 tmo /= 1000; /* finish normalize. */
302 } else { /* else small number, don't kill it prior to HZ multiply */
wdenk63e73c92004-02-23 22:22:28 +0000303 tmo = usec * CFG_HZ;
304 tmo /= (1000*1000);
305 }
wdenk6f213472003-08-29 22:00:43 +0000306
wdenk101e8df2005-04-04 12:08:28 +0000307 endtime = get_timer_masked () + tmo;
wdenk6f213472003-08-29 22:00:43 +0000308
wdenk101e8df2005-04-04 12:08:28 +0000309 do {
310 ulong now = get_timer_masked ();
311 diff = endtime - now;
312 } while (diff >= 0);
wdenk6f213472003-08-29 22:00:43 +0000313}
314
315/*
316 * This function is derived from PowerPC code (read timebase as long long).
317 * On ARM it just returns the timer value.
318 */
319unsigned long long get_ticks(void)
320{
321 return get_timer(0);
322}
323
324/*
325 * This function is derived from PowerPC code (timebase clock frequency).
326 * On ARM it returns the number of timer ticks per second.
327 */
328ulong get_tbclk (void)
329{
330 ulong tbclk;
wdenk63e73c92004-02-23 22:22:28 +0000331
wdenk6f213472003-08-29 22:00:43 +0000332 tbclk = CFG_HZ;
333 return tbclk;
334}