Alex Marginean | 120b5ef | 2019-07-03 12:11:40 +0300 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * ENETC ethernet controller driver |
| 4 | * Copyright 2017-2019 NXP |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <dm.h> |
| 9 | #include <errno.h> |
| 10 | #include <memalign.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <pci.h> |
| 13 | |
| 14 | #include "fsl_enetc.h" |
| 15 | |
| 16 | /* |
| 17 | * Bind the device: |
| 18 | * - set a more explicit name on the interface |
| 19 | */ |
| 20 | static int enetc_bind(struct udevice *dev) |
| 21 | { |
| 22 | char name[16]; |
| 23 | static int eth_num_devices; |
| 24 | |
| 25 | /* |
| 26 | * prefer using PCI function numbers to number interfaces, but these |
| 27 | * are only available if dts nodes are present. For PCI they are |
| 28 | * optional, handle that case too. Just in case some nodes are present |
| 29 | * and some are not, use different naming scheme - enetc-N based on |
| 30 | * PCI function # and enetc#N based on interface count |
| 31 | */ |
| 32 | if (ofnode_valid(dev->node)) |
| 33 | sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev))); |
| 34 | else |
| 35 | sprintf(name, "enetc#%u", eth_num_devices++); |
| 36 | device_set_name(dev, name); |
| 37 | |
| 38 | return 0; |
| 39 | } |
| 40 | |
| 41 | /* |
| 42 | * Probe ENETC driver: |
| 43 | * - initialize port and station interface BARs |
| 44 | */ |
| 45 | static int enetc_probe(struct udevice *dev) |
| 46 | { |
| 47 | struct enetc_priv *priv = dev_get_priv(dev); |
| 48 | |
| 49 | if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) { |
| 50 | enetc_dbg(dev, "interface disabled\n"); |
| 51 | return -ENODEV; |
| 52 | } |
| 53 | |
| 54 | priv->enetc_txbd = memalign(ENETC_BD_ALIGN, |
| 55 | sizeof(struct enetc_tx_bd) * ENETC_BD_CNT); |
| 56 | priv->enetc_rxbd = memalign(ENETC_BD_ALIGN, |
| 57 | sizeof(union enetc_rx_bd) * ENETC_BD_CNT); |
| 58 | |
| 59 | if (!priv->enetc_txbd || !priv->enetc_rxbd) { |
| 60 | /* free should be able to handle NULL, just free all pointers */ |
| 61 | free(priv->enetc_txbd); |
| 62 | free(priv->enetc_rxbd); |
| 63 | |
| 64 | return -ENOMEM; |
| 65 | } |
| 66 | |
| 67 | /* initialize register */ |
| 68 | priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0); |
| 69 | if (!priv->regs_base) { |
| 70 | enetc_dbg(dev, "failed to map BAR0\n"); |
| 71 | return -EINVAL; |
| 72 | } |
| 73 | priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF; |
| 74 | |
| 75 | dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | /* |
| 81 | * Remove the driver from an interface: |
| 82 | * - free up allocated memory |
| 83 | */ |
| 84 | static int enetc_remove(struct udevice *dev) |
| 85 | { |
| 86 | struct enetc_priv *priv = dev_get_priv(dev); |
| 87 | |
| 88 | free(priv->enetc_txbd); |
| 89 | free(priv->enetc_rxbd); |
| 90 | |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | /* ENETC Port MAC address registers, accepts big-endian format */ |
| 95 | static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr) |
| 96 | { |
| 97 | u16 lower = *(const u16 *)(addr + 4); |
| 98 | u32 upper = *(const u32 *)addr; |
| 99 | |
| 100 | enetc_write_port(priv, ENETC_PSIPMAR0, upper); |
| 101 | enetc_write_port(priv, ENETC_PSIPMAR1, lower); |
| 102 | } |
| 103 | |
| 104 | /* Configure port parameters (# of rings, frame size, enable port) */ |
| 105 | static void enetc_enable_si_port(struct enetc_priv *priv) |
| 106 | { |
| 107 | u32 val; |
| 108 | |
| 109 | /* set Rx/Tx BDR count */ |
| 110 | val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT); |
| 111 | val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT); |
| 112 | enetc_write_port(priv, ENETC_PSICFGR(0), val); |
| 113 | /* set Rx max frame size */ |
| 114 | enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); |
| 115 | /* enable MAC port */ |
| 116 | enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN); |
| 117 | /* enable port */ |
| 118 | enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN); |
| 119 | /* set SI cache policy */ |
| 120 | enetc_write(priv, ENETC_SICAR0, |
| 121 | ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG); |
| 122 | /* enable SI */ |
| 123 | enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN); |
| 124 | } |
| 125 | |
| 126 | /* returns DMA address for a given buffer index */ |
| 127 | static inline u64 enetc_rxb_address(struct udevice *dev, int i) |
| 128 | { |
| 129 | return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i])); |
| 130 | } |
| 131 | |
| 132 | /* |
| 133 | * Setup a single Tx BD Ring (ID = 0): |
| 134 | * - set Tx buffer descriptor address |
| 135 | * - set the BD count |
| 136 | * - initialize the producer and consumer index |
| 137 | */ |
| 138 | static void enetc_setup_tx_bdr(struct udevice *dev) |
| 139 | { |
| 140 | struct enetc_priv *priv = dev_get_priv(dev); |
| 141 | struct bd_ring *tx_bdr = &priv->tx_bdr; |
| 142 | u64 tx_bd_add = (u64)priv->enetc_txbd; |
| 143 | |
| 144 | /* used later to advance to the next Tx BD */ |
| 145 | tx_bdr->bd_count = ENETC_BD_CNT; |
| 146 | tx_bdr->next_prod_idx = 0; |
| 147 | tx_bdr->next_cons_idx = 0; |
| 148 | tx_bdr->cons_idx = priv->regs_base + |
| 149 | ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR); |
| 150 | tx_bdr->prod_idx = priv->regs_base + |
| 151 | ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR); |
| 152 | |
| 153 | /* set Tx BD address */ |
| 154 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0, |
| 155 | lower_32_bits(tx_bd_add)); |
| 156 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1, |
| 157 | upper_32_bits(tx_bd_add)); |
| 158 | /* set Tx 8 BD count */ |
| 159 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR, |
| 160 | tx_bdr->bd_count); |
| 161 | |
| 162 | /* reset both producer/consumer indexes */ |
| 163 | enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx); |
| 164 | enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx); |
| 165 | |
| 166 | /* enable TX ring */ |
| 167 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN); |
| 168 | } |
| 169 | |
| 170 | /* |
| 171 | * Setup a single Rx BD Ring (ID = 0): |
| 172 | * - set Rx buffer descriptors address (one descriptor per buffer) |
| 173 | * - set buffer size as max frame size |
| 174 | * - enable Rx ring |
| 175 | * - reset consumer and producer indexes |
| 176 | * - set buffer for each descriptor |
| 177 | */ |
| 178 | static void enetc_setup_rx_bdr(struct udevice *dev) |
| 179 | { |
| 180 | struct enetc_priv *priv = dev_get_priv(dev); |
| 181 | struct bd_ring *rx_bdr = &priv->rx_bdr; |
| 182 | u64 rx_bd_add = (u64)priv->enetc_rxbd; |
| 183 | int i; |
| 184 | |
| 185 | /* used later to advance to the next BD produced by ENETC HW */ |
| 186 | rx_bdr->bd_count = ENETC_BD_CNT; |
| 187 | rx_bdr->next_prod_idx = 0; |
| 188 | rx_bdr->next_cons_idx = 0; |
| 189 | rx_bdr->cons_idx = priv->regs_base + |
| 190 | ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR); |
| 191 | rx_bdr->prod_idx = priv->regs_base + |
| 192 | ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR); |
| 193 | |
| 194 | /* set Rx BD address */ |
| 195 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0, |
| 196 | lower_32_bits(rx_bd_add)); |
| 197 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1, |
| 198 | upper_32_bits(rx_bd_add)); |
| 199 | /* set Rx BD count (multiple of 8) */ |
| 200 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR, |
| 201 | rx_bdr->bd_count); |
| 202 | /* set Rx buffer size */ |
| 203 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN); |
| 204 | |
| 205 | /* fill Rx BD */ |
| 206 | memset(priv->enetc_rxbd, 0, |
| 207 | rx_bdr->bd_count * sizeof(union enetc_rx_bd)); |
| 208 | for (i = 0; i < rx_bdr->bd_count; i++) { |
| 209 | priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i); |
| 210 | /* each RX buffer must be aligned to 64B */ |
| 211 | WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1)); |
| 212 | } |
| 213 | |
| 214 | /* reset producer (ENETC owned) and consumer (SW owned) index */ |
| 215 | enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx); |
| 216 | enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx); |
| 217 | |
| 218 | /* enable Rx ring */ |
| 219 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN); |
| 220 | } |
| 221 | |
| 222 | /* |
| 223 | * Start ENETC interface: |
| 224 | * - perform FLR |
| 225 | * - enable access to port and SI registers |
| 226 | * - set mac address |
| 227 | * - setup TX/RX buffer descriptors |
| 228 | * - enable Tx/Rx rings |
| 229 | */ |
| 230 | static int enetc_start(struct udevice *dev) |
| 231 | { |
| 232 | struct eth_pdata *plat = dev_get_platdata(dev); |
| 233 | struct enetc_priv *priv = dev_get_priv(dev); |
| 234 | |
| 235 | /* reset and enable the PCI device */ |
| 236 | dm_pci_flr(dev); |
| 237 | dm_pci_clrset_config16(dev, PCI_COMMAND, 0, |
| 238 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 239 | |
| 240 | if (!is_valid_ethaddr(plat->enetaddr)) { |
| 241 | enetc_dbg(dev, "invalid MAC address, generate random ...\n"); |
| 242 | net_random_ethaddr(plat->enetaddr); |
| 243 | } |
| 244 | enetc_set_primary_mac_addr(priv, plat->enetaddr); |
| 245 | |
| 246 | enetc_enable_si_port(priv); |
| 247 | |
| 248 | /* setup Tx/Rx buffer descriptors */ |
| 249 | enetc_setup_tx_bdr(dev); |
| 250 | enetc_setup_rx_bdr(dev); |
| 251 | |
| 252 | return 0; |
| 253 | } |
| 254 | |
| 255 | /* |
| 256 | * Stop the network interface: |
| 257 | * - just quiesce it, we can wipe all configuration as _start starts from |
| 258 | * scratch each time |
| 259 | */ |
| 260 | static void enetc_stop(struct udevice *dev) |
| 261 | { |
| 262 | /* FLR is sufficient to quiesce the device */ |
| 263 | dm_pci_flr(dev); |
| 264 | } |
| 265 | |
| 266 | /* |
| 267 | * ENETC transmit packet: |
| 268 | * - check if Tx BD ring is full |
| 269 | * - set buffer/packet address (dma address) |
| 270 | * - set final fragment flag |
| 271 | * - try while producer index equals consumer index or timeout |
| 272 | */ |
| 273 | static int enetc_send(struct udevice *dev, void *packet, int length) |
| 274 | { |
| 275 | struct enetc_priv *priv = dev_get_priv(dev); |
| 276 | struct bd_ring *txr = &priv->tx_bdr; |
| 277 | void *nv_packet = (void *)packet; |
| 278 | int tries = ENETC_POLL_TRIES; |
| 279 | u32 pi, ci; |
| 280 | |
| 281 | pi = txr->next_prod_idx; |
| 282 | ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK; |
| 283 | /* Tx ring is full when */ |
| 284 | if (((pi + 1) % txr->bd_count) == ci) { |
| 285 | enetc_dbg(dev, "Tx BDR full\n"); |
| 286 | return -ETIMEDOUT; |
| 287 | } |
| 288 | enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length, |
| 289 | upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet)); |
| 290 | |
| 291 | /* prepare Tx BD */ |
| 292 | memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd)); |
| 293 | priv->enetc_txbd[pi].addr = |
| 294 | cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet)); |
| 295 | priv->enetc_txbd[pi].buf_len = cpu_to_le16(length); |
| 296 | priv->enetc_txbd[pi].frm_len = cpu_to_le16(length); |
| 297 | priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F); |
| 298 | dmb(); |
| 299 | /* send frame: increment producer index */ |
| 300 | pi = (pi + 1) % txr->bd_count; |
| 301 | txr->next_prod_idx = pi; |
| 302 | enetc_write_reg(txr->prod_idx, pi); |
| 303 | while ((--tries >= 0) && |
| 304 | (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK))) |
| 305 | udelay(10); |
| 306 | |
| 307 | return tries > 0 ? 0 : -ETIMEDOUT; |
| 308 | } |
| 309 | |
| 310 | /* |
| 311 | * Receive frame: |
| 312 | * - wait for the next BD to get ready bit set |
| 313 | * - clean up the descriptor |
| 314 | * - move on and indicate to HW that the cleaned BD is available for Rx |
| 315 | */ |
| 316 | static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) |
| 317 | { |
| 318 | struct enetc_priv *priv = dev_get_priv(dev); |
| 319 | struct bd_ring *rxr = &priv->rx_bdr; |
| 320 | int tries = ENETC_POLL_TRIES; |
| 321 | int pi = rxr->next_prod_idx; |
| 322 | int ci = rxr->next_cons_idx; |
| 323 | u32 status; |
| 324 | int len; |
| 325 | u8 rdy; |
| 326 | |
| 327 | do { |
| 328 | dmb(); |
| 329 | status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus); |
| 330 | /* check if current BD is ready to be consumed */ |
| 331 | rdy = ENETC_RXBD_STATUS_R(status); |
| 332 | } while (--tries >= 0 && !rdy); |
| 333 | |
| 334 | if (!rdy) |
| 335 | return -EAGAIN; |
| 336 | |
| 337 | dmb(); |
| 338 | len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len); |
| 339 | *packetp = (uchar *)enetc_rxb_address(dev, pi); |
| 340 | enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len, |
| 341 | ENETC_RXBD_STATUS_ERRORS(status), |
| 342 | upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp)); |
| 343 | |
| 344 | /* BD clean up and advance to next in ring */ |
| 345 | memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd)); |
| 346 | priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi); |
| 347 | rxr->next_prod_idx = (pi + 1) % rxr->bd_count; |
| 348 | ci = (ci + 1) % rxr->bd_count; |
| 349 | rxr->next_cons_idx = ci; |
| 350 | dmb(); |
| 351 | /* free up the slot in the ring for HW */ |
| 352 | enetc_write_reg(rxr->cons_idx, ci); |
| 353 | |
| 354 | return len; |
| 355 | } |
| 356 | |
| 357 | static const struct eth_ops enetc_ops = { |
| 358 | .start = enetc_start, |
| 359 | .send = enetc_send, |
| 360 | .recv = enetc_recv, |
| 361 | .stop = enetc_stop, |
| 362 | }; |
| 363 | |
| 364 | U_BOOT_DRIVER(eth_enetc) = { |
| 365 | .name = "enetc_eth", |
| 366 | .id = UCLASS_ETH, |
| 367 | .bind = enetc_bind, |
| 368 | .probe = enetc_probe, |
| 369 | .remove = enetc_remove, |
| 370 | .ops = &enetc_ops, |
| 371 | .priv_auto_alloc_size = sizeof(struct enetc_priv), |
| 372 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), |
| 373 | }; |
| 374 | |
| 375 | static struct pci_device_id enetc_ids[] = { |
| 376 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) }, |
| 377 | {} |
| 378 | }; |
| 379 | |
| 380 | U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids); |