| Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 1 | CONFIG_X86=y |
| Simon Glass | c1446ac | 2015-09-08 17:52:45 -0600 | [diff] [blame] | 2 | CONFIG_SYS_MALLOC_F_LEN=0x1800 |
| Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 3 | CONFIG_VENDOR_GOOGLE=y |
| Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 4 | CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" |
| Joe Hershberger | bd328eb | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 5 | CONFIG_TARGET_CHROMEBOOK_LINK=y |
| Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 6 | CONFIG_HAVE_MRC=y |
| Bin Meng | f6220f1 | 2015-10-11 21:37:36 -0700 | [diff] [blame] | 7 | CONFIG_ENABLE_MRC_CACHE=y |
| Bin Meng | 786a08e | 2015-07-06 16:31:33 +0800 | [diff] [blame] | 8 | CONFIG_HAVE_VGA_BIOS=y |
| Joe Hershberger | ef0f2f5 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 9 | # CONFIG_CMD_IMLS is not set |
| 10 | # CONFIG_CMD_FLASH is not set |
| Thomas Chou | e4aa8ed | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 11 | CONFIG_CMD_GPIO=y |
| Joe Hershberger | ef0f2f5 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 12 | # CONFIG_CMD_SETEXPR is not set |
| 13 | # CONFIG_CMD_NFS is not set |
| Joe Hershberger | c9bb942 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 14 | CONFIG_BOOTSTAGE=y |
| 15 | CONFIG_BOOTSTAGE_REPORT=y |
| 16 | CONFIG_CMD_BOOTSTAGE=y |
| Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 17 | CONFIG_CMD_TPM=y |
| Simon Glass | eddb8cf | 2015-08-22 18:31:43 -0600 | [diff] [blame] | 18 | CONFIG_CMD_TPM_TEST=y |
| Joe Hershberger | bd328eb | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 19 | CONFIG_OF_CONTROL=y |
| Simon Glass | ca4435e | 2015-07-27 15:47:22 -0600 | [diff] [blame] | 20 | CONFIG_CMD_CROS_EC=y |
| 21 | CONFIG_CROS_EC=y |
| 22 | CONFIG_CROS_EC_LPC=y |
| Bin Meng | 80df691 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 23 | CONFIG_SPI_FLASH=y |
| Bin Meng | 68d5342 | 2015-11-25 05:34:54 -0800 | [diff] [blame] | 24 | CONFIG_SPI_FLASH_GIGADEVICE=y |
| 25 | CONFIG_SPI_FLASH_MACRONIX=y |
| 26 | CONFIG_SPI_FLASH_WINBOND=y |
| Bin Meng | 80df691 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 27 | CONFIG_DM_PCI=y |
| 28 | CONFIG_DM_RTC=y |
| Simon Glass | 7b95252 | 2015-10-18 19:51:27 -0600 | [diff] [blame] | 29 | CONFIG_DEBUG_UART=y |
| 30 | CONFIG_DEBUG_UART_BASE=0x3f8 |
| 31 | CONFIG_DEBUG_UART_CLOCK=1843200 |
| 32 | CONFIG_DEBUG_UART_BOARD_INIT=y |
| Thomas Chou | 9e39003 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 33 | CONFIG_SYS_NS16550=y |
| Bin Meng | e5d5d44 | 2015-11-25 05:34:53 -0800 | [diff] [blame] | 34 | CONFIG_ICH_SPI=y |
| Bin Meng | 80af398 | 2015-11-13 00:11:22 -0800 | [diff] [blame] | 35 | CONFIG_TIMER=y |
| Simon Glass | 26468d5 | 2015-08-22 18:31:20 -0600 | [diff] [blame] | 36 | CONFIG_TPM_TIS_LPC=y |
| Joe Hershberger | bd328eb | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 37 | CONFIG_VIDEO_VESA=y |
| Joe Hershberger | c9bb942 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 38 | CONFIG_FRAMEBUFFER_SET_VESA_MODE=y |
| 39 | CONFIG_FRAMEBUFFER_VESA_MODE_11A=y |
| 40 | CONFIG_USE_PRIVATE_LIBGCC=y |
| Simon Glass | 26468d5 | 2015-08-22 18:31:20 -0600 | [diff] [blame] | 41 | CONFIG_TPM=y |