blob: 264e9b6080034371e92643284d30008231e6e6d5 [file] [log] [blame]
Aubrey Li26bf7de2007-03-19 01:24:52 +08001/*
2 * U-boot - start.S Startup file of u-boot for BF537
3 *
4 * Copyright (c) 2005 blackfin.uclinux.org
5 *
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33/*
34 * Note: A change in this file subsequently requires a change in
35 * board/$(board_name)/config.mk for a valid u-boot.bin
36 */
37
38#define ASSEMBLY
39
40#include <linux/config.h>
41#include <config.h>
42#include <asm/blackfin.h>
43
44.global _stext;
45.global __bss_start;
46.global start;
47.global _start;
48.global _rambase;
49.global _ramstart;
50.global _ramend;
51.global _bf533_data_dest;
52.global _bf533_data_size;
53.global edata;
54.global _initialize;
55.global _exit;
56.global flashdataend;
57.global init_sdram;
58.global _icache_enable;
59.global _dcache_enable;
60#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
61.global _memory_post_test;
62.global _post_flag;
63#endif
64
65#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
66#if (CONFIG_CCLK_DIV == 1)
67#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
68#endif
69#if (CONFIG_CCLK_DIV == 2)
70#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
71#endif
72#if (CONFIG_CCLK_DIV == 4)
73#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
74#endif
75#if (CONFIG_CCLK_DIV == 8)
76#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
77#endif
78#ifndef CONFIG_CCLK_ACT_DIV
79#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
80#endif
81#endif
82
83.text
84_start:
85start:
86_stext:
87
88 R0 = 0x32;
89 SYSCFG = R0;
90 SSYNC;
91
92 /* As per HW reference manual DAG registers,
93 * DATA and Address resgister shall be zero'd
94 * in initialization, after a reset state
95 */
96 r1 = 0; /* Data registers zero'd */
97 r2 = 0;
98 r3 = 0;
99 r4 = 0;
100 r5 = 0;
101 r6 = 0;
102 r7 = 0;
103
104 p0 = 0; /* Address registers zero'd */
105 p1 = 0;
106 p2 = 0;
107 p3 = 0;
108 p4 = 0;
109 p5 = 0;
110
111 i0 = 0; /* DAG Registers zero'd */
112 i1 = 0;
113 i2 = 0;
114 i3 = 0;
115 m0 = 0;
116 m1 = 0;
117 m3 = 0;
118 m3 = 0;
119 l0 = 0;
120 l1 = 0;
121 l2 = 0;
122 l3 = 0;
123 b0 = 0;
124 b1 = 0;
125 b2 = 0;
126 b3 = 0;
127
128 /* Set loop counters to zero, to make sure that
129 * hw loops are disabled.
130 */
131 r0 = 0;
132 lc0 = r0;
133 lc1 = r0;
134
135 SSYNC;
136
137 /* Check soft reset status */
138 p0.h = SWRST >> 16;
139 p0.l = SWRST & 0xFFFF;
140 r0.l = w[p0];
141
142 cc = bittst(r0, 15);
143 if !cc jump no_soft_reset;
144
145 /* Clear Soft reset */
146 r0 = 0x0000;
147 w[p0] = r0;
148 ssync;
149
150no_soft_reset:
151 nop;
152
153 /* Clear EVT registers */
154 p0.h = (EVT_EMULATION_ADDR >> 16);
155 p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
156 p0 += 8;
157 p1 = 14;
158 r1 = 0;
159 LSETUP(4,4) lc0 = p1;
160 [ p0 ++ ] = r1;
161
162#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
163 p0.h = hi(SIC_IWR);
164 p0.l = lo(SIC_IWR);
165 r0.l = 0x1;
166 w[p0] = r0.l;
167 SSYNC;
168#endif
169
170#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
171
172 p0.h = hi(SIC_IWR);
173 p0.l = lo(SIC_IWR);
174 r0.l = 0x1;
175 w[p0] = r0.l;
176 SSYNC;
177
178 /*
179 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
180 */
181 p0.h = hi(PLL_LOCKCNT);
182 p0.l = lo(PLL_LOCKCNT);
183 r0 = 0x300(Z);
184 w[p0] = r0.l;
185 ssync;
186
187 /*
188 * Put SDRAM in self-refresh, incase anything is running
189 */
190 P2.H = hi(EBIU_SDGCTL);
191 P2.L = lo(EBIU_SDGCTL);
192 R0 = [P2];
193 BITSET (R0, 24);
194 [P2] = R0;
195 SSYNC;
196
197 /*
198 * Set PLL_CTL with the value that we calculate in R0
199 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
200 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
201 * - [7] = output delay (add 200ps of delay to mem signals)
202 * - [6] = input delay (add 200ps of input delay to mem signals)
203 * - [5] = PDWN : 1=All Clocks off
204 * - [3] = STOPCK : 1=Core Clock off
205 * - [1] = PLL_OFF : 1=Disable Power to PLL
206 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
207 * all other bits set to zero
208 */
209
210 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
211 r0 = r0 << 9; /* Shift it over, */
212 r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
213 r0 = r1 | r0;
214 r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
215 r1 = r1 << 8; /* Shift it over */
216 r0 = r1 | r0; /* add them all together */
217
218 p0.h = hi(PLL_CTL);
219 p0.l = lo(PLL_CTL); /* Load the address */
220 cli r2; /* Disable interrupts */
221 ssync;
222 w[p0] = r0.l; /* Set the value */
223 idle; /* Wait for the PLL to stablize */
224 sti r2; /* Enable interrupts */
225
226check_again:
227 p0.h = hi(PLL_STAT);
228 p0.l = lo(PLL_STAT);
229 R0 = W[P0](Z);
230 CC = BITTST(R0,5);
231 if ! CC jump check_again;
232
233 /* Configure SCLK & CCLK Dividers */
234 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
235 p0.h = hi(PLL_DIV);
236 p0.l = lo(PLL_DIV);
237 w[p0] = r0.l;
238 ssync;
239#endif
240
241 /*
242 * We now are running at speed, time to set the Async mem bank wait states
243 * This will speed up execution, since we are normally running from FLASH.
244 * we need to read MAC address from FLASH
245 */
246 p2.h = (EBIU_AMBCTL1 >> 16);
247 p2.l = (EBIU_AMBCTL1 & 0xFFFF);
248 r0.h = (AMBCTL1VAL >> 16);
249 r0.l = (AMBCTL1VAL & 0xFFFF);
250 [p2] = r0;
251 ssync;
252
253 p2.h = (EBIU_AMBCTL0 >> 16);
254 p2.l = (EBIU_AMBCTL0 & 0xFFFF);
255 r0.h = (AMBCTL0VAL >> 16);
256 r0.l = (AMBCTL0VAL & 0xFFFF);
257 [p2] = r0;
258 ssync;
259
260 p2.h = (EBIU_AMGCTL >> 16);
261 p2.l = (EBIU_AMGCTL & 0xffff);
262 r0 = AMGCTLVAL;
263 w[p2] = r0;
264 ssync;
265
266#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
267 sp.l = (0xffb01000 & 0xFFFF);
268 sp.h = (0xffb01000 >> 16);
269
270 call init_sdram;
271#endif
272
273
274#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
275 /* DMA POST code to Hi of L1 SRAM */
276postcopy:
277 /* P1 Points to the beginning of SYSTEM MMR Space */
278 P1.H = hi(SYSMMR_BASE);
279 P1.L = lo(SYSMMR_BASE);
280
281 R0.H = _text_l1;
282 R0.L = _text_l1;
283 R1.H = _etext_l1;
284 R1.L = _etext_l1;
285 R2 = R1 - R0; /* Count */
286 R0.H = _etext;
287 R0.L = _etext;
288 R1.H = (CFG_MONITOR_BASE >> 16);
289 R1.L = (CFG_MONITOR_BASE & 0xFFFF);
290 R0 = R0 - R1;
291 R1.H = (CFG_FLASH_BASE >> 16);
292 R1.L = (CFG_FLASH_BASE & 0xFFFF);
293 R0 = R0 + R1; /* Source Address */
294 R1.H = hi(L1_ISRAM); /* Destination Address (high) */
295 R1.L = lo(L1_ISRAM); /* Destination Address (low) */
296 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
297 /* Destination DMAConfig Value (8-bit words) */
298 R4.L = (DI_EN | WNR | DMAEN);
299
300 R6 = 0x1 (Z);
301 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
302 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
303
304 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
305 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
306 /* Set Source DMAConfig = DMA Enable,
307 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
308 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
309
310 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
311 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
312 /* Set Destination DMAConfig = DMA Enable,
313 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
314 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
315
316POST_DMA_DONE:
317 p0.h = hi(MDMA_D0_IRQ_STATUS);
318 p0.l = lo(MDMA_D0_IRQ_STATUS);
319 R0 = W[P0](Z);
320 CC = BITTST(R0, 0);
321 if ! CC jump POST_DMA_DONE
322
323 R0 = 0x1;
324 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
325
326 /* DMA POST data to Hi of L1 SRAM */
327 R0.H = _rodata_l1;
328 R0.L = _rodata_l1;
329 R1.H = _erodata_l1;
330 R1.L = _erodata_l1;
331 R2 = R1 - R0; /* Count */
332 R0.H = _erodata;
333 R0.L = _erodata;
334 R1.H = (CFG_MONITOR_BASE >> 16);
335 R1.L = (CFG_MONITOR_BASE & 0xFFFF);
336 R0 = R0 - R1;
337 R1.H = (CFG_FLASH_BASE >> 16);
338 R1.L = (CFG_FLASH_BASE & 0xFFFF);
339 R0 = R0 + R1; /* Source Address */
340 R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
341 R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
342 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
343 R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
344
345 R6 = 0x1 (Z);
346 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
347 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
348
349 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
350 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
351 /* Set Source DMAConfig = DMA Enable,
352 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
353 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
354
355 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
356 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
357 /* Set Destination DMAConfig = DMA Enable,
358 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
359 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
360
361POST_DATA_DMA_DONE:
362 p0.h = hi(MDMA_D0_IRQ_STATUS);
363 p0.l = lo(MDMA_D0_IRQ_STATUS);
364 R0 = W[P0](Z);
365 CC = BITTST(R0, 0);
366 if ! CC jump POST_DATA_DMA_DONE
367
368 R0 = 0x1;
369 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
370
371 p0.l = _memory_post_test;
372 p0.h = _memory_post_test;
373 r0 = 0x0;
374 call (p0);
375 r7 = r0; /* save return value */
376
377 call init_sdram;
378#endif
379
380 /* relocate into to RAM */
381 call get_pc;
382offset:
383 r2.l = offset;
384 r2.h = offset;
385 r3.l = start;
386 r3.h = start;
387 r1 = r2 - r3;
388
389 r0 = r0 - r1;
390 p1 = r0;
391
392 p2.l = (CFG_MONITOR_BASE & 0xffff);
393 p2.h = (CFG_MONITOR_BASE >> 16);
394
395 p3 = 0x04;
396 p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
397 p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
398loop1:
399 r1 = [p1 ++ p3];
400 [p2 ++ p3] = r1;
401 cc=p2==p4;
402 if !cc jump loop1;
403 /*
404 * configure STACK
405 */
406 r0.h = (CONFIG_STACKBASE >> 16);
407 r0.l = (CONFIG_STACKBASE & 0xFFFF);
408 sp = r0;
409 fp = sp;
410
411 /*
412 * This next section keeps the processor in supervisor mode
413 * during kernel boot. Switches to user mode at end of boot.
414 * See page 3-9 of Hardware Reference manual for documentation.
415 */
416
417 /* To keep ourselves in the supervisor mode */
418 p0.l = (EVT_IVG15_ADDR & 0xFFFF);
419 p0.h = (EVT_IVG15_ADDR >> 16);
420
421 p1.l = _real_start;
422 p1.h = _real_start;
423 [p0] = p1;
424
425 p0.l = (IMASK & 0xFFFF);
426 p0.h = (IMASK >> 16);
427 r0.l = LO(IVG15_POS);
428 r0.h = HI(IVG15_POS);
429 [p0] = r0;
430 raise 15;
431 p0.l = WAIT_HERE;
432 p0.h = WAIT_HERE;
433 reti = p0;
434 rti;
435
436WAIT_HERE:
437 jump WAIT_HERE;
438
439.global _real_start;
440_real_start:
441 [ -- sp ] = reti;
442
443#ifdef CONFIG_BF537
444/* Initialise General-Purpose I/O Modules on BF537
445 * Rev 0.0 Anomaly 05000212 - PORTx_FER,
446 * PORT_MUX Registers Do Not accept "writes" correctly
447 */
448 p0.h = hi(PORTF_FER);
449 p0.l = lo(PORTF_FER);
450 R0.L = W[P0]; /* Read */
451 nop;
452 nop;
453 nop;
454 ssync;
455 R0 = 0x000F(Z);
456 W[P0] = R0.L; /* Write */
457 nop;
458 nop;
459 nop;
460 ssync;
461 W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
462 nop;
463 nop;
464 nop;
465 ssync;
466
467 p0.h = hi(PORTH_FER);
468 p0.l = lo(PORTH_FER);
469 R0.L = W[P0]; /* Read */
470 nop;
471 nop;
472 nop;
473 ssync;
474 R0 = 0xFFFF(Z);
475 W[P0] = R0.L; /* Write */
476 nop;
477 nop;
478 nop;
479 ssync;
480 W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
481 nop;
482 nop;
483 nop;
484 ssync;
485
486#endif
487
488 /* DMA reset code to Hi of L1 SRAM */
489copy:
490 P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
491 P1.L = lo(SYSMMR_BASE);
492
493 R0.H = reset_start; /* Source Address (high) */
494 R0.L = reset_start; /* Source Address (low) */
495 R1.H = reset_end;
496 R1.L = reset_end;
497 R2 = R1 - R0; /* Count */
498 R1.H = hi(L1_ISRAM); /* Destination Address (high) */
499 R1.L = lo(L1_ISRAM); /* Destination Address (low) */
500 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
501 R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
502
503DMA:
504 R6 = 0x1 (Z);
505 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
506 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
507
508 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
509 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
510 /* Set Source DMAConfig = DMA Enable,
511 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
512 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
513
514 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
515 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
516 /* Set Destination DMAConfig = DMA Enable,
517 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
518 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
519
520WAIT_DMA_DONE:
521 p0.h = hi(MDMA_D0_IRQ_STATUS);
522 p0.l = lo(MDMA_D0_IRQ_STATUS);
523 R0 = W[P0](Z);
524 CC = BITTST(R0, 0);
525 if ! CC jump WAIT_DMA_DONE
526
527 R0 = 0x1;
528 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
529
530 /* Initialize BSS Section with 0 s */
531 p1.l = __bss_start;
532 p1.h = __bss_start;
533 p2.l = _end;
534 p2.h = _end;
535 r1 = p1;
536 r2 = p2;
537 r3 = r2 - r1;
538 r3 = r3 >> 2;
539 p3 = r3;
540 lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
541 CC = p2<=p1;
542 if CC jump _clear_bss_skip;
543 r0 = 0;
544_clear_bss:
545_clear_bss_end:
546 [p1++] = r0;
547_clear_bss_skip:
548
549#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
550 p0.l = _post_flag;
551 p0.h = _post_flag;
552 r0 = r7;
553 [p0] = r0;
554#endif
555
556 p0.l = _start1;
557 p0.h = _start1;
558 jump (p0);
559
560reset_start:
561 p0.h = WDOG_CNT >> 16;
562 p0.l = WDOG_CNT & 0xffff;
563 r0 = 0x0010;
564 w[p0] = r0;
565 p0.h = WDOG_CTL >> 16;
566 p0.l = WDOG_CTL & 0xffff;
567 r0 = 0x0000;
568 w[p0] = r0;
569reset_wait:
570 jump reset_wait;
571
572reset_end:
573 nop;
574
575_exit:
576 jump.s _exit;
577get_pc:
578 r0 = rets;
579 rts;