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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkad5bb452007-03-06 18:08:43 +01002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkad5bb452007-03-06 18:08:43 +01005 */
6
7#include <common.h>
Simon Glass36bf4462019-11-14 12:57:42 -07008#include <irq_func.h>
Wolfgang Denkad5bb452007-03-06 18:08:43 +01009
10/*
11 * CPU test
12 * Shift instructions: rlwinm
13 *
14 * The test contains a pre-built table of instructions, operands and
15 * expected results. For each table entry, the test will cyclically use
16 * different sets of operand registers and result registers.
17 */
18
Wolfgang Denkad5bb452007-03-06 18:08:43 +010019#include <post.h>
20#include "cpu_asm.h"
21
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkad5bb452007-03-06 18:08:43 +010023
24extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
25extern ulong cpu_post_makecr (long v);
26
27static struct cpu_post_rlwinm_s
28{
29 ulong cmd;
30 ulong op1;
31 uchar op2;
32 uchar mb;
33 uchar me;
34 ulong res;
35} cpu_post_rlwinm_table[] =
36{
37 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020038 OP_RLWINM,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010039 0xffff0000,
40 24,
41 16,
42 23,
43 0x0000ff00
44 },
45};
Mike Frysingerd2397812011-05-10 07:28:35 +000046static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table);
Wolfgang Denkad5bb452007-03-06 18:08:43 +010047
48int cpu_post_test_rlwinm (void)
49{
50 int ret = 0;
51 unsigned int i, reg;
52 int flag = disable_interrupts();
53
54 for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
55 {
56 struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
57
58 for (reg = 0; reg < 32 && ret == 0; reg++)
59 {
60 unsigned int reg0 = (reg + 0) % 32;
61 unsigned int reg1 = (reg + 1) % 32;
62 unsigned int stk = reg < 16 ? 31 : 15;
Wolfgang Denk53677ef2008-05-20 16:00:29 +020063 unsigned long code[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +010064 {
65 ASM_STW(stk, 1, -4),
66 ASM_ADDI(stk, 1, -16),
67 ASM_STW(3, stk, 8),
68 ASM_STW(reg0, stk, 4),
69 ASM_STW(reg1, stk, 0),
70 ASM_LWZ(reg0, stk, 8),
71 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
72 ASM_STW(reg1, stk, 8),
73 ASM_LWZ(reg1, stk, 0),
74 ASM_LWZ(reg0, stk, 4),
75 ASM_LWZ(3, stk, 8),
76 ASM_ADDI(1, stk, 16),
77 ASM_LWZ(stk, 1, -4),
78 ASM_BLR,
79 };
Wolfgang Denk53677ef2008-05-20 16:00:29 +020080 unsigned long codecr[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +010081 {
82 ASM_STW(stk, 1, -4),
83 ASM_ADDI(stk, 1, -16),
84 ASM_STW(3, stk, 8),
85 ASM_STW(reg0, stk, 4),
86 ASM_STW(reg1, stk, 0),
87 ASM_LWZ(reg0, stk, 8),
88 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
89 test->me) | BIT_C,
90 ASM_STW(reg1, stk, 8),
91 ASM_LWZ(reg1, stk, 0),
92 ASM_LWZ(reg0, stk, 4),
93 ASM_LWZ(3, stk, 8),
94 ASM_ADDI(1, stk, 16),
95 ASM_LWZ(stk, 1, -4),
96 ASM_BLR,
97 };
98 ulong res;
99 ulong cr;
100
101 if (ret == 0)
102 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200103 cr = 0;
104 cpu_post_exec_21 (code, & cr, & res, test->op1);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100105
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200106 ret = res == test->res && cr == 0 ? 0 : -1;
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100107
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200108 if (ret != 0)
109 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200110 post_log ("Error at rlwinm test %d !\n", i);
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200111 }
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100112 }
113
114 if (ret == 0)
115 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200116 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100117
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200118 ret = res == test->res &&
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100119 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
120
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200121 if (ret != 0)
122 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200123 post_log ("Error at rlwinm test %d !\n", i);
124 }
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100125 }
126 }
127 }
128
129 if (flag)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200130 enable_interrupts();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100131
132 return ret;
133}
134
135#endif