Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2020 NXP |
| 4 | * Layerscape PCIe EP driver |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <dm.h> |
| 9 | #include <dm/devres.h> |
| 10 | #include <errno.h> |
| 11 | #include <pci_ep.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <linux/sizes.h> |
| 14 | #include <linux/log2.h> |
| 15 | #include "pcie_layerscape.h" |
| 16 | |
| 17 | DECLARE_GLOBAL_DATA_PTR; |
| 18 | |
| 19 | static void ls_pcie_ep_enable_cfg(struct ls_pcie_ep *pcie_ep) |
| 20 | { |
| 21 | struct ls_pcie *pcie = pcie_ep->pcie; |
| 22 | u32 config; |
| 23 | |
| 24 | config = ctrl_readl(pcie, PCIE_PF_CONFIG); |
| 25 | config |= PCIE_CONFIG_READY; |
| 26 | ctrl_writel(pcie, config, PCIE_PF_CONFIG); |
| 27 | } |
| 28 | |
| 29 | static int ls_ep_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar) |
| 30 | { |
| 31 | struct ls_pcie_ep *pcie_ep = dev_get_priv(dev); |
| 32 | struct ls_pcie *pcie = pcie_ep->pcie; |
| 33 | dma_addr_t bar_phys = ep_bar->phys_addr; |
| 34 | enum pci_barno bar = ep_bar->barno; |
| 35 | u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); |
| 36 | int flags = ep_bar->flags; |
| 37 | int type, idx; |
| 38 | u64 size; |
| 39 | |
| 40 | idx = bar; |
| 41 | /* BAR size is 2^(aperture + 11) */ |
| 42 | size = max_t(size_t, ep_bar->size, FSL_PCIE_EP_MIN_APERTURE); |
| 43 | |
| 44 | if (!(flags & PCI_BASE_ADDRESS_SPACE)) |
| 45 | type = PCIE_ATU_TYPE_MEM; |
| 46 | else |
| 47 | type = PCIE_ATU_TYPE_IO; |
| 48 | |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 49 | ls_pcie_atu_inbound_set(pcie, fn, type, idx, bar, bar_phys); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 50 | |
| 51 | dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE); |
| 52 | dbi_writel(pcie, flags, reg); |
| 53 | |
| 54 | if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
| 55 | dbi_writel(pcie, upper_32_bits(size - 1), |
| 56 | reg + 4 + PCIE_NO_SRIOV_BAR_BASE); |
| 57 | dbi_writel(pcie, 0, reg + 4); |
| 58 | } |
| 59 | |
| 60 | return 0; |
| 61 | } |
| 62 | |
| 63 | static struct pci_ep_ops ls_pcie_ep_ops = { |
| 64 | .set_bar = ls_ep_set_bar, |
| 65 | }; |
| 66 | |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 67 | static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf) |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 68 | { |
| 69 | struct ls_pcie *pcie = pcie_ep->pcie; |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 70 | u64 phys = 0; |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 71 | |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 72 | phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M; |
| 73 | |
| 74 | phys = ALIGN(phys, PCIE_BAR0_SIZE); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 75 | /* ATU 0 : INBOUND : map BAR0 */ |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 76 | ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM, |
| 77 | 0 + pf * BAR_NUM, 0, phys); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 78 | /* ATU 1 : INBOUND : map BAR1 */ |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 79 | phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE); |
| 80 | ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM, |
| 81 | 1 + pf * BAR_NUM, 1, phys); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 82 | /* ATU 2 : INBOUND : map BAR2 */ |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 83 | phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE); |
| 84 | ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM, |
| 85 | 2 + pf * BAR_NUM, 2, phys); |
| 86 | /* ATU 3 : INBOUND : map BAR2 */ |
| 87 | phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR4_SIZE); |
| 88 | ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM, |
| 89 | 3 + pf * BAR_NUM, 4, phys); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 90 | |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 91 | /* ATU: OUTBOUND : map MEM */ |
| 92 | ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM, |
| 93 | (u64)pcie_ep->addr_res.start + |
| 94 | pf * CONFIG_SYS_PCI_MEMORY_SIZE, |
| 95 | 0, CONFIG_SYS_PCI_MEMORY_SIZE); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ |
| 99 | static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) |
| 100 | { |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 101 | u32 mask; |
| 102 | |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 103 | /* The least inbound window is 4KiB */ |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 104 | if (size < SZ_4K) |
| 105 | mask = 0; |
| 106 | else |
| 107 | mask = size - 1; |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 108 | |
| 109 | switch (bar) { |
| 110 | case 0: |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 111 | writel(mask, bar_base + PCI_BASE_ADDRESS_0); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 112 | break; |
| 113 | case 1: |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 114 | writel(mask, bar_base + PCI_BASE_ADDRESS_1); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 115 | break; |
| 116 | case 2: |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 117 | writel(mask, bar_base + PCI_BASE_ADDRESS_2); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 118 | writel(0, bar_base + PCI_BASE_ADDRESS_3); |
| 119 | break; |
| 120 | case 4: |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 121 | writel(mask, bar_base + PCI_BASE_ADDRESS_4); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 122 | writel(0, bar_base + PCI_BASE_ADDRESS_5); |
| 123 | break; |
| 124 | default: |
| 125 | break; |
| 126 | } |
| 127 | } |
| 128 | |
| 129 | static void ls_pcie_ep_setup_bars(void *bar_base) |
| 130 | { |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 131 | /* BAR0 - 32bit - MEM */ |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 132 | ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 133 | /* BAR1 - 32bit - MEM*/ |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 134 | ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 135 | /* BAR2 - 64bit - MEM */ |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 136 | ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 137 | /* BAR4 - 64bit - MEM */ |
| 138 | ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); |
| 139 | } |
| 140 | |
| 141 | static void ls_pcie_ep_setup_vf_bars(void *bar_base) |
| 142 | { |
| 143 | /* VF BAR0 MASK register at offset 0x19c*/ |
| 144 | bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0; |
| 145 | |
| 146 | /* VF-BAR0 - 32bit - MEM */ |
| 147 | ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); |
| 148 | /* VF-BAR1 - 32bit - MEM*/ |
| 149 | ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); |
| 150 | /* VF-BAR2 - 64bit - MEM */ |
| 151 | ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); |
| 152 | /* VF-BAR4 - 64bit - MEM */ |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 153 | ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); |
| 154 | } |
| 155 | |
| 156 | static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep) |
| 157 | { |
| 158 | u32 sriov; |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 159 | u32 pf, vf; |
| 160 | void *bar_base = NULL; |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 161 | struct ls_pcie *pcie = pcie_ep->pcie; |
| 162 | |
| 163 | sriov = readl(pcie->dbi + PCIE_SRIOV); |
| 164 | if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) { |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 165 | pcie_ep->sriov_flag = 1; |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 166 | for (pf = 0; pf < PCIE_PF_NUM; pf++) { |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 167 | if (pcie_ep->cfg2_flag) { |
| 168 | for (vf = 0; vf <= PCIE_VF_NUM; vf++) { |
| 169 | ctrl_writel(pcie, |
| 170 | PCIE_LCTRL0_VAL(pf, vf), |
| 171 | PCIE_PF_VF_CTRL); |
| 172 | } |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 173 | } |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 174 | bar_base = pcie->dbi + |
| 175 | PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf); |
| 176 | ls_pcie_ep_setup_bars(bar_base); |
| 177 | ls_pcie_ep_setup_vf_bars(bar_base); |
| 178 | |
| 179 | ls_pcie_ep_setup_atu(pcie_ep, pf); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 180 | } |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 181 | |
| 182 | if (pcie_ep->cfg2_flag) /* Disable CFG2 */ |
| 183 | ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 184 | } else { |
| 185 | ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 186 | ls_pcie_ep_setup_atu(pcie_ep, 0); |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | ls_pcie_ep_enable_cfg(pcie_ep); |
| 190 | } |
| 191 | |
| 192 | static int ls_pcie_ep_probe(struct udevice *dev) |
| 193 | { |
| 194 | struct ls_pcie_ep *pcie_ep = dev_get_priv(dev); |
| 195 | struct ls_pcie *pcie; |
| 196 | u16 link_sta; |
| 197 | int ret; |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 198 | u32 svr; |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 199 | |
| 200 | pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL); |
| 201 | if (!pcie) |
| 202 | return -ENOMEM; |
| 203 | |
| 204 | pcie_ep->pcie = pcie; |
| 205 | |
| 206 | pcie->dbi = (void __iomem *)devfdt_get_addr_index(dev, 0); |
| 207 | if (!pcie->dbi) |
| 208 | return -ENOMEM; |
| 209 | |
| 210 | pcie->ctrl = (void __iomem *)devfdt_get_addr_index(dev, 1); |
| 211 | if (!pcie->ctrl) |
| 212 | return -ENOMEM; |
| 213 | |
| 214 | ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev), |
| 215 | "reg", "reg-names", |
| 216 | "addr_space", &pcie_ep->addr_res); |
| 217 | if (ret) { |
| 218 | printf("%s: resource \"addr_space\" not found\n", dev->name); |
| 219 | return ret; |
| 220 | } |
| 221 | |
| 222 | pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) / |
| 223 | PCIE_CCSR_SIZE; |
| 224 | |
| 225 | pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), |
| 226 | "big-endian"); |
| 227 | |
Xiaowei Bao | c5174a5 | 2020-07-09 23:31:36 +0800 | [diff] [blame^] | 228 | svr = SVR_SOC_VER(get_svr()); |
| 229 | |
| 230 | if (svr == SVR_LS2080A || svr == SVR_LS2085A) |
| 231 | pcie_ep->cfg2_flag = 1; |
| 232 | else |
| 233 | pcie_ep->cfg2_flag = 0; |
| 234 | |
Xiaowei Bao | 118e58e | 2020-07-09 23:31:33 +0800 | [diff] [blame] | 235 | pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f; |
| 236 | if (pcie->mode != PCI_HEADER_TYPE_NORMAL) |
| 237 | return 0; |
| 238 | |
| 239 | pcie_ep->max_functions = fdtdec_get_int(gd->fdt_blob, |
| 240 | dev_of_offset(dev), |
| 241 | "max-functions", 1); |
| 242 | pcie_ep->num_ib_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
| 243 | "num-ib-windows", 8); |
| 244 | pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
| 245 | "num-ob-windows", 8); |
| 246 | |
| 247 | printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint"); |
| 248 | ls_pcie_setup_ep(pcie_ep); |
| 249 | |
| 250 | if (!ls_pcie_link_up(pcie)) { |
| 251 | /* Let the user know there's no PCIe link */ |
| 252 | printf(": no link\n"); |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | /* Print the negotiated PCIe link width */ |
| 257 | link_sta = readw(pcie->dbi + PCIE_LINK_STA); |
| 258 | printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4, |
| 259 | link_sta & PCIE_LINK_SPEED_MASK); |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | static int ls_pcie_ep_remove(struct udevice *dev) |
| 265 | { |
| 266 | return 0; |
| 267 | } |
| 268 | |
| 269 | const struct udevice_id ls_pcie_ep_ids[] = { |
| 270 | { .compatible = "fsl,ls-pcie-ep" }, |
| 271 | { } |
| 272 | }; |
| 273 | |
| 274 | U_BOOT_DRIVER(pci_layerscape_ep) = { |
| 275 | .name = "pci_layerscape_ep", |
| 276 | .id = UCLASS_PCI_EP, |
| 277 | .of_match = ls_pcie_ep_ids, |
| 278 | .ops = &ls_pcie_ep_ops, |
| 279 | .probe = ls_pcie_ep_probe, |
| 280 | .remove = ls_pcie_ep_remove, |
| 281 | .priv_auto_alloc_size = sizeof(struct ls_pcie_ep), |
| 282 | }; |