blob: 1c4370b0819d83145ff3b4b2c405c376d008ee5d [file] [log] [blame]
wdenk2262cfe2002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* stuff specific for the sc520,
25 * but idependent of implementation */
26
wdenk7a8e9bed2003-05-31 18:35:21 +000027#include <config.h>
28
29#ifdef CONFIG_SC520
wdenk2262cfe2002-11-18 00:14:45 +000030
31#include <common.h>
32#include <config.h>
33#include <pci.h>
Wolfgang Denk94568b62006-08-14 23:23:06 +020034#ifdef CONFIG_SC520_SSI
wdenk7a8e9bed2003-05-31 18:35:21 +000035#include <ssi.h>
Wolfgang Denk94568b62006-08-14 23:23:06 +020036#endif
wdenk2262cfe2002-11-18 00:14:45 +000037#include <asm/io.h>
38#include <asm/pci.h>
39#include <asm/ic/sc520.h>
40
Wolfgang Denkd87080b2006-03-31 18:32:53 +020041DECLARE_GLOBAL_DATA_PTR;
42
wdenk8bde7f72003-06-27 21:31:46 +000043/*
44 * utility functions for boards based on the AMD sc520
45 *
wdenk2262cfe2002-11-18 00:14:45 +000046 * void write_mmcr_byte(u16 mmcr, u8 data)
47 * void write_mmcr_word(u16 mmcr, u16 data)
48 * void write_mmcr_long(u16 mmcr, u32 data)
wdenk8bde7f72003-06-27 21:31:46 +000049 *
wdenk2262cfe2002-11-18 00:14:45 +000050 * u8 read_mmcr_byte(u16 mmcr)
51 * u16 read_mmcr_word(u16 mmcr)
52 * u32 read_mmcr_long(u16 mmcr)
wdenk8bde7f72003-06-27 21:31:46 +000053 *
wdenk2262cfe2002-11-18 00:14:45 +000054 * void init_sc520(void)
55 * unsigned long init_sc520_dram(void)
56 * void pci_sc520_init(struct pci_controller *hose)
wdenk8bde7f72003-06-27 21:31:46 +000057 *
wdenk2262cfe2002-11-18 00:14:45 +000058 * void reset_timer(void)
59 * ulong get_timer(ulong base)
60 * void set_timer(ulong t)
61 * void udelay(unsigned long usec)
wdenk8bde7f72003-06-27 21:31:46 +000062 *
wdenk2262cfe2002-11-18 00:14:45 +000063 */
64
65static u32 mmcr_base= 0xfffef000;
66
67void write_mmcr_byte(u16 mmcr, u8 data)
68{
69 writeb(data, mmcr+mmcr_base);
70}
71
72void write_mmcr_word(u16 mmcr, u16 data)
73{
wdenk8bde7f72003-06-27 21:31:46 +000074 writew(data, mmcr+mmcr_base);
wdenk2262cfe2002-11-18 00:14:45 +000075}
76
77void write_mmcr_long(u16 mmcr, u32 data)
78{
79 writel(data, mmcr+mmcr_base);
80}
81
82u8 read_mmcr_byte(u16 mmcr)
83{
84 return readb(mmcr+mmcr_base);
85}
86
87u16 read_mmcr_word(u16 mmcr)
88{
wdenk8bde7f72003-06-27 21:31:46 +000089 return readw(mmcr+mmcr_base);
wdenk2262cfe2002-11-18 00:14:45 +000090}
91
92u32 read_mmcr_long(u16 mmcr)
93{
94 return readl(mmcr+mmcr_base);
95}
96
97
98void init_sc520(void)
99{
wdenk2262cfe2002-11-18 00:14:45 +0000100 /* Set the UARTxCTL register at it's slower,
wdenk8bde7f72003-06-27 21:31:46 +0000101 * baud clock giving us a 1.8432 MHz reference
wdenk2262cfe2002-11-18 00:14:45 +0000102 */
103 write_mmcr_byte(SC520_UART1CTL, 7);
104 write_mmcr_byte(SC520_UART2CTL, 7);
wdenk8bde7f72003-06-27 21:31:46 +0000105
wdenk2262cfe2002-11-18 00:14:45 +0000106 /* first set the timer pin mapping */
107 write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
wdenk8bde7f72003-06-27 21:31:46 +0000108
wdenk2262cfe2002-11-18 00:14:45 +0000109 /* enable PCI bus arbitrer */
110 write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
wdenk8bde7f72003-06-27 21:31:46 +0000111
wdenk2262cfe2002-11-18 00:14:45 +0000112 write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
113 write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
114
115
116 if (CFG_SC520_HIGH_SPEED) {
117 write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
118 gd->cpu_clk = 133000000;
119 printf("## CPU Speed set to 133MHz\n");
120 } else {
121 write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */
122 printf("## CPU Speed set to 100MHz\n");
123 gd->cpu_clk = 100000000;
124 }
wdenk8bde7f72003-06-27 21:31:46 +0000125
wdenk2262cfe2002-11-18 00:14:45 +0000126
127 /* wait at least one millisecond */
wdenk8bde7f72003-06-27 21:31:46 +0000128 asm("movl $0x2000,%%ecx\n"
wdenk2262cfe2002-11-18 00:14:45 +0000129 "wait_loop: pushl %%ecx\n"
130 "popl %%ecx\n"
131 "loop wait_loop\n": : : "ecx");
132
133 /* turn on the SDRAM write buffer */
134 write_mmcr_byte(SC520_DBCTL, 0x11);
135
136 /* turn on the cache and disable write through */
137 asm("movl %%cr0, %%eax\n"
138 "andl $0x9fffffff, %%eax\n"
139 "movl %%eax, %%cr0\n" : : : "eax");
140}
141
142unsigned long init_sc520_dram(void)
143{
wdenk2262cfe2002-11-18 00:14:45 +0000144 bd_t *bd = gd->bd;
wdenk8bde7f72003-06-27 21:31:46 +0000145
wdenk2262cfe2002-11-18 00:14:45 +0000146 u32 dram_present=0;
147 u32 dram_ctrl;
Wolfgang Denk94568b62006-08-14 23:23:06 +0200148#ifdef CFG_SDRAM_DRCTMCTL
149 /* these memory control registers are set up in the assember part,
150 * in sc520_asm.S, during 'mem_init'. If we muck with them here,
151 * after we are running a stack in RAM, we have troubles. Besides,
152 * these refresh and delay values are better ? simply specified
153 * outright in the include/configs/{cfg} file since the HW designer
154 * simply dictates it.
155 */
156#else
wdenk2262cfe2002-11-18 00:14:45 +0000157 int val;
wdenk8bde7f72003-06-27 21:31:46 +0000158
159 int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
160 int refresh_rate = CFG_SDRAM_REFRESH_RATE;
wdenk2262cfe2002-11-18 00:14:45 +0000161 int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY;
wdenk8bde7f72003-06-27 21:31:46 +0000162
wdenk2262cfe2002-11-18 00:14:45 +0000163 /* set SDRAM speed here */
wdenk8bde7f72003-06-27 21:31:46 +0000164
165 refresh_rate/=78;
wdenk2262cfe2002-11-18 00:14:45 +0000166 if (refresh_rate<=1) {
167 val = 0; /* 7.8us */
168 } else if (refresh_rate==2) {
169 val = 1; /* 15.6us */
170 } else if (refresh_rate==3 || refresh_rate==4) {
171 val = 2; /* 31.2us */
172 } else {
173 val = 3; /* 62.4us */
174 }
Wolfgang Denk94568b62006-08-14 23:23:06 +0200175
wdenk2262cfe2002-11-18 00:14:45 +0000176 write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
wdenk8bde7f72003-06-27 21:31:46 +0000177
wdenk2262cfe2002-11-18 00:14:45 +0000178 val = read_mmcr_byte(SC520_DRCTMCTL);
179 val &= 0xf0;
wdenk8bde7f72003-06-27 21:31:46 +0000180
181 if (cas_precharge_delay==3) {
wdenk2262cfe2002-11-18 00:14:45 +0000182 val |= 0x04; /* 3T */
wdenk8bde7f72003-06-27 21:31:46 +0000183 } else if (cas_precharge_delay==4) {
wdenk2262cfe2002-11-18 00:14:45 +0000184 val |= 0x08; /* 4T */
wdenk8bde7f72003-06-27 21:31:46 +0000185 } else if (cas_precharge_delay>4) {
wdenk2262cfe2002-11-18 00:14:45 +0000186 val |= 0x0c;
wdenk8bde7f72003-06-27 21:31:46 +0000187 }
188
wdenk2262cfe2002-11-18 00:14:45 +0000189 if (ras_cas_delay > 3) {
wdenk8bde7f72003-06-27 21:31:46 +0000190 val |= 2;
wdenk2262cfe2002-11-18 00:14:45 +0000191 } else {
wdenk8bde7f72003-06-27 21:31:46 +0000192 val |= 1;
wdenk2262cfe2002-11-18 00:14:45 +0000193 }
194 write_mmcr_byte(SC520_DRCTMCTL, val);
Wolfgang Denk94568b62006-08-14 23:23:06 +0200195#endif
wdenk2262cfe2002-11-18 00:14:45 +0000196
197 /* We read-back the configuration of the dram
198 * controller that the assembly code wrote */
199 dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
wdenk8bde7f72003-06-27 21:31:46 +0000200
wdenk2262cfe2002-11-18 00:14:45 +0000201 bd->bi_dram[0].start = 0;
202 if (dram_ctrl & 0x80) {
203 /* bank 0 enabled */
204 dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
wdenk8bde7f72003-06-27 21:31:46 +0000205 bd->bi_dram[0].size = bd->bi_dram[1].start;
wdenk2262cfe2002-11-18 00:14:45 +0000206
207 } else {
208 bd->bi_dram[0].size = 0;
209 bd->bi_dram[1].start = bd->bi_dram[0].start;
210 }
wdenk8bde7f72003-06-27 21:31:46 +0000211
wdenk2262cfe2002-11-18 00:14:45 +0000212 if (dram_ctrl & 0x8000) {
213 /* bank 1 enabled */
214 dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
wdenk8bde7f72003-06-27 21:31:46 +0000215 bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
wdenk2262cfe2002-11-18 00:14:45 +0000216 } else {
217 bd->bi_dram[1].size = 0;
218 bd->bi_dram[2].start = bd->bi_dram[1].start;
219 }
wdenk8bde7f72003-06-27 21:31:46 +0000220
wdenk2262cfe2002-11-18 00:14:45 +0000221 if (dram_ctrl & 0x800000) {
222 /* bank 2 enabled */
223 dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
wdenk8bde7f72003-06-27 21:31:46 +0000224 bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
wdenk2262cfe2002-11-18 00:14:45 +0000225 } else {
226 bd->bi_dram[2].size = 0;
227 bd->bi_dram[3].start = bd->bi_dram[2].start;
wdenk8bde7f72003-06-27 21:31:46 +0000228 }
229
wdenk2262cfe2002-11-18 00:14:45 +0000230 if (dram_ctrl & 0x80000000) {
231 /* bank 3 enabled */
232 dram_present = (dram_ctrl & 0x7f000000) >> 2;
233 bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
234 } else {
235 bd->bi_dram[3].size = 0;
236 }
237
wdenk8bde7f72003-06-27 21:31:46 +0000238
239#if 0
wdenk2262cfe2002-11-18 00:14:45 +0000240 printf("Configured %d bytes of dram\n", dram_present);
wdenk8bde7f72003-06-27 21:31:46 +0000241#endif
wdenk2262cfe2002-11-18 00:14:45 +0000242 gd->ram_size = dram_present;
wdenk8bde7f72003-06-27 21:31:46 +0000243
wdenk2262cfe2002-11-18 00:14:45 +0000244 return dram_present;
245}
246
247
248#ifdef CONFIG_PCI
249
250
wdenk7a8e9bed2003-05-31 18:35:21 +0000251static struct {
252 u8 priority;
253 u16 level_reg;
254 u8 level_bit;
255} sc520_irq[] = {
256 { SC520_IRQ0, SC520_MPICMODE, 0x01 },
257 { SC520_IRQ1, SC520_MPICMODE, 0x02 },
258 { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
259 { SC520_IRQ3, SC520_MPICMODE, 0x08 },
260 { SC520_IRQ4, SC520_MPICMODE, 0x10 },
261 { SC520_IRQ5, SC520_MPICMODE, 0x20 },
262 { SC520_IRQ6, SC520_MPICMODE, 0x40 },
263 { SC520_IRQ7, SC520_MPICMODE, 0x80 },
264
265 { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
266 { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
267 { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
268 { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
269 { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
270 { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
271 { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
272 { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
273};
274
275
276/* The interrupt used for PCI INTA-INTD */
wdenk8bde7f72003-06-27 21:31:46 +0000277int sc520_pci_ints[15] = {
wdenk7a8e9bed2003-05-31 18:35:21 +0000278 -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1
280};
281
282/* utility function to configure a pci interrupt */
wdenk8bde7f72003-06-27 21:31:46 +0000283int pci_sc520_set_irq(int pci_pin, int irq)
wdenk7a8e9bed2003-05-31 18:35:21 +0000284{
285 int i;
wdenk8bde7f72003-06-27 21:31:46 +0000286
Wolfgang Denk94568b62006-08-14 23:23:06 +0200287# if 1
wdenk7a8e9bed2003-05-31 18:35:21 +0000288 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
wdenk8bde7f72003-06-27 21:31:46 +0000289#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000290 if (irq < 0 || irq > 15) {
291 return -1; /* illegal irq */
292 }
293
294 if (pci_pin < 0 || pci_pin > 15) {
295 return -1; /* illegal pci int pin */
296 }
297
wdenk8bde7f72003-06-27 21:31:46 +0000298 /* first disable any non-pci interrupt source that use
wdenk7a8e9bed2003-05-31 18:35:21 +0000299 * this level */
300 for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
301 if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
302 continue;
303 }
304 if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
305 write_mmcr_byte(i, SC520_IRQ_DISABLED);
306 }
307 }
wdenk8bde7f72003-06-27 21:31:46 +0000308
wdenk7a8e9bed2003-05-31 18:35:21 +0000309 /* Set the trigger to level */
wdenk8bde7f72003-06-27 21:31:46 +0000310 write_mmcr_byte(sc520_irq[irq].level_reg,
wdenk7a8e9bed2003-05-31 18:35:21 +0000311 read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
wdenk8bde7f72003-06-27 21:31:46 +0000312
313
wdenk7a8e9bed2003-05-31 18:35:21 +0000314 if (pci_pin < 4) {
315 /* PCI INTA-INTD */
316 /* route the interrupt */
317 write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
wdenk8bde7f72003-06-27 21:31:46 +0000318
319
wdenk7a8e9bed2003-05-31 18:35:21 +0000320 } else {
321 /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
322 write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
wdenk8bde7f72003-06-27 21:31:46 +0000323
wdenk7a8e9bed2003-05-31 18:35:21 +0000324 /* also set the polarity in this case */
wdenk8bde7f72003-06-27 21:31:46 +0000325 write_mmcr_word(SC520_INTPINPOL,
wdenk7a8e9bed2003-05-31 18:35:21 +0000326 read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
wdenk8bde7f72003-06-27 21:31:46 +0000327
wdenk7a8e9bed2003-05-31 18:35:21 +0000328 }
wdenk8bde7f72003-06-27 21:31:46 +0000329
330 /* register the pin */
wdenk7a8e9bed2003-05-31 18:35:21 +0000331 sc520_pci_ints[pci_pin] = irq;
wdenk8bde7f72003-06-27 21:31:46 +0000332
wdenk7a8e9bed2003-05-31 18:35:21 +0000333
334 return 0; /* OK */
335}
wdenk2262cfe2002-11-18 00:14:45 +0000336
337void pci_sc520_init(struct pci_controller *hose)
338{
339 hose->first_busno = 0;
340 hose->last_busno = 0xff;
341
342 /* System memory space */
wdenk8bde7f72003-06-27 21:31:46 +0000343 pci_set_region(hose->regions + 0,
wdenk2262cfe2002-11-18 00:14:45 +0000344 SC520_PCI_MEMORY_BUS,
345 SC520_PCI_MEMORY_PHYS,
346 SC520_PCI_MEMORY_SIZE,
347 PCI_REGION_MEM | PCI_REGION_MEMORY);
348
349 /* PCI memory space */
wdenk8bde7f72003-06-27 21:31:46 +0000350 pci_set_region(hose->regions + 1,
wdenk2262cfe2002-11-18 00:14:45 +0000351 SC520_PCI_MEM_BUS,
352 SC520_PCI_MEM_PHYS,
353 SC520_PCI_MEM_SIZE,
354 PCI_REGION_MEM);
355
356 /* ISA/PCI memory space */
wdenk8bde7f72003-06-27 21:31:46 +0000357 pci_set_region(hose->regions + 2,
wdenk2262cfe2002-11-18 00:14:45 +0000358 SC520_ISA_MEM_BUS,
359 SC520_ISA_MEM_PHYS,
360 SC520_ISA_MEM_SIZE,
361 PCI_REGION_MEM);
362
363 /* PCI I/O space */
wdenk8bde7f72003-06-27 21:31:46 +0000364 pci_set_region(hose->regions + 3,
wdenk2262cfe2002-11-18 00:14:45 +0000365 SC520_PCI_IO_BUS,
366 SC520_PCI_IO_PHYS,
367 SC520_PCI_IO_SIZE,
368 PCI_REGION_IO);
369
370 /* ISA/PCI I/O space */
wdenk8bde7f72003-06-27 21:31:46 +0000371 pci_set_region(hose->regions + 4,
wdenk2262cfe2002-11-18 00:14:45 +0000372 SC520_ISA_IO_BUS,
373 SC520_ISA_IO_PHYS,
374 SC520_ISA_IO_SIZE,
375 PCI_REGION_IO);
376
377 hose->region_count = 5;
378
379 pci_setup_type1(hose,
380 SC520_REG_ADDR,
381 SC520_REG_DATA);
382
383 pci_register_hose(hose);
384
385 hose->last_busno = pci_hose_scan(hose);
wdenk8bde7f72003-06-27 21:31:46 +0000386
wdenk2262cfe2002-11-18 00:14:45 +0000387 /* enable target memory acceses on host brige */
wdenk8bde7f72003-06-27 21:31:46 +0000388 pci_write_config_word(0, PCI_COMMAND,
wdenk2262cfe2002-11-18 00:14:45 +0000389 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
390
391}
392
393
394#endif
395
396#ifdef CFG_TIMER_SC520
397
398
399void reset_timer(void)
400{
401 write_mmcr_word(SC520_GPTMR0CNT, 0);
402 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
wdenk8bde7f72003-06-27 21:31:46 +0000403
wdenk2262cfe2002-11-18 00:14:45 +0000404}
405
406ulong get_timer(ulong base)
407{
408 /* fixme: 30 or 33 */
409 return read_mmcr_word(SC520_GPTMR0CNT) / 33;
410}
411
412void set_timer(ulong t)
413{
414 /* FixMe: use two cascade coupled timers */
415 write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
416 write_mmcr_word(SC520_GPTMR0CNT, t*33);
417 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
418}
419
420
421void udelay(unsigned long usec)
422{
423 int m=0;
424 long u;
wdenk8bde7f72003-06-27 21:31:46 +0000425
wdenk2262cfe2002-11-18 00:14:45 +0000426 read_mmcr_word(SC520_SWTMRMILLI);
427 read_mmcr_word(SC520_SWTMRMICRO);
wdenk8bde7f72003-06-27 21:31:46 +0000428
wdenk2262cfe2002-11-18 00:14:45 +0000429#if 0
430 /* do not enable this line, udelay is used in the serial driver -> recursion */
431 printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
wdenk8bde7f72003-06-27 21:31:46 +0000432#endif
wdenk2262cfe2002-11-18 00:14:45 +0000433 while (1) {
wdenk8bde7f72003-06-27 21:31:46 +0000434
wdenk2262cfe2002-11-18 00:14:45 +0000435 m += read_mmcr_word(SC520_SWTMRMILLI);
436 u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
wdenk8bde7f72003-06-27 21:31:46 +0000437
wdenk2262cfe2002-11-18 00:14:45 +0000438 if (usec <= u) {
439 break;
440 }
441 }
442}
443
444#endif
445
wdenk7a8e9bed2003-05-31 18:35:21 +0000446int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
447{
448 u8 temp=0;
wdenk2262cfe2002-11-18 00:14:45 +0000449
wdenk7a8e9bed2003-05-31 18:35:21 +0000450 if (freq >= 8192) {
wdenk8bde7f72003-06-27 21:31:46 +0000451 temp |= CTL_CLK_SEL_4;
wdenk7a8e9bed2003-05-31 18:35:21 +0000452 } else if (freq >= 4096) {
wdenk8bde7f72003-06-27 21:31:46 +0000453 temp |= CTL_CLK_SEL_8;
wdenk7a8e9bed2003-05-31 18:35:21 +0000454 } else if (freq >= 2048) {
wdenk8bde7f72003-06-27 21:31:46 +0000455 temp |= CTL_CLK_SEL_16;
wdenk7a8e9bed2003-05-31 18:35:21 +0000456 } else if (freq >= 1024) {
wdenk8bde7f72003-06-27 21:31:46 +0000457 temp |= CTL_CLK_SEL_32;
wdenk7a8e9bed2003-05-31 18:35:21 +0000458 } else if (freq >= 512) {
459 temp |= CTL_CLK_SEL_64;
460 } else if (freq >= 256) {
461 temp |= CTL_CLK_SEL_128;
462 } else if (freq >= 128) {
463 temp |= CTL_CLK_SEL_256;
464 } else {
465 temp |= CTL_CLK_SEL_512;
466 }
wdenk8bde7f72003-06-27 21:31:46 +0000467
wdenk7a8e9bed2003-05-31 18:35:21 +0000468 if (!lsb_first) {
469 temp |= MSBF_ENB;
470 }
wdenk8bde7f72003-06-27 21:31:46 +0000471
wdenk7a8e9bed2003-05-31 18:35:21 +0000472 if (inv_clock) {
473 temp |= CLK_INV_ENB;
474 }
wdenk8bde7f72003-06-27 21:31:46 +0000475
wdenk7a8e9bed2003-05-31 18:35:21 +0000476 if (inv_phase) {
477 temp |= PHS_INV_ENB;
478 }
wdenk8bde7f72003-06-27 21:31:46 +0000479
wdenk7a8e9bed2003-05-31 18:35:21 +0000480 write_mmcr_byte(SC520_SSICTL, temp);
wdenk8bde7f72003-06-27 21:31:46 +0000481
wdenk7a8e9bed2003-05-31 18:35:21 +0000482 return 0;
483}
484
wdenk8bde7f72003-06-27 21:31:46 +0000485u8 ssi_txrx_byte(u8 data)
wdenk7a8e9bed2003-05-31 18:35:21 +0000486{
487 write_mmcr_byte(SC520_SSIXMIT, data);
488 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
489 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
490 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
wdenk8bde7f72003-06-27 21:31:46 +0000491 return read_mmcr_byte(SC520_SSIRCV);
492}
wdenk7a8e9bed2003-05-31 18:35:21 +0000493
494
wdenk8bde7f72003-06-27 21:31:46 +0000495void ssi_tx_byte(u8 data)
wdenk7a8e9bed2003-05-31 18:35:21 +0000496{
497 write_mmcr_byte(SC520_SSIXMIT, data);
wdenk8bde7f72003-06-27 21:31:46 +0000498 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
wdenk7a8e9bed2003-05-31 18:35:21 +0000499 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
500}
501
wdenk8bde7f72003-06-27 21:31:46 +0000502u8 ssi_rx_byte(void)
wdenk7a8e9bed2003-05-31 18:35:21 +0000503{
504 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
505 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
506 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
507 return read_mmcr_byte(SC520_SSIRCV);
wdenk8bde7f72003-06-27 21:31:46 +0000508}
wdenk7a8e9bed2003-05-31 18:35:21 +0000509
510#endif /* CONFIG_SC520 */