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Paul Gortmaker91e25762007-01-16 11:38:14 -05001/*
2 * WindRiver SBC8349 U-Boot configuration file.
3 * Copyright (c) 2006, 2007 Wind River Systems, Inc.
4 *
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on the MPC8349EMDS config.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * sbc8349 board configuration file.
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
Paul Gortmaker91e25762007-01-16 11:38:14 -050034/*
35 * High Level Configuration Options
36 */
37#define CONFIG_E300 1 /* E300 Family */
38#define CONFIG_MPC83XX 1 /* MPC83XX family */
39#define CONFIG_MPC834X 1 /* MPC834X family */
40#define CONFIG_MPC8349 1 /* MPC8349 specific */
41#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
42
43#undef CONFIG_PCI
44/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
45#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
46
47#define PCI_66M
48#ifdef PCI_66M
49#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
50#else
51#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
52#endif
53
54#ifndef CONFIG_SYS_CLK_FREQ
55#ifdef PCI_66M
56#define CONFIG_SYS_CLK_FREQ 66000000
57#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
58#else
59#define CONFIG_SYS_CLK_FREQ 33000000
60#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
61#endif
62#endif
63
Paul Gortmaker91e25762007-01-16 11:38:14 -050064#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
65
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_IMMR 0xE0000000
Paul Gortmaker91e25762007-01-16 11:38:14 -050067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
69#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
70#define CONFIG_SYS_MEMTEST_END 0x00100000
Paul Gortmaker91e25762007-01-16 11:38:14 -050071
72/*
73 * DDR Setup
74 */
75#undef CONFIG_DDR_ECC /* only for ECC DDR module */
76#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
77#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
Paul Gortmaker91e25762007-01-16 11:38:14 -050079
80/*
81 * 32-bit data path mode.
82 *
83 * Please note that using this mode for devices with the real density of 64-bit
84 * effectively reduces the amount of available memory due to the effect of
85 * wrapping around while translating address to row/columns, for example in the
86 * 256MB module the upper 128MB get aliased with contents of the lower
87 * 128MB); normally this define should be used for devices with real 32-bit
88 * data path.
89 */
90#undef CONFIG_DDR_32BIT
91
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
93#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
94#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
95#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Paul Gortmaker91e25762007-01-16 11:38:14 -050096 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
97#define CONFIG_DDR_2T_TIMING
98
99#if defined(CONFIG_SPD_EEPROM)
100/*
101 * Determine DDR configuration from I2C interface.
102 */
103#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
104
105#else
106/*
107 * Manually set up DDR parameters
108 * NB: manual DDR setup untested on sbc834x
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_DDR_SIZE 256 /* MB */
111#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
112#define CONFIG_SYS_DDR_TIMING_1 0x36332321
113#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
114#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
115#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500116
117#if defined(CONFIG_DDR_32BIT)
118/* set burst length to 8 for 32-bit data path */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500120#else
121/* the default burst length is 4 - for 64-bit data path */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500123#endif
124#endif
125
126/*
127 * SDRAM on the Local Bus
128 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */
130#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500131
132/*
133 * FLASH on the Local Bus
134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200136#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
138#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
139/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500142 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
143 BR_V) /* valid */
144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
146#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
147#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
150#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#undef CONFIG_SYS_FLASH_CHECKSUM
153#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
154#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000
157#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
160#define CONFIG_SYS_RAMBOOT
Paul Gortmaker91e25762007-01-16 11:38:14 -0500161#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#undef CONFIG_SYS_RAMBOOT
Paul Gortmaker91e25762007-01-16 11:38:14 -0500163#endif
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_INIT_RAM_LOCK 1
166#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
167#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Paul Gortmaker91e25762007-01-16 11:38:14 -0500168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
170#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
171#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Paul Gortmaker91e25762007-01-16 11:38:14 -0500172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
174#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500175
176/*
177 * Local Bus LCRR and LBCR regs
178 * LCRR: DLL bypass, Clock divider is 4
179 * External Local Bus rate is
180 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
183#define CONFIG_SYS_LBC_LBCR 0x00000000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#ifdef CONFIG_SYS_LB_SDRAM
Paul Gortmaker91e25762007-01-16 11:38:14 -0500188/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
189/*
190 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Paul Gortmaker91e25762007-01-16 11:38:14 -0500192 *
193 * For BR2, need:
194 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
195 * port-size = 32-bits = BR2[19:20] = 11
196 * no parity checking = BR2[21:22] = 00
197 * SDRAM for MSEL = BR2[24:26] = 011
198 * Valid = BR[31] = 1
199 *
200 * 0 4 8 12 16 20 24 28
201 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
202 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
Paul Gortmaker91e25762007-01-16 11:38:14 -0500204 * FIXME: the top 17 bits of BR2.
205 */
206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
208#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
209#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500210
211/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Paul Gortmaker91e25762007-01-16 11:38:14 -0500213 *
214 * For OR2, need:
215 * 64MB mask for AM, OR2[0:7] = 1111 1100
216 * XAM, OR2[17:18] = 11
217 * 9 columns OR2[19-21] = 010
218 * 13 rows OR2[23-25] = 100
219 * EAD set for extra time OR[31] = 1
220 *
221 * 0 4 8 12 16 20 24 28
222 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
223 */
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_OR2_PRELIM 0xFC006901
Paul Gortmaker91e25762007-01-16 11:38:14 -0500226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
228#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500229
230/*
231 * LSDMR masks
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
234#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
235#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
236#define CONFIG_SYS_LBC_LSDMR_RFCR5 (3 << (31 - 16))
237#define CONFIG_SYS_LBC_LSDMR_RFCR8 (5 << (31 - 16))
238#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
239#define CONFIG_SYS_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
240#define CONFIG_SYS_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
241#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
242#define CONFIG_SYS_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
243#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
244#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
245#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
246#define CONFIG_SYS_LBC_LSDMR_WRC2 (2 << (31 - 27))
247#define CONFIG_SYS_LBC_LSDMR_WRC3 (3 << (31 - 27))
248#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
249#define CONFIG_SYS_LBC_LSDMR_BUFCMD (1 << (31 - 29))
250#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
Paul Gortmaker91e25762007-01-16 11:38:14 -0500251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
253#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
254#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
255#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
256#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
257#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
258#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
259#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
Paul Gortmaker91e25762007-01-16 11:38:14 -0500260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFEN \
262 | CONFIG_SYS_LBC_LSDMR_BSMA1516 \
263 | CONFIG_SYS_LBC_LSDMR_RFCR8 \
264 | CONFIG_SYS_LBC_LSDMR_PRETOACT6 \
265 | CONFIG_SYS_LBC_LSDMR_ACTTORW3 \
266 | CONFIG_SYS_LBC_LSDMR_BL8 \
267 | CONFIG_SYS_LBC_LSDMR_WRC3 \
268 | CONFIG_SYS_LBC_LSDMR_CL3 \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500269 )
270
271/*
272 * SDRAM Controller configuration sequence.
273 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \
275 | CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
276#define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \
277 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
278#define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \
279 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
280#define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \
281 | CONFIG_SYS_LBC_LSDMR_OP_MRW)
282#define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \
283 | CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500284#endif
285
286/*
287 * Serial Port
288 */
289#define CONFIG_CONS_INDEX 1
290#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_NS16550
292#define CONFIG_SYS_NS16550_SERIAL
293#define CONFIG_SYS_NS16550_REG_SIZE 1
294#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_BAUDRATE_TABLE \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
300#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500301
Kim Phillips22d71a72007-02-27 18:41:08 -0600302#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500303/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_HUSH_PARSER
305#ifdef CONFIG_SYS_HUSH_PARSER
306#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Paul Gortmaker91e25762007-01-16 11:38:14 -0500307#endif
308
309/* pass open firmware flat tree */
Paul Gortmakere4968652007-12-20 12:58:51 -0500310#define CONFIG_OF_LIBFDT 1
Paul Gortmaker91e25762007-01-16 11:38:14 -0500311#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600312#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Paul Gortmaker91e25762007-01-16 11:38:14 -0500313
314/* I2C */
315#define CONFIG_HARD_I2C /* I2C with hardware support*/
316#undef CONFIG_SOFT_I2C /* I2C bit-banged */
317#define CONFIG_FSL_I2C
318#define CONFIG_I2C_CMD_TREE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
320#define CONFIG_SYS_I2C_SLAVE 0x7F
321#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
322#define CONFIG_SYS_I2C1_OFFSET 0x3000
323#define CONFIG_SYS_I2C2_OFFSET 0x3100
324#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
Paul Gortmaker91e25762007-01-16 11:38:14 -0500325/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
326
327/* TSEC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_TSEC1_OFFSET 0x24000
329#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
330#define CONFIG_SYS_TSEC2_OFFSET 0x25000
331#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500332
333/*
334 * General PCI
335 * Addresses are mapped 1-1.
336 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
338#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
339#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
340#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
341#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
342#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
343#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
344#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
345#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
348#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
349#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
350#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
351#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
352#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
353#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
354#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
355#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500356
357#if defined(CONFIG_PCI)
358
359#define PCI_64BIT
360#define PCI_ONE_PCI1
361#if defined(PCI_64BIT)
362#undef PCI_ALL_PCI1
363#undef PCI_TWO_PCI1
364#undef PCI_ONE_PCI1
365#endif
366
367#define CONFIG_NET_MULTI
368#define CONFIG_PCI_PNP /* do pci plug-and-play */
369
370#undef CONFIG_EEPRO100
371#undef CONFIG_TULIP
372
373#if !defined(CONFIG_PCI_PNP)
374 #define PCI_ENET0_IOADDR 0xFIXME
375 #define PCI_ENET0_MEMADDR 0xFIXME
376 #define PCI_IDSEL_NUMBER 0xFIXME
377#endif
378
379#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500381
382#endif /* CONFIG_PCI */
383
384/*
385 * TSEC configuration
386 */
387#define CONFIG_TSEC_ENET /* TSEC ethernet support */
388
389#if defined(CONFIG_TSEC_ENET)
390#ifndef CONFIG_NET_MULTI
391#define CONFIG_NET_MULTI 1
392#endif
393
Kim Phillips255a35772007-05-16 16:52:19 -0500394#define CONFIG_TSEC1 1
395#define CONFIG_TSEC1_NAME "TSEC0"
396#define CONFIG_TSEC2 1
397#define CONFIG_TSEC2_NAME "TSEC1"
Paul Gortmaker91e25762007-01-16 11:38:14 -0500398#define CONFIG_PHY_BCM5421S 1
399#define TSEC1_PHY_ADDR 0x19
400#define TSEC2_PHY_ADDR 0x1a
401#define TSEC1_PHYIDX 0
402#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500403#define TSEC1_FLAGS TSEC_GIGABIT
404#define TSEC2_FLAGS TSEC_GIGABIT
Paul Gortmaker91e25762007-01-16 11:38:14 -0500405
406/* Options are: TSEC[0-1] */
407#define CONFIG_ETHPRIME "TSEC0"
408
409#endif /* CONFIG_TSEC_ENET */
410
411/*
412 * Environment
413 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200415 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200417 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
418 #define CONFIG_ENV_SIZE 0x2000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500419
420/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200421#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
422#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500423
424#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200426 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200428 #define CONFIG_ENV_SIZE 0x2000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500429#endif
430
431#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500433
Jon Loeliger866e3082007-07-04 22:30:58 -0500434
435/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500436 * BOOTP options
437 */
438#define CONFIG_BOOTP_BOOTFILESIZE
439#define CONFIG_BOOTP_BOOTPATH
440#define CONFIG_BOOTP_GATEWAY
441#define CONFIG_BOOTP_HOSTNAME
442
443
444/*
Jon Loeliger866e3082007-07-04 22:30:58 -0500445 * Command line configuration.
446 */
447#include <config_cmd_default.h>
448
449#define CONFIG_CMD_I2C
450#define CONFIG_CMD_MII
451#define CONFIG_CMD_PING
452
Paul Gortmaker91e25762007-01-16 11:38:14 -0500453#if defined(CONFIG_PCI)
Paul Gortmakere4968652007-12-20 12:58:51 -0500454 #define CONFIG_CMD_PCI
Paul Gortmaker91e25762007-01-16 11:38:14 -0500455#endif
456
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger866e3082007-07-04 22:30:58 -0500458 #undef CONFIG_CMD_ENV
459 #undef CONFIG_CMD_LOADS
460#endif
461
Paul Gortmaker91e25762007-01-16 11:38:14 -0500462
463#undef CONFIG_WATCHDOG /* watchdog disabled */
464
465/*
466 * Miscellaneous configurable options
467 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_LONGHELP /* undef to save memory */
469#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
470#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500471
Jon Loeliger866e3082007-07-04 22:30:58 -0500472#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500474#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500476#endif
477
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
479#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
480#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
481#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500482
483/*
484 * For booting Linux, the board info and command line data
485 * have to be in the first 8 MB of memory, since this is
486 * the maximum mapped by the Linux kernel during initialization.
487 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Paul Gortmaker91e25762007-01-16 11:38:14 -0500489
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500491
492#if 1 /*528/264*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500494 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
495 HRCWL_DDR_TO_SCB_CLK_1X1 |\
496 HRCWL_CSB_TO_CLKIN |\
497 HRCWL_VCO_1X2 |\
498 HRCWL_CORE_TO_CSB_2X1)
499#elif 0 /*396/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500501 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
502 HRCWL_DDR_TO_SCB_CLK_1X1 |\
503 HRCWL_CSB_TO_CLKIN |\
504 HRCWL_VCO_1X4 |\
505 HRCWL_CORE_TO_CSB_3X1)
506#elif 0 /*264/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500508 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
509 HRCWL_DDR_TO_SCB_CLK_1X1 |\
510 HRCWL_CSB_TO_CLKIN |\
511 HRCWL_VCO_1X4 |\
512 HRCWL_CORE_TO_CSB_2X1)
513#elif 0 /*132/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500515 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
516 HRCWL_DDR_TO_SCB_CLK_1X1 |\
517 HRCWL_CSB_TO_CLKIN |\
518 HRCWL_VCO_1X4 |\
519 HRCWL_CORE_TO_CSB_1X1)
520#elif 0 /*264/264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500522 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
523 HRCWL_DDR_TO_SCB_CLK_1X1 |\
524 HRCWL_CSB_TO_CLKIN |\
525 HRCWL_VCO_1X4 |\
526 HRCWL_CORE_TO_CSB_1X1)
527#endif
528
529#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_HRCW_HIGH (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500531 HRCWH_PCI_HOST |\
532 HRCWH_64_BIT_PCI |\
533 HRCWH_PCI1_ARBITER_ENABLE |\
534 HRCWH_PCI2_ARBITER_DISABLE |\
535 HRCWH_CORE_ENABLE |\
536 HRCWH_FROM_0X00000100 |\
537 HRCWH_BOOTSEQ_DISABLE |\
538 HRCWH_SW_WATCHDOG_DISABLE |\
539 HRCWH_ROM_LOC_LOCAL_16BIT |\
540 HRCWH_TSEC1M_IN_GMII |\
541 HRCWH_TSEC2M_IN_GMII )
542#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_HRCW_HIGH (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500544 HRCWH_PCI_HOST |\
545 HRCWH_32_BIT_PCI |\
546 HRCWH_PCI1_ARBITER_ENABLE |\
547 HRCWH_PCI2_ARBITER_ENABLE |\
548 HRCWH_CORE_ENABLE |\
549 HRCWH_FROM_0X00000100 |\
550 HRCWH_BOOTSEQ_DISABLE |\
551 HRCWH_SW_WATCHDOG_DISABLE |\
552 HRCWH_ROM_LOC_LOCAL_16BIT |\
553 HRCWH_TSEC1M_IN_GMII |\
554 HRCWH_TSEC2M_IN_GMII )
555#endif
556
557/* System IO Config */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_SICRH SICRH_TSOBI1
559#define CONFIG_SYS_SICRL SICRL_LDP_A
Paul Gortmaker91e25762007-01-16 11:38:14 -0500560
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561#define CONFIG_SYS_HID0_INIT 0x000000000
562#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
Paul Gortmaker91e25762007-01-16 11:38:14 -0500563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564/* #define CONFIG_SYS_HID0_FINAL (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500565 HID0_ENABLE_INSTRUCTION_CACHE |\
566 HID0_ENABLE_M_BIT |\
567 HID0_ENABLE_ADDRESS_BROADCAST ) */
568
569
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_HID2 HID2_HBE
Paul Gortmaker91e25762007-01-16 11:38:14 -0500571
Becky Bruce31d82672008-05-08 19:02:12 -0500572#define CONFIG_HIGH_BATS 1 /* High BATs supported */
573
Paul Gortmaker91e25762007-01-16 11:38:14 -0500574/* DDR @ 0x00000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200575#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
576#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500577
578/* PCI @ 0x80000000 */
579#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
581#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
582#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
583#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500584#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200585#define CONFIG_SYS_IBAT1L (0)
586#define CONFIG_SYS_IBAT1U (0)
587#define CONFIG_SYS_IBAT2L (0)
588#define CONFIG_SYS_IBAT2U (0)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500589#endif
590
591#ifdef CONFIG_MPC83XX_PCI2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200592#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
593#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
594#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
595#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500596#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#define CONFIG_SYS_IBAT3L (0)
598#define CONFIG_SYS_IBAT3U (0)
599#define CONFIG_SYS_IBAT4L (0)
600#define CONFIG_SYS_IBAT4U (0)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500601#endif
602
603/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
605#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500606
607/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200608#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
609#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500610
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200611#define CONFIG_SYS_IBAT7L (0)
612#define CONFIG_SYS_IBAT7U (0)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500613
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
615#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
616#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
617#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
618#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
619#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
620#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
621#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
622#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
623#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
624#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
625#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
626#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
627#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
628#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
629#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Paul Gortmaker91e25762007-01-16 11:38:14 -0500630
631/*
632 * Internal Definitions
633 *
634 * Boot Flags
635 */
636#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
637#define BOOTFLAG_WARM 0x02 /* Software reboot */
638
Jon Loeliger866e3082007-07-04 22:30:58 -0500639#if defined(CONFIG_CMD_KGDB)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500640#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
641#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
642#endif
643
644/*
645 * Environment Configuration
646 */
647#define CONFIG_ENV_OVERWRITE
648
649#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500650#define CONFIG_HAS_ETH0
Paul Gortmaker91e25762007-01-16 11:38:14 -0500651#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d
652#define CONFIG_HAS_ETH1
653#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e
654#endif
655
656#define CONFIG_IPADDR 192.168.1.234
657
658#define CONFIG_HOSTNAME SBC8349
659#define CONFIG_ROOTPATH /tftpboot/rootfs
660#define CONFIG_BOOTFILE uImage
661
662#define CONFIG_SERVERIP 192.168.1.1
663#define CONFIG_GATEWAYIP 192.168.1.1
664#define CONFIG_NETMASK 255.255.255.0
665
Kim Phillipsb2115752008-04-24 14:07:38 -0500666#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500667
668#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
669#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
670
671#define CONFIG_BAUDRATE 115200
672
673#define CONFIG_EXTRA_ENV_SETTINGS \
674 "netdev=eth0\0" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200675 "hostname=sbc8349\0" \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500676 "nfsargs=setenv bootargs root=/dev/nfs rw " \
677 "nfsroot=${serverip}:${rootpath}\0" \
678 "ramargs=setenv bootargs root=/dev/ram rw\0" \
679 "addip=setenv bootargs ${bootargs} " \
680 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
681 ":${hostname}:${netdev}:off panic=1\0" \
682 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
683 "flash_nfs=run nfsargs addip addtty;" \
684 "bootm ${kernel_addr}\0" \
685 "flash_self=run ramargs addip addtty;" \
686 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
687 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
688 "bootm\0" \
689 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
690 "update=protect off fff00000 fff3ffff; " \
691 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100692 "upd=run load update\0" \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500693 "fdtaddr=400000\0" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200694 "fdtfile=sbc8349.dtb\0" \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500695 ""
696
697#define CONFIG_NFSBOOTCOMMAND \
698 "setenv bootargs root=/dev/nfs rw " \
699 "nfsroot=$serverip:$rootpath " \
700 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $loadaddr $bootfile;" \
703 "tftp $fdtaddr $fdtfile;" \
704 "bootm $loadaddr - $fdtaddr"
705
706#define CONFIG_RAMBOOTCOMMAND \
707 "setenv bootargs root=/dev/ram rw " \
708 "console=$consoledev,$baudrate $othbootargs;" \
709 "tftp $ramdiskaddr $ramdiskfile;" \
710 "tftp $loadaddr $bootfile;" \
711 "tftp $fdtaddr $fdtfile;" \
712 "bootm $loadaddr $ramdiskaddr $fdtaddr"
713
714#define CONFIG_BOOTCOMMAND "run flash_self"
715
716#endif /* __CONFIG_H */