blob: bb06e89b4ea00e9d13acbe5967c43a492b097f6a [file] [log] [blame]
Kim Phillips5e918a92008-01-16 00:38:05 -06001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Kim Phillips5e918a92008-01-16 00:38:05 -06007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050016#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Kim Phillips5e918a92008-01-16 00:38:05 -060017#define CONFIG_MPC837XERDB 1
Sinan Akman77d52ed2015-01-17 02:09:13 -050018#define CONFIG_DISPLAY_BOARDINFO
Kim Phillips5e918a92008-01-16 00:38:05 -060019
Wolfgang Denk2ae18242010-10-06 09:05:45 +020020#define CONFIG_SYS_TEXT_BASE 0xFE000000
21
Kim Phillips5e918a92008-01-16 00:38:05 -060022#define CONFIG_PCI 1
23
Anton Vorontsov2bd74602008-03-24 17:40:43 +030024#define CONFIG_BOARD_EARLY_INIT_F
Timur Tabi89c77842008-02-08 13:15:55 -060025#define CONFIG_MISC_INIT_R
Anton Vorontsovc9646ed2009-06-10 00:25:30 +040026#define CONFIG_HWCONFIG
Timur Tabi89c77842008-02-08 13:15:55 -060027
28/*
29 * On-board devices
30 */
31#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
32#define CONFIG_VSC7385_ENET
33
Kim Phillips5e918a92008-01-16 00:38:05 -060034/*
35 * System Clock Setup
36 */
37#ifdef CONFIG_PCISLAVE
38#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
39#else
40#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
Kim Phillipsbe9b56d2009-07-23 14:09:38 -050041#define CONFIG_PCIE
Kim Phillips5e918a92008-01-16 00:38:05 -060042#endif
43
44#ifndef CONFIG_SYS_CLK_FREQ
45#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
46#endif
47
48/*
49 * Hardware Reset Configuration Word
50 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_HRCW_LOW (\
Kim Phillips5e918a92008-01-16 00:38:05 -060052 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
53 HRCWL_DDR_TO_SCB_CLK_1X1 |\
54 HRCWL_SVCOD_DIV_2 |\
55 HRCWL_CSB_TO_CLKIN_5X1 |\
56 HRCWL_CORE_TO_CSB_2X1)
57
58#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips5e918a92008-01-16 00:38:05 -060060 HRCWH_PCI_AGENT |\
61 HRCWH_PCI1_ARBITER_DISABLE |\
62 HRCWH_CORE_ENABLE |\
63 HRCWH_FROM_0XFFF00100 |\
64 HRCWH_BOOTSEQ_DISABLE |\
65 HRCWH_SW_WATCHDOG_DISABLE |\
66 HRCWH_ROM_LOC_LOCAL_16BIT |\
67 HRCWH_RL_EXT_LEGACY |\
68 HRCWH_TSEC1M_IN_RGMII |\
69 HRCWH_TSEC2M_IN_RGMII |\
70 HRCWH_BIG_ENDIAN |\
71 HRCWH_LDP_CLEAR)
72#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips5e918a92008-01-16 00:38:05 -060074 HRCWH_PCI_HOST |\
75 HRCWH_PCI1_ARBITER_ENABLE |\
76 HRCWH_CORE_ENABLE |\
77 HRCWH_FROM_0X00000100 |\
78 HRCWH_BOOTSEQ_DISABLE |\
79 HRCWH_SW_WATCHDOG_DISABLE |\
80 HRCWH_ROM_LOC_LOCAL_16BIT |\
81 HRCWH_RL_EXT_LEGACY |\
82 HRCWH_TSEC1M_IN_RGMII |\
83 HRCWH_TSEC2M_IN_RGMII |\
84 HRCWH_BIG_ENDIAN |\
85 HRCWH_LDP_CLEAR)
86#endif
87
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088/* System performance - define the value i.e. CONFIG_SYS_XXX
Kim Phillips5e918a92008-01-16 00:38:05 -060089*/
90
91/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger5afe9722011-10-11 23:57:19 -050093#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Kim Phillips5e918a92008-01-16 00:38:05 -060094
95/* System Priority Control Regsiter */
Joe Hershberger5afe9722011-10-11 23:57:19 -050096#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
Kim Phillips5e918a92008-01-16 00:38:05 -060097
98/* System Clock Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
100#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500101#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600102
103/*
104 * System IO Config
105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_SICRH 0x08200000
107#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600108
109/*
110 * Output Buffer Impedance
111 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_OBIR 0x30100000
Kim Phillips5e918a92008-01-16 00:38:05 -0600113
114/*
115 * IMMR new address
116 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_IMMR 0xE0000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600118
119/*
Timur Tabi89c77842008-02-08 13:15:55 -0600120 * Device configurations
121 */
122
123/* Vitesse 7385 */
124
125#ifdef CONFIG_VSC7385_ENET
126
127#define CONFIG_TSEC2
128
129/* The flash address and size of the VSC7385 firmware image */
130#define CONFIG_VSC7385_IMAGE 0xFE7FE000
131#define CONFIG_VSC7385_IMAGE_SIZE 8192
132
133#endif
134
135/*
Kim Phillips5e918a92008-01-16 00:38:05 -0600136 * DDR Setup
137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
139#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
140#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
141#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
142#define CONFIG_SYS_83XX_DDR_USES_CS0
Kim Phillips5e918a92008-01-16 00:38:05 -0600143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
Kim Phillips5e918a92008-01-16 00:38:05 -0600145
146#undef CONFIG_DDR_ECC /* support DDR ECC function */
147#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
148
149#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
150
151/*
152 * Manually set up DDR parameters
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500155#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
156#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
157 | CSCONFIG_ODT_WR_ONLY_CURRENT \
158 | CSCONFIG_ROW_BIT_13 \
159 | CSCONFIG_COL_BIT_10)
Kim Phillips5e918a92008-01-16 00:38:05 -0600160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_DDR_TIMING_3 0x00000000
162#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600163 | (0 << TIMING_CFG0_WRT_SHIFT) \
164 | (0 << TIMING_CFG0_RRT_SHIFT) \
165 | (0 << TIMING_CFG0_WWT_SHIFT) \
166 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
167 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
168 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
169 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600170 /* 0x00260802 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600172 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
173 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
174 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
175 | (13 << TIMING_CFG1_REFREC_SHIFT) \
176 | (3 << TIMING_CFG1_WRREC_SHIFT) \
177 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
178 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600179 /* 0x3937d322 */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500180#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
181 | (5 << TIMING_CFG2_CPO_SHIFT) \
182 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
183 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
184 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
185 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
186 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
187 /* 0x02984cc8 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600188
Kim Phillips8eceeb72009-08-21 16:33:15 -0500189#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
190 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600191 /* 0x06090100 */
192
193#if defined(CONFIG_DDR_2T_TIMING)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500194#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500195 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
196 | SDRAM_CFG_32_BE \
197 | SDRAM_CFG_2T_EN)
198 /* 0x43088000 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600199#else
Joe Hershberger5afe9722011-10-11 23:57:19 -0500200#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500201 | SDRAM_CFG_SDRAM_TYPE_DDR2)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500202 /* 0x43000000 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600203#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Kim Phillips8eceeb72009-08-21 16:33:15 -0500205#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500206 | (0x0442 << SDRAM_MODE_SD_SHIFT))
207 /* 0x04400442 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_DDR_MODE2 0x00000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600209
210/*
211 * Memory test
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
214#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
215#define CONFIG_SYS_MEMTEST_END 0x0ef70010
Kim Phillips5e918a92008-01-16 00:38:05 -0600216
217/*
218 * The reserved memory
219 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200220#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips5e918a92008-01-16 00:38:05 -0600221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
223#define CONFIG_SYS_RAMBOOT
Kim Phillips5e918a92008-01-16 00:38:05 -0600224#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#undef CONFIG_SYS_RAMBOOT
Kim Phillips5e918a92008-01-16 00:38:05 -0600226#endif
227
Joe Hershberger5afe9722011-10-11 23:57:19 -0500228#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
229#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Kim Phillips5e918a92008-01-16 00:38:05 -0600230
231/*
232 * Initial RAM Base Address Setup
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_INIT_RAM_LOCK 1
235#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200236#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500237#define CONFIG_SYS_GBL_DATA_OFFSET \
238 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips5e918a92008-01-16 00:38:05 -0600239
240/*
241 * Local Bus Configuration & Clock Setup
242 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500243#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
244#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500246#define CONFIG_FSL_ELBC 1
Kim Phillips5e918a92008-01-16 00:38:05 -0600247
248/*
249 * FLASH on the Local Bus
250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200252#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
254#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
Kim Phillips5e918a92008-01-16 00:38:05 -0600255
Joe Hershberger5afe9722011-10-11 23:57:19 -0500256#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
257#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
258#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
Kim Phillips5e918a92008-01-16 00:38:05 -0600259
Joe Hershberger5afe9722011-10-11 23:57:19 -0500260 /* Window base at flash base */
261#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600263
Joe Hershberger5afe9722011-10-11 23:57:19 -0500264#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500265 | BR_PS_16 /* 16 bit port */ \
266 | BR_MS_GPCM /* MSEL = GPCM */ \
267 | BR_V) /* valid */
268#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600269 | OR_GPCM_XACS \
270 | OR_GPCM_SCY_9 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500271 | OR_GPCM_EHTR_SET \
Kim Phillips5e918a92008-01-16 00:38:05 -0600272 | OR_GPCM_EAD)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500273 /* 0xFF800191 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
276#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Kim Phillips5e918a92008-01-16 00:38:05 -0600277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#undef CONFIG_SYS_FLASH_CHECKSUM
279#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
280#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600281
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300282/*
283 * NAND Flash on the Local Bus
284 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500285#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500286#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500287 | BR_DECC_CHK_GEN /* Use HW ECC */ \
288 | BR_PS_8 /* 8 bit port */ \
289 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500290 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500291#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500292 | OR_FCM_CSCT \
293 | OR_FCM_CST \
294 | OR_FCM_CHT \
295 | OR_FCM_SCY_1 \
296 | OR_FCM_TRLX \
297 | OR_FCM_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500299#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300300
Timur Tabi89c77842008-02-08 13:15:55 -0600301/* Vitesse 7385 */
302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_VSC7385_BASE 0xF0000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600304
Timur Tabi89c77842008-02-08 13:15:55 -0600305#ifdef CONFIG_VSC7385_ENET
306
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500307#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
308 | BR_PS_8 \
309 | BR_MS_GPCM \
310 | BR_V)
311 /* 0xF0000801 */
312#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
313 | OR_GPCM_CSNT \
314 | OR_GPCM_XACS \
315 | OR_GPCM_SCY_15 \
316 | OR_GPCM_SETA \
317 | OR_GPCM_TRLX_SET \
318 | OR_GPCM_EHTR_SET \
319 | OR_GPCM_EAD)
320 /* 0xfffe09ff */
321
Joe Hershberger5afe9722011-10-11 23:57:19 -0500322 /* Access Base */
323#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500324#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Kim Phillips5e918a92008-01-16 00:38:05 -0600325
Timur Tabi89c77842008-02-08 13:15:55 -0600326#endif
327
Kim Phillips5e918a92008-01-16 00:38:05 -0600328/*
329 * Serial Port
330 */
331#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_NS16550_SERIAL
333#define CONFIG_SYS_NS16550_REG_SIZE 1
334#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips5e918a92008-01-16 00:38:05 -0600335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500337 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Kim Phillips5e918a92008-01-16 00:38:05 -0600338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
340#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips5e918a92008-01-16 00:38:05 -0600341
Anton Vorontsov2bd74602008-03-24 17:40:43 +0300342/* SERDES */
343#define CONFIG_FSL_SERDES
344#define CONFIG_FSL_SERDES1 0xe3000
345#define CONFIG_FSL_SERDES2 0xe3100
346
Kim Phillips5e918a92008-01-16 00:38:05 -0600347/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200348#define CONFIG_SYS_I2C
349#define CONFIG_SYS_I2C_FSL
350#define CONFIG_SYS_FSL_I2C_SPEED 400000
351#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
352#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
353#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Kim Phillips5e918a92008-01-16 00:38:05 -0600354
355/*
356 * Config on-board RTC
357 */
358#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600360
361/*
362 * General PCI
363 * Addresses are mapped 1-1.
364 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500365#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
366#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
367#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
369#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
370#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
371#define CONFIG_SYS_PCI_IO_BASE 0x00000000
372#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
373#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Kim Phillips5e918a92008-01-16 00:38:05 -0600374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
376#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
377#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600378
Anton Vorontsov7e915582009-02-19 18:20:52 +0300379#define CONFIG_SYS_PCIE1_BASE 0xA0000000
380#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
381#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
382#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
383#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
384#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
385#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
386#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
387#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
388
389#define CONFIG_SYS_PCIE2_BASE 0xC0000000
390#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
391#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
392#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
393#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
394#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
395#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
396#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
397#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
398
Kim Phillips5e918a92008-01-16 00:38:05 -0600399#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000400#define CONFIG_PCI_INDIRECT_BRIDGE
Kim Phillips5e918a92008-01-16 00:38:05 -0600401#define CONFIG_PCI_PNP /* do pci plug-and-play */
402
Kim Phillips5e918a92008-01-16 00:38:05 -0600403#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Kim Phillips5e918a92008-01-16 00:38:05 -0600405#endif /* CONFIG_PCI */
406
Kim Phillips5e918a92008-01-16 00:38:05 -0600407/*
408 * TSEC
409 */
Timur Tabi89c77842008-02-08 13:15:55 -0600410#ifdef CONFIG_TSEC_ENET
Kim Phillips5e918a92008-01-16 00:38:05 -0600411
Timur Tabi89c77842008-02-08 13:15:55 -0600412#define CONFIG_GMII /* MII PHY management */
413
414#define CONFIG_TSEC1
415
416#ifdef CONFIG_TSEC1
417#define CONFIG_HAS_ETH0
Kim Phillips5e918a92008-01-16 00:38:05 -0600418#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Kim Phillips5e918a92008-01-16 00:38:05 -0600420#define TSEC1_PHY_ADDR 2
Kim Phillips5e918a92008-01-16 00:38:05 -0600421#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Kim Phillips5e918a92008-01-16 00:38:05 -0600422#define TSEC1_PHYIDX 0
Timur Tabi89c77842008-02-08 13:15:55 -0600423#endif
Kim Phillips5e918a92008-01-16 00:38:05 -0600424
Timur Tabi89c77842008-02-08 13:15:55 -0600425#ifdef CONFIG_TSEC2
426#define CONFIG_HAS_ETH1
427#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600429#define TSEC2_PHY_ADDR 0x1c
430#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
431#define TSEC2_PHYIDX 0
432#endif
Kim Phillips5e918a92008-01-16 00:38:05 -0600433
434/* Options are: TSEC[0-1] */
435#define CONFIG_ETHPRIME "TSEC0"
436
Timur Tabi89c77842008-02-08 13:15:55 -0600437#endif
438
Kim Phillips5e918a92008-01-16 00:38:05 -0600439/*
Kim Phillips730e7922008-03-28 14:31:23 -0500440 * SATA
441 */
442#define CONFIG_LIBATA
443#define CONFIG_FSL_SATA
444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips730e7922008-03-28 14:31:23 -0500446#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500448#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
449#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500450#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500452#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
453#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500454
455#ifdef CONFIG_FSL_SATA
456#define CONFIG_LBA48
457#define CONFIG_CMD_SATA
458#define CONFIG_DOS_PARTITION
Kim Phillips730e7922008-03-28 14:31:23 -0500459#endif
460
461/*
Kim Phillips5e918a92008-01-16 00:38:05 -0600462 * Environment
463 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200465 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger5afe9722011-10-11 23:57:19 -0500466 #define CONFIG_ENV_ADDR \
467 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200468 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
469 #define CONFIG_ENV_SIZE 0x4000
Kim Phillips5e918a92008-01-16 00:38:05 -0600470#else
Joe Hershberger5afe9722011-10-11 23:57:19 -0500471 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200472 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200474 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips5e918a92008-01-16 00:38:05 -0600475#endif
476
477#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips5e918a92008-01-16 00:38:05 -0600479
480/*
481 * BOOTP options
482 */
483#define CONFIG_BOOTP_BOOTFILESIZE
484#define CONFIG_BOOTP_BOOTPATH
485#define CONFIG_BOOTP_GATEWAY
486#define CONFIG_BOOTP_HOSTNAME
487
Kim Phillips5e918a92008-01-16 00:38:05 -0600488/*
489 * Command line configuration.
490 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600491#define CONFIG_CMD_DATE
492
493#if defined(CONFIG_PCI)
494#define CONFIG_CMD_PCI
495#endif
496
Kim Phillips5e918a92008-01-16 00:38:05 -0600497#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500498#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillips5e918a92008-01-16 00:38:05 -0600499
500#undef CONFIG_WATCHDOG /* watchdog disabled */
501
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400502#define CONFIG_MMC 1
503
504#ifdef CONFIG_MMC
505#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800506#define CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400507#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400508#define CONFIG_GENERIC_MMC
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400509#define CONFIG_DOS_PARTITION
510#endif
511
Kim Phillips5e918a92008-01-16 00:38:05 -0600512/*
513 * Miscellaneous configurable options
514 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500515#define CONFIG_SYS_LONGHELP /* undef to save memory */
516#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips5e918a92008-01-16 00:38:05 -0600517
518#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600520#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600522#endif
523
Joe Hershberger5afe9722011-10-11 23:57:19 -0500524 /* Print Buffer Size */
525#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
526#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
527 /* Boot Argument Buffer Size */
528#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Kim Phillips5e918a92008-01-16 00:38:05 -0600529
530/*
531 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700532 * have to be in the first 256 MB of memory, since this is
Kim Phillips5e918a92008-01-16 00:38:05 -0600533 * the maximum mapped by the Linux kernel during initialization.
534 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500535#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kim Phillips5e918a92008-01-16 00:38:05 -0600536
537/*
538 * Core HID Setup
539 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500540#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500541#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
542 | HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_HID2 HID2_HBE
Kim Phillips5e918a92008-01-16 00:38:05 -0600544
545/*
546 * MMU Setup
547 */
548
Becky Bruce31d82672008-05-08 19:02:12 -0500549#define CONFIG_HIGH_BATS 1 /* High BATs supported */
550
Kim Phillips5e918a92008-01-16 00:38:05 -0600551/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200552#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
553#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Kim Phillips5e918a92008-01-16 00:38:05 -0600554
Joe Hershberger5afe9722011-10-11 23:57:19 -0500555#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500556 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500557 | BATL_MEMCOHERENCE)
558#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
559 | BATU_BL_256M \
560 | BATU_VS \
561 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
563#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Kim Phillips5e918a92008-01-16 00:38:05 -0600564
Joe Hershberger5afe9722011-10-11 23:57:19 -0500565#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500566 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500567 | BATL_MEMCOHERENCE)
568#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
569 | BATU_BL_256M \
570 | BATU_VS \
571 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
573#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Kim Phillips5e918a92008-01-16 00:38:05 -0600574
575/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500576#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500577 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500578 | BATL_CACHEINHIBIT \
579 | BATL_GUARDEDSTORAGE)
580#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
581 | BATU_BL_8M \
582 | BATU_VS \
583 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200584#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
585#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Kim Phillips5e918a92008-01-16 00:38:05 -0600586
587/* L2 Switch: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500588#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500589 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500590 | BATL_CACHEINHIBIT \
591 | BATL_GUARDEDSTORAGE)
592#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
593 | BATU_BL_128K \
594 | BATU_VS \
595 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
597#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Kim Phillips5e918a92008-01-16 00:38:05 -0600598
599/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500600#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500601 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500602 | BATL_MEMCOHERENCE)
603#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
604 | BATU_BL_32M \
605 | BATU_VS \
606 | BATU_VP)
607#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500608 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500609 | BATL_CACHEINHIBIT \
610 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200611#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Kim Phillips5e918a92008-01-16 00:38:05 -0600612
613/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500614#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500615#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
616 | BATU_BL_128K \
617 | BATU_VS \
618 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200619#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
620#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Kim Phillips5e918a92008-01-16 00:38:05 -0600621
622#ifdef CONFIG_PCI
623/* PCI MEM space: cacheable */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500624#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500625 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500626 | BATL_MEMCOHERENCE)
627#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
628 | BATU_BL_256M \
629 | BATU_VS \
630 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200631#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
632#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips5e918a92008-01-16 00:38:05 -0600633/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500634#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500635 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500636 | BATL_CACHEINHIBIT \
637 | BATL_GUARDEDSTORAGE)
638#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
639 | BATU_BL_256M \
640 | BATU_VS \
641 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200642#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
643#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips5e918a92008-01-16 00:38:05 -0600644#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200645#define CONFIG_SYS_IBAT6L (0)
646#define CONFIG_SYS_IBAT6U (0)
647#define CONFIG_SYS_IBAT7L (0)
648#define CONFIG_SYS_IBAT7U (0)
649#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
650#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
651#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
652#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips5e918a92008-01-16 00:38:05 -0600653#endif
654
Kim Phillips5e918a92008-01-16 00:38:05 -0600655#if defined(CONFIG_CMD_KGDB)
656#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Kim Phillips5e918a92008-01-16 00:38:05 -0600657#endif
658
659/*
660 * Environment Configuration
661 */
662#define CONFIG_ENV_OVERWRITE
663
Anton Vorontsov18e69a32008-03-14 23:20:18 +0300664#define CONFIG_HAS_FSL_DR_USB
Nikhil Badola6c3c5752014-10-20 16:31:01 +0530665#define CONFIG_USB_STORAGE
666#define CONFIG_USB_EHCI
667#define CONFIG_USB_EHCI_FSL
668#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov18e69a32008-03-14 23:20:18 +0300669
Joe Hershberger5afe9722011-10-11 23:57:19 -0500670#define CONFIG_NETDEV "eth1"
Kim Phillips5e918a92008-01-16 00:38:05 -0600671
672#define CONFIG_HOSTNAME mpc837x_rdb
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000673#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershberger5afe9722011-10-11 23:57:19 -0500674#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000675#define CONFIG_BOOTFILE "uImage"
Joe Hershberger5afe9722011-10-11 23:57:19 -0500676 /* U-Boot image on TFTP server */
677#define CONFIG_UBOOTPATH "u-boot.bin"
678#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
Kim Phillips5e918a92008-01-16 00:38:05 -0600679
Joe Hershberger5afe9722011-10-11 23:57:19 -0500680 /* default location for tftp and bootm */
681#define CONFIG_LOADADDR 800000
Kim Phillips5e918a92008-01-16 00:38:05 -0600682#define CONFIG_BAUDRATE 115200
683
Kim Phillips5e918a92008-01-16 00:38:05 -0600684#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500685 "netdev=" CONFIG_NETDEV "\0" \
686 "uboot=" CONFIG_UBOOTPATH "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600687 "tftpflash=tftp $loadaddr $uboot;" \
Marek Vasut5368c552012-09-23 17:41:24 +0200688 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
689 " +$filesize; " \
690 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
691 " +$filesize; " \
692 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
693 " $filesize; " \
694 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
695 " +$filesize; " \
696 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
697 " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500698 "fdtaddr=780000\0" \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500699 "fdtfile=" CONFIG_FDTFILE "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600700 "ramdiskaddr=1000000\0" \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500701 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600702 "console=ttyS0\0" \
703 "setbootargs=setenv bootargs " \
704 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
705 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500706 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
707 "$netdev:off " \
Kim Phillips5e918a92008-01-16 00:38:05 -0600708 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
709
710#define CONFIG_NFSBOOTCOMMAND \
711 "setenv rootdev /dev/nfs;" \
712 "run setbootargs;" \
713 "run setipargs;" \
714 "tftp $loadaddr $bootfile;" \
715 "tftp $fdtaddr $fdtfile;" \
716 "bootm $loadaddr - $fdtaddr"
717
718#define CONFIG_RAMBOOTCOMMAND \
719 "setenv rootdev /dev/ram;" \
720 "run setbootargs;" \
721 "tftp $ramdiskaddr $ramdiskfile;" \
722 "tftp $loadaddr $bootfile;" \
723 "tftp $fdtaddr $fdtfile;" \
724 "bootm $loadaddr $ramdiskaddr $fdtaddr"
725
Kim Phillips5e918a92008-01-16 00:38:05 -0600726#endif /* __CONFIG_H */