Masahiro Yamada | 8138581 | 2016-01-12 16:36:38 +0900 | [diff] [blame] | 1 | menu "Clock" |
| 2 | |
Simon Glass | f26c8a8 | 2015-06-23 15:39:15 -0600 | [diff] [blame] | 3 | config CLK |
| 4 | bool "Enable clock driver support" |
| 5 | depends on DM |
| 6 | help |
| 7 | This allows drivers to be provided for clock generators, including |
| 8 | oscillators and PLLs. Devices can use a common clock API to request |
| 9 | a particular clock rate and check on available clocks. Clocks can |
| 10 | feed into other clocks in a tree structure, with multiplexers to |
| 11 | choose the source for each clock. |
| 12 | |
Masahiro Yamada | 0543589 | 2015-08-12 07:31:46 +0900 | [diff] [blame] | 13 | config SPL_CLK |
Simon Glass | f26c8a8 | 2015-06-23 15:39:15 -0600 | [diff] [blame] | 14 | bool "Enable clock support in SPL" |
Wenyou Yang | 0712b67 | 2017-07-31 15:21:57 +0800 | [diff] [blame] | 15 | depends on CLK && SPL && SPL_DM |
Simon Glass | f26c8a8 | 2015-06-23 15:39:15 -0600 | [diff] [blame] | 16 | help |
| 17 | The clock subsystem adds a small amount of overhead to the image. |
| 18 | If this is acceptable and you have a need to use clock drivers in |
| 19 | SPL, enable this option. It might provide a cleaner interface to |
| 20 | setting up clocks within SPL, and allows the same drivers to be |
| 21 | used as U-Boot proper. |
Masahiro Yamada | 8138581 | 2016-01-12 16:36:38 +0900 | [diff] [blame] | 22 | |
Philipp Tomsich | 7c819e7 | 2017-06-29 01:45:01 +0200 | [diff] [blame] | 23 | config TPL_CLK |
| 24 | bool "Enable clock support in TPL" |
| 25 | depends on CLK && TPL_DM |
| 26 | help |
| 27 | The clock subsystem adds a small amount of overhead to the image. |
| 28 | If this is acceptable and you have a need to use clock drivers in |
| 29 | SPL, enable this option. It might provide a cleaner interface to |
| 30 | setting up clocks within TPL, and allows the same drivers to be |
| 31 | used as U-Boot proper. |
| 32 | |
Simon Glass | 747093d | 2022-04-30 00:56:53 -0600 | [diff] [blame] | 33 | config VPL_CLK |
| 34 | bool "Enable clock support in VPL" |
| 35 | depends on CLK && VPL_DM |
| 36 | help |
| 37 | The clock subsystem adds a small amount of overhead to the image. |
| 38 | If this is acceptable and you have a need to use clock drivers in |
| 39 | SPL, enable this option. It might provide a cleaner interface to |
| 40 | setting up clocks within TPL, and allows the same drivers to be |
| 41 | used as U-Boot proper. |
| 42 | |
| 43 | config CLK_BCM6345 |
| 44 | bool "Clock controller driver for BCM6345" |
| 45 | depends on CLK && ARCH_BMIPS |
| 46 | default y |
| 47 | help |
| 48 | This clock driver adds support for enabling and disabling peripheral |
| 49 | clocks on BCM6345 SoCs. HW has no rate changing capabilities. |
| 50 | |
| 51 | config CLK_BOSTON |
| 52 | def_bool y if TARGET_BOSTON |
| 53 | depends on CLK |
| 54 | select REGMAP |
| 55 | select SYSCON |
| 56 | help |
| 57 | Enable this to support the clocks |
| 58 | |
Lukasz Majewski | 1d7993d | 2019-06-24 15:50:45 +0200 | [diff] [blame] | 59 | config SPL_CLK_CCF |
| 60 | bool "SPL Common Clock Framework [CCF] support " |
Adam Ford | a074667 | 2019-08-24 13:50:34 -0500 | [diff] [blame] | 61 | depends on SPL |
Lukasz Majewski | 1d7993d | 2019-06-24 15:50:45 +0200 | [diff] [blame] | 62 | help |
| 63 | Enable this option if you want to (re-)use the Linux kernel's Common |
| 64 | Clock Framework [CCF] code in U-Boot's SPL. |
| 65 | |
Peng Fan | 0009763 | 2019-07-31 07:01:54 +0000 | [diff] [blame] | 66 | config SPL_CLK_COMPOSITE_CCF |
| 67 | bool "SPL Common Clock Framework [CCF] composite clk support " |
| 68 | depends on SPL_CLK_CCF |
| 69 | help |
| 70 | Enable this option if you want to (re-)use the Linux kernel's Common |
| 71 | Clock Framework [CCF] composite code in U-Boot's SPL. |
| 72 | |
Lukasz Majewski | 1d7993d | 2019-06-24 15:50:45 +0200 | [diff] [blame] | 73 | config CLK_CCF |
| 74 | bool "Common Clock Framework [CCF] support " |
Lukasz Majewski | 1d7993d | 2019-06-24 15:50:45 +0200 | [diff] [blame] | 75 | help |
| 76 | Enable this option if you want to (re-)use the Linux kernel's Common |
| 77 | Clock Framework [CCF] code in U-Boot's clock driver. |
| 78 | |
Peng Fan | 0009763 | 2019-07-31 07:01:54 +0000 | [diff] [blame] | 79 | config CLK_COMPOSITE_CCF |
| 80 | bool "Common Clock Framework [CCF] composite clk support " |
| 81 | depends on CLK_CCF |
| 82 | help |
| 83 | Enable this option if you want to (re-)use the Linux kernel's Common |
| 84 | Clock Framework [CCF] composite code in U-Boot's clock driver. |
| 85 | |
Sean Anderson | 7d4a785 | 2021-12-15 11:36:19 -0500 | [diff] [blame] | 86 | config CLK_BCM6345 |
| 87 | bool "Clock controller driver for BCM6345" |
| 88 | depends on CLK && ARCH_BMIPS |
| 89 | default y |
| 90 | help |
| 91 | This clock driver adds support for enabling and disabling peripheral |
| 92 | clocks on BCM6345 SoCs. HW has no rate changing capabilities. |
| 93 | |
| 94 | config CLK_BOSTON |
| 95 | def_bool y if TARGET_BOSTON |
| 96 | depends on CLK |
| 97 | select REGMAP |
| 98 | select SYSCON |
| 99 | help |
| 100 | Enable this to support the clocks |
| 101 | |
| 102 | config CLK_CDCE9XX |
| 103 | bool "Enable CDCD9XX clock driver" |
| 104 | depends on CLK |
| 105 | help |
| 106 | Enable the clock synthesizer driver for CDCE913/925/937/949 |
| 107 | series of chips. |
| 108 | |
Sean Anderson | 052bebe | 2021-12-15 11:36:20 -0500 | [diff] [blame] | 109 | config CLK_ICS8N3QV01 |
Sean Anderson | 7d4a785 | 2021-12-15 11:36:19 -0500 | [diff] [blame] | 110 | bool "Enable ICS8N3QV01 VCXO driver" |
| 111 | depends on CLK |
| 112 | help |
| 113 | Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled |
| 114 | Crystal Oscillator). The output frequency can be programmed via an |
| 115 | I2C interface. |
| 116 | |
Simon Glass | b4d00b2 | 2020-02-06 09:54:53 -0700 | [diff] [blame] | 117 | config CLK_INTEL |
| 118 | bool "Enable clock driver for Intel x86" |
| 119 | depends on CLK && X86 |
| 120 | help |
| 121 | This provides very basic support for clocks on Intel SoCs. The driver |
| 122 | is barely used at present but could be expanded as needs arise. |
| 123 | Much clock configuration in U-Boot is either set up by the FSP, or |
| 124 | set up by U-Boot itself but only statically. Thus the driver does not |
| 125 | support changing clock rates, only querying them. |
| 126 | |
Sean Anderson | 7d4a785 | 2021-12-15 11:36:19 -0500 | [diff] [blame] | 127 | config CLK_K210 |
| 128 | bool "Clock support for Kendryte K210" |
| 129 | depends on CLK |
| 130 | help |
| 131 | This enables support clock driver for Kendryte K210 platforms. |
| 132 | |
| 133 | config CLK_K210_SET_RATE |
| 134 | bool "Enable setting the Kendryte K210 PLL rate" |
| 135 | depends on CLK_K210 |
| 136 | help |
| 137 | Add functionality to calculate new rates for K210 PLLs. Enabling this |
| 138 | feature adds around 1K to U-Boot's final size. |
| 139 | |
| 140 | config CLK_MPC83XX |
| 141 | bool "Enable MPC83xx clock driver" |
| 142 | depends on CLK |
| 143 | help |
| 144 | Support for the clock driver of the MPC83xx series of SoCs. |
| 145 | |
Stefan Roese | b113c9b | 2020-07-30 13:56:16 +0200 | [diff] [blame] | 146 | config CLK_OCTEON |
| 147 | bool "Clock controller driver for Marvell MIPS Octeon" |
| 148 | depends on CLK && ARCH_OCTEON |
| 149 | default y |
| 150 | help |
| 151 | Enable this to support the clocks on Octeon MIPS platforms. |
| 152 | |
Sean Anderson | 7d4a785 | 2021-12-15 11:36:19 -0500 | [diff] [blame] | 153 | config SANDBOX_CLK_CCF |
| 154 | bool "Sandbox Common Clock Framework [CCF] support " |
| 155 | depends on SANDBOX |
| 156 | select CLK_CCF |
| 157 | help |
| 158 | Enable this option if you want to test the Linux kernel's Common |
| 159 | Clock Framework [CCF] code in U-Boot's Sandbox clock driver. |
| 160 | |
| 161 | config CLK_SCMI |
| 162 | bool "Enable SCMI clock driver" |
AKASHI Takahiro | 45a0052 | 2023-06-12 10:14:49 +0900 | [diff] [blame] | 163 | depends on CLK |
Sean Anderson | 7d4a785 | 2021-12-15 11:36:19 -0500 | [diff] [blame] | 164 | depends on SCMI_FIRMWARE |
| 165 | help |
| 166 | Enable this option if you want to support clock devices exposed |
| 167 | by a SCMI agent based on SCMI clock protocol communication |
| 168 | with a SCMI server. |
| 169 | |
Jonas Karlman | 2229758 | 2023-04-17 19:07:18 +0000 | [diff] [blame] | 170 | config SPL_CLK_SCMI |
| 171 | bool "Enable SCMI clock driver in SPL" |
| 172 | depends on SCMI_FIRMWARE && SPL_FIRMWARE |
| 173 | help |
| 174 | Enable this option if you want to support clock devices exposed |
| 175 | by a SCMI agent based on SCMI clock protocol communication |
| 176 | with a SCMI server in SPL. |
| 177 | |
Eugeniy Paltsev | e80dac0 | 2017-12-10 21:20:08 +0300 | [diff] [blame] | 178 | config CLK_HSDK |
Eugeniy Paltsev | 80a7674 | 2020-05-07 22:20:10 +0300 | [diff] [blame] | 179 | bool "Enable cgu clock driver for HSDK boards" |
| 180 | depends on CLK && TARGET_HSDK |
Eugeniy Paltsev | e80dac0 | 2017-12-10 21:20:08 +0300 | [diff] [blame] | 181 | help |
Eugeniy Paltsev | 80a7674 | 2020-05-07 22:20:10 +0300 | [diff] [blame] | 182 | Enable this to support the cgu clocks on Synopsys ARC HSDK and |
| 183 | Synopsys ARC HSDK-4xD boards |
Eugeniy Paltsev | e80dac0 | 2017-12-10 21:20:08 +0300 | [diff] [blame] | 184 | |
Sean Anderson | 7d4a785 | 2021-12-15 11:36:19 -0500 | [diff] [blame] | 185 | config CLK_VERSACLOCK |
| 186 | tristate "Enable VersaClock 5/6 devices" |
| 187 | depends on CLK |
| 188 | depends on CLK_CCF |
| 189 | depends on OF_CONTROL |
| 190 | help |
| 191 | This driver supports the IDT VersaClock 5 and VersaClock 6 |
| 192 | programmable clock generators. |
| 193 | |
Siva Durga Prasad Paladugu | 9510508 | 2019-06-23 12:24:57 +0530 | [diff] [blame] | 194 | config CLK_VERSAL |
| 195 | bool "Enable clock driver support for Versal" |
Jay Buddhabhatti | ff33227 | 2022-09-19 14:21:05 +0200 | [diff] [blame] | 196 | depends on (ARCH_VERSAL || ARCH_VERSAL_NET) |
Algapally Santosh Sagar | 6d87b15 | 2023-02-01 02:55:53 -0700 | [diff] [blame] | 197 | imply ZYNQMP_FIRMWARE |
Siva Durga Prasad Paladugu | 9510508 | 2019-06-23 12:24:57 +0530 | [diff] [blame] | 198 | help |
| 199 | This clock driver adds support for clock realted settings for |
| 200 | Versal platform. |
| 201 | |
Liviu Dudau | a71e907 | 2018-09-17 17:50:00 +0100 | [diff] [blame] | 202 | config CLK_VEXPRESS_OSC |
| 203 | bool "Enable driver for Arm Versatile Express OSC clock generators" |
| 204 | depends on CLK && VEXPRESS_CONFIG |
| 205 | help |
| 206 | This clock driver adds support for clock generators present on |
| 207 | Arm Versatile Express platforms. |
| 208 | |
Zhengxun | 2b157d8 | 2021-06-11 15:10:48 +0000 | [diff] [blame] | 209 | config CLK_XLNX_CLKWZRD |
| 210 | bool "Xilinx Clocking Wizard" |
| 211 | depends on CLK |
| 212 | help |
| 213 | Support for the Xilinx Clocking Wizard IP core clock generator. |
| 214 | The wizard support for dynamically reconfiguring the clocking |
| 215 | primitives for Multiply, Divide, Phase Shift/Offset, or Duty |
| 216 | Cycle. Limited by U-Boot clk uclass without set_phase API and |
| 217 | set_duty_cycle API, this driver only supports set_rate to modify |
| 218 | the frequency. |
| 219 | |
Sean Anderson | 7d4a785 | 2021-12-15 11:36:19 -0500 | [diff] [blame] | 220 | config CLK_ZYNQ |
| 221 | bool "Enable clock driver support for Zynq" |
| 222 | depends on CLK && ARCH_ZYNQ |
| 223 | default y |
| 224 | help |
| 225 | This clock driver adds support for clock related settings for |
| 226 | Zynq platform. |
| 227 | |
Siva Durga Prasad Paladugu | 128ec1f | 2016-11-15 16:15:41 +0530 | [diff] [blame] | 228 | config CLK_ZYNQMP |
| 229 | bool "Enable clock driver support for ZynqMP" |
| 230 | depends on ARCH_ZYNQMP |
Algapally Santosh Sagar | 6d87b15 | 2023-02-01 02:55:53 -0700 | [diff] [blame] | 231 | imply ZYNQMP_FIRMWARE |
Siva Durga Prasad Paladugu | 128ec1f | 2016-11-15 16:15:41 +0530 | [diff] [blame] | 232 | help |
| 233 | This clock driver adds support for clock realted settings for |
| 234 | ZynqMP platform. |
| 235 | |
Anup Patel | d04c79d | 2019-06-25 06:31:02 +0000 | [diff] [blame] | 236 | source "drivers/clk/analogbits/Kconfig" |
Wenyou Yang | 9e5935c | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 237 | source "drivers/clk/at91/Kconfig" |
Jagan Teki | cf68225 | 2018-07-30 18:26:18 +0530 | [diff] [blame] | 238 | source "drivers/clk/exynos/Kconfig" |
Peng Fan | f77d441 | 2018-10-18 14:28:30 +0200 | [diff] [blame] | 239 | source "drivers/clk/imx/Kconfig" |
Jerome Brunet | f5abfed | 2019-02-10 14:54:30 +0100 | [diff] [blame] | 240 | source "drivers/clk/meson/Kconfig" |
Padmarao Begari | 2f27c92 | 2021-01-15 08:20:38 +0530 | [diff] [blame] | 241 | source "drivers/clk/microchip/Kconfig" |
Marek BehĂșn | 82a248d | 2018-04-24 17:21:25 +0200 | [diff] [blame] | 242 | source "drivers/clk/mvebu/Kconfig" |
Manivannan Sadhasivam | ae485b5 | 2018-06-14 23:38:35 +0530 | [diff] [blame] | 243 | source "drivers/clk/owl/Kconfig" |
Jagan Teki | cf68225 | 2018-07-30 18:26:18 +0530 | [diff] [blame] | 244 | source "drivers/clk/renesas/Kconfig" |
Jagan Teki | 0d47bc7 | 2018-12-22 21:32:49 +0530 | [diff] [blame] | 245 | source "drivers/clk/sunxi/Kconfig" |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 246 | source "drivers/clk/sifive/Kconfig" |
Yanhong Wang | c13fe7c | 2023-03-29 11:42:13 +0800 | [diff] [blame] | 247 | source "drivers/clk/starfive/Kconfig" |
Patrick Delaunay | b992933 | 2022-05-19 17:56:45 +0200 | [diff] [blame] | 248 | source "drivers/clk/stm32/Kconfig" |
Jagan Teki | cf68225 | 2018-07-30 18:26:18 +0530 | [diff] [blame] | 249 | source "drivers/clk/tegra/Kconfig" |
Dario Binacchi | d09f063 | 2020-12-30 00:06:32 +0100 | [diff] [blame] | 250 | source "drivers/clk/ti/Kconfig" |
Jagan Teki | cf68225 | 2018-07-30 18:26:18 +0530 | [diff] [blame] | 251 | source "drivers/clk/uniphier/Kconfig" |
Masahiro Yamada | 48264d9 | 2016-02-02 21:11:32 +0900 | [diff] [blame] | 252 | |
Masahiro Yamada | 8138581 | 2016-01-12 16:36:38 +0900 | [diff] [blame] | 253 | endmenu |