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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_ERIC 1 /* ...on a ERIC board */
39
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* run board_early_init_f() */
wdenke2211742002-11-02 23:30:20 +000041
42#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
43
44#if 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020045#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
wdenke2211742002-11-02 23:30:20 +000046#endif
47#if 0
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020048#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
wdenke2211742002-11-02 23:30:20 +000049#endif
50#if 0
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020051#define CONFIG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020052#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
53#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
wdenke2211742002-11-02 23:30:20 +000054#endif /* total size of a X1240 is 2048 bytes */
55
56#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
58#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenke2211742002-11-02 23:30:20 +000059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */
61#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */
wdenke2211742002-11-02 23:30:20 +000062#define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_I2C_RTC_ADDR 0x6F /* and one for RTC */
wdenke2211742002-11-02 23:30:20 +000064
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020065#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020066#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020067#undef CONFIG_ENV_IS_IN_EEPROM
wdenke2211742002-11-02 23:30:20 +000068#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020069#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020070#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020071#undef CONFIG_ENV_IS_IN_EEPROM
wdenke2211742002-11-02 23:30:20 +000072#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020073#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020074#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020075#undef CONFIG_ENV_IS_IN_FLASH
wdenke2211742002-11-02 23:30:20 +000076#endif
77#endif
78#endif
79
80#define CONFIG_BAUDRATE 115200
81#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
82
83#if 1
84#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
85#else
86#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
87#endif
88
89#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \
90 "nfsroot=192.168.1.2:/eric_root_devel " \
91 "ip=192.168.1.22:192.168.1.2"
92
93#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenke2211742002-11-02 23:30:20 +000095
Ben Warren96e21f82008-10-27 23:50:15 -070096#define CONFIG_PPC4xx_EMAC
wdenke2211742002-11-02 23:30:20 +000097#define CONFIG_MII 1 /* MII PHY management */
98#define CONFIG_PHY_ADDR 1 /* PHY address */
99
wdenke2211742002-11-02 23:30:20 +0000100
101/*
Jon Loeliger11799432007-07-10 09:02:57 -0500102 * BOOTP options
103 */
104#define CONFIG_BOOTP_BOOTFILESIZE
105#define CONFIG_BOOTP_BOOTPATH
106#define CONFIG_BOOTP_GATEWAY
107#define CONFIG_BOOTP_HOSTNAME
108
109
110/*
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500111 * Command line configuration.
wdenke2211742002-11-02 23:30:20 +0000112 */
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500113#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +0000114
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500115#define CONFIG_CMD_PCI
116#define CONFIG_CMD_IRQ
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500117#define CONFIG_CMD_SAVEENV
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500118#define CONFIG_CMD_FLASH
119
wdenke2211742002-11-02 23:30:20 +0000120
121#undef CONFIG_WATCHDOG /* watchdog disabled */
122
123/*
124 * Miscellaneous configurable options
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#undef CONFIG_SYS_LONGHELP /* undef to save memory */
127#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500128#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000130#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000132#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
134#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
135#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
138#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180
wdenke2211742002-11-02 23:30:20 +0000141
142/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_BAUDRATE_TABLE \
wdenke2211742002-11-02 23:30:20 +0000144 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
145 57600, 115200, 230400, 460800, 921600 }
146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
148#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenke2211742002-11-02 23:30:20 +0000149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000151
152/*-----------------------------------------------------------------------
153 * PCI stuff
154 *-----------------------------------------------------------------------
155 */
156#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
157#define PCI_HOST_FORCE 1 /* configure as pci host */
158#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
159
160#define CONFIG_PCI /* include pci support */
161#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
162#undef CONFIG_PCI_PNP /* no pci plug-and-play */
wdenk8bde7f72003-06-27 21:31:46 +0000163 /* resource configuration */
wdenke2211742002-11-02 23:30:20 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */
166#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */
167#define CONFIG_SYS_PCI_PTM1LA 0xFFFC0000 /* point to flash */
168#define CONFIG_SYS_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */
169#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
170#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
171#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
172#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenke2211742002-11-02 23:30:20 +0000173
174/*-----------------------------------------------------------------------
175 * External peripheral base address
176 *-----------------------------------------------------------------------
177 */
178/* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */
179/* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */
180/* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */
181/* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */
182/* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */
183/* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */
184/* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */
185/* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */
186
187/* ----------------------------------------------------------------------- */
188/* Memory Bank 0 (Flash) initialization */
189/* ----------------------------------------------------------------------- */
190#define CS0_AP 0x9B015480
191#define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
192/* ----------------------------------------------------------------------- */
193/* Memory Bank 1 (NVRAM/RTC) initialization */
194/* ----------------------------------------------------------------------- */
195#define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
196#define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
197 /* ----------------------------------------------------------------------- */
198 /* Memory Bank 2 (A/D converter) initialization */
199 /* ----------------------------------------------------------------------- */
200#define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
201#define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
202/* ----------------------------------------------------------------------- */
203/* Memory Bank 3 (Ethernet PHY Reset) initialization */
204/* ----------------------------------------------------------------------- */
205#define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
206#define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
207/* ----------------------------------------------------------------------- */
208/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
209/* ----------------------------------------------------------------------- */
210#define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
211#define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
212/* ----------------------------------------------------------------------- */
213/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
214/* ----------------------------------------------------------------------- */
215#define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
216#define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
217/* ----------------------------------------------------------------------- */
218/* Memory Bank 6 (CPU LED0) initialization */
219/* ----------------------------------------------------------------------- */
220#define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
221#define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
222/* ----------------------------------------------------------------------- */
223/* Memory Bank 7 (CPU LED1) initialization */
224/* ----------------------------------------------------------------------- */
225#define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
226#define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_NVRAM_REG_BASE_ADDR 0xF0000000
229#define CONFIG_SYS_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8)
230#define CONFIG_SYS_ADC_REG_BASE_ADDR 0xF0100000
231#define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
232#define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
233#define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
234#define CONFIG_SYS_LED0_REG_BASE_ADDR 0xF0500000
235#define CONFIG_SYS_LED1_REG_BASE_ADDR 0xF0600000
wdenke2211742002-11-02 23:30:20 +0000236
237
238/* SDRAM CONFIG */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_SDRAM_MANUALLY 1
240#define CONFIG_SYS_SDRAM_SINGLE_BANK 1
wdenke2211742002-11-02 23:30:20 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#ifdef CONFIG_SYS_SDRAM_MANUALLY
wdenke2211742002-11-02 23:30:20 +0000243/*-----------------------------------------------------------------------
244 * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
245 *----------------------------------------------------------------------*/
246#define MB0CF 0x00062001 /* 32MB @ 0 */
247/*-----------------------------------------------------------------------
248 * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
249 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
wdenke2211742002-11-02 23:30:20 +0000251#define MB1CF 0x0 /* 0MB @ 32MB */
252#else
253#define MB1CF 0x02062001 /* 32MB @ 32MB */
254#endif
255/*-----------------------------------------------------------------------
256 * Set MB2CF for bank 2. off
257 *----------------------------------------------------------------------*/
258#define MB2CF 0x0 /* 0MB */
259/*-----------------------------------------------------------------------
260 * Set MB3CF for bank 3. off
261 *----------------------------------------------------------------------*/
262#define MB3CF 0x0 /* 0MB */
263
264#define SDTR_100 0x0086400D
265#define RTR_100 0x05F0
266#define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */
267#define RTR_66 0x03f8
268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#endif /* CONFIG_SYS_SDRAM_MANUALLY */
wdenke2211742002-11-02 23:30:20 +0000270
271
272/*-----------------------------------------------------------------------
273 * Start addresses for the final memory configuration
274 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_SDRAM_BASE 0x00000000
278#define CONFIG_SYS_SDRAM_SIZE 32
279#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* 8 MByte Flash */
280#define CONFIG_SYS_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */
281/*#define CONFIG_SYS_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */
282#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
283#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000284
285/*
286 * For booting Linux, the board info and command line data
287 * have to be in the first 8 MB of memory, since this is
288 * the maximum mapped by the Linux kernel during initialization.
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000291/*-----------------------------------------------------------------------
292 * FLASH organization
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
295#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
296#define CONFIG_SYS_FLASH_16BIT 1 /* Rom 16 bit data bus */
wdenke2211742002-11-02 23:30:20 +0000297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
299#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000300
301/* BEG ENVIRONNEMENT FLASH */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200302#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200303#define CONFIG_ENV_SECT_SIZE (128*1024)
wdenke2211742002-11-02 23:30:20 +0000304
305#if 0 /* force ENV to be NOT embedded */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200306#define CONFIG_ENV_ADDR 0xfffa0000
wdenke2211742002-11-02 23:30:20 +0000307#else /* force ENV to be embedded */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200308#define CONFIG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
310/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE)*/
311#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
wdenke2211742002-11-02 23:30:20 +0000312#endif
313
314#endif
315/* END ENVIRONNEMENT FLASH */
316/*-----------------------------------------------------------------------
317 * NVRAM organization
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_REG_BASE_ADDR /* NVRAM base address */
320#define CONFIG_SYS_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */
wdenke2211742002-11-02 23:30:20 +0000321
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200322#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200323#define CONFIG_ENV_SIZE 0x7F8 /* Size of Environment vars */
324#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
wdenke2211742002-11-02 23:30:20 +0000326#endif
wdenke2211742002-11-02 23:30:20 +0000327
328/*
329 * Init Memory Controller:
330 *
331 * BR0/1 and OR0/1 (FLASH)
332 */
333
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200334#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
wdenke2211742002-11-02 23:30:20 +0000335#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
336
337
338/* Configuration Port location */
339/* #define CONFIG_PORT_ADDR 0xF0000500 */
340
341/*-----------------------------------------------------------------------
342 * Definitions for initial stack pointer and data area (in DPRAM)
343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
345#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
346#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
347#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
348#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000349
350/*-----------------------------------------------------------------------
351 * Definitions for Serial Presence Detect EEPROM address
352 * (to get SDRAM settings)
353 */
354#define SPD_EEPROM_ADDRESS 0x50
355
356/*
357 * Internal Definitions
358 *
359 * Boot Flags
360 */
361#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
362#define BOOTFLAG_WARM 0x02 /* Software reboot */
363
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500364#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000365#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
366#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
367#endif
368#endif /* __CONFIG_H */