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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
wdenke35745b2004-04-18 23:32:11 +00005 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
wdenk945af8d2003-07-16 21:53:01 +00008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
wdenk96e48cf2003-08-05 18:22:44 +000029#include <pci.h>
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020030#include <asm/processor.h>
Grant Likelycf2817a2007-09-06 09:46:23 -060031#include <libfdt.h>
Ben Warren19403632008-08-31 10:03:22 -070032#include <netdev.h>
Stefan Roesee59581c2006-11-28 17:55:49 +010033
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010034#if defined(CONFIG_LITE5200B)
35#include "mt46v32m16.h"
wdenke35745b2004-04-18 23:32:11 +000036#else
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010037# if defined(CONFIG_MPC5200_DDR)
38# include "mt46v16m16-75.h"
39# else
wdenke35745b2004-04-18 23:32:11 +000040#include "mt48lc16m16a2-75.h"
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010041# endif
wdenke35745b2004-04-18 23:32:11 +000042#endif
Domen Puncerd3832e82007-04-16 14:00:13 +020043
44#ifdef CONFIG_LITE5200B_PM
45/* u-boot part of low-power mode implementation */
46#define SAVED_ADDR (*(void **)0x00000000)
47#define PSC2_4 0x02
48
49void lite5200b_wakeup(void)
50{
51 unsigned char wakeup_pin;
52 void (*linux_wakeup)(void);
53
54 /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
55 * from low power mode */
56 *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
57 __asm__ volatile ("sync");
58
59 wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
60 if (wakeup_pin & PSC2_4)
61 return;
62
63 /* acknowledge to "QT"
64 * by holding pin at 1 for 10 uS */
65 *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
66 __asm__ volatile ("sync");
67 *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
68 __asm__ volatile ("sync");
69 udelay(10);
70
71 /* put ram out of self-refresh */
72 *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
73 __asm__ volatile ("sync");
74 *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
75 __asm__ volatile ("sync");
76 *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
77 __asm__ volatile ("sync");
78 udelay(10); /* wait a bit */
79
80 /* jump back to linux kernel code */
81 linux_wakeup = SAVED_ADDR;
82 printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
83 linux_wakeup);
84 linux_wakeup();
85}
86#else
87#define lite5200b_wakeup()
88#endif
89
wdenkd94f92c2003-08-28 09:41:22 +000090#ifndef CFG_RAMBOOT
wdenke0ac62d2003-08-17 18:55:18 +000091static void sdram_start (int hi_addr)
92{
93 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
94
wdenkb2001f22003-12-20 22:45:10 +000095 /* unlock mode register */
wdenke35745b2004-04-18 23:32:11 +000096 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
97 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +000098
wdenkb2001f22003-12-20 22:45:10 +000099 /* precharge all banks */
wdenke35745b2004-04-18 23:32:11 +0000100 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
101 __asm__ volatile ("sync");
102
103#if SDRAM_DDR
wdenkb2001f22003-12-20 22:45:10 +0000104 /* set mode register: extended mode */
wdenke35745b2004-04-18 23:32:11 +0000105 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
106 __asm__ volatile ("sync");
107
wdenkb2001f22003-12-20 22:45:10 +0000108 /* set mode register: reset DLL */
wdenke35745b2004-04-18 23:32:11 +0000109 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
110 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +0000111#endif
wdenke35745b2004-04-18 23:32:11 +0000112
113 /* precharge all banks */
114 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
115 __asm__ volatile ("sync");
116
wdenkf8d813e2004-03-02 14:05:39 +0000117 /* auto refresh */
wdenke35745b2004-04-18 23:32:11 +0000118 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
119 __asm__ volatile ("sync");
120
wdenke0ac62d2003-08-17 18:55:18 +0000121 /* set mode register */
wdenke35745b2004-04-18 23:32:11 +0000122 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
123 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +0000124
wdenke0ac62d2003-08-17 18:55:18 +0000125 /* normal operation */
wdenke35745b2004-04-18 23:32:11 +0000126 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
127 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +0000128}
wdenkd94f92c2003-08-28 09:41:22 +0000129#endif
wdenke0ac62d2003-08-17 18:55:18 +0000130
wdenke35745b2004-04-18 23:32:11 +0000131/*
132 * ATTENTION: Although partially referenced initdram does NOT make real use
133 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
134 * is something else than 0x00000000.
135 */
136
137#if defined(CONFIG_MPC5200)
Becky Bruce9973e3c2008-06-09 16:03:40 -0500138phys_size_t initdram (int board_type)
wdenk945af8d2003-07-16 21:53:01 +0000139{
wdenkd94f92c2003-08-28 09:41:22 +0000140 ulong dramsize = 0;
wdenkb2001f22003-12-20 22:45:10 +0000141 ulong dramsize2 = 0;
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200142 uint svr, pvr;
143
wdenk945af8d2003-07-16 21:53:01 +0000144#ifndef CFG_RAMBOOT
wdenkd94f92c2003-08-28 09:41:22 +0000145 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +0000146
wdenke35745b2004-04-18 23:32:11 +0000147 /* setup SDRAM chip selects */
wdenke0ac62d2003-08-17 18:55:18 +0000148 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
149 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
wdenke35745b2004-04-18 23:32:11 +0000150 __asm__ volatile ("sync");
wdenk945af8d2003-07-16 21:53:01 +0000151
wdenkb2001f22003-12-20 22:45:10 +0000152 /* setup config registers */
wdenke35745b2004-04-18 23:32:11 +0000153 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
154 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
155 __asm__ volatile ("sync");
wdenkd4ca31c2004-01-02 14:00:00 +0000156
wdenke35745b2004-04-18 23:32:11 +0000157#if SDRAM_DDR
158 /* set tap delay */
159 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
160 __asm__ volatile ("sync");
wdenkb2001f22003-12-20 22:45:10 +0000161#endif
wdenk945af8d2003-07-16 21:53:01 +0000162
wdenke35745b2004-04-18 23:32:11 +0000163 /* find RAM size using SDRAM CS0 only */
wdenke0ac62d2003-08-17 18:55:18 +0000164 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200165 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000166 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200167 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000168 if (test1 > test2) {
169 sdram_start(0);
170 dramsize = test1;
171 } else {
172 dramsize = test2;
173 }
wdenke35745b2004-04-18 23:32:11 +0000174
175 /* memory smaller than 1MB is impossible */
176 if (dramsize < (1 << 20)) {
177 dramsize = 0;
178 }
wdenk5cf91d62004-04-23 20:32:05 +0000179
wdenke35745b2004-04-18 23:32:11 +0000180 /* set SDRAM CS0 size according to the amount of RAM found */
181 if (dramsize > 0) {
182 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
183 } else {
184 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
185 }
186
wdenke35745b2004-04-18 23:32:11 +0000187 /* let SDRAM CS1 start right after CS0 */
wdenkb2001f22003-12-20 22:45:10 +0000188 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
wdenke35745b2004-04-18 23:32:11 +0000189
190 /* find RAM size using SDRAM CS1 only */
wdenk07cc0992005-05-05 00:04:14 +0000191 if (!dramsize)
wdenka6310922005-04-21 21:10:22 +0000192 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200193 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000194 if (!dramsize) {
195 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200196 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000197 }
wdenkb2001f22003-12-20 22:45:10 +0000198 if (test1 > test2) {
199 sdram_start(0);
200 dramsize2 = test1;
201 } else {
202 dramsize2 = test2;
203 }
wdenk5cf91d62004-04-23 20:32:05 +0000204
wdenke35745b2004-04-18 23:32:11 +0000205 /* memory smaller than 1MB is impossible */
206 if (dramsize2 < (1 << 20)) {
207 dramsize2 = 0;
208 }
wdenk5cf91d62004-04-23 20:32:05 +0000209
wdenke35745b2004-04-18 23:32:11 +0000210 /* set SDRAM CS1 size according to the amount of RAM found */
211 if (dramsize2 > 0) {
212 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
213 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
214 } else {
215 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
216 }
wdenke0ac62d2003-08-17 18:55:18 +0000217
wdenke35745b2004-04-18 23:32:11 +0000218#else /* CFG_RAMBOOT */
219
220 /* retrieve size of memory connected to SDRAM CS0 */
221 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
222 if (dramsize >= 0x13) {
223 dramsize = (1 << (dramsize - 0x13)) << 20;
224 } else {
225 dramsize = 0;
226 }
227
228 /* retrieve size of memory connected to SDRAM CS1 */
229 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
230 if (dramsize2 >= 0x13) {
231 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
232 } else {
233 dramsize2 = 0;
234 }
235
wdenkd94f92c2003-08-28 09:41:22 +0000236#endif /* CFG_RAMBOOT */
wdenkb2001f22003-12-20 22:45:10 +0000237
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200238 /*
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200239 * On MPC5200B we need to set the special configuration delay in the
240 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200241 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
242 *
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200243 * "The SDelay should be written to a value of 0x00000004. It is
244 * required to account for changes caused by normal wafer processing
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200245 * parameters."
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200246 */
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200247 svr = get_svr();
248 pvr = get_pvr();
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200249 if ((SVR_MJREV(svr) >= 2) &&
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200250 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
251
252 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
253 __asm__ volatile ("sync");
254 }
255
Domen Puncerd3832e82007-04-16 14:00:13 +0200256 lite5200b_wakeup();
257
wdenke35745b2004-04-18 23:32:11 +0000258 return dramsize + dramsize2;
259}
260
261#elif defined(CONFIG_MGT5100)
262
Becky Bruce9973e3c2008-06-09 16:03:40 -0500263phys_size_t initdram (int board_type)
wdenke35745b2004-04-18 23:32:11 +0000264{
265 ulong dramsize = 0;
266#ifndef CFG_RAMBOOT
267 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +0000268
wdenke35745b2004-04-18 23:32:11 +0000269 /* setup and enable SDRAM chip selects */
270 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
271 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
272 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
273 __asm__ volatile ("sync");
274
275 /* setup config registers */
276 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
277 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
278
279 /* address select register */
280 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
281 __asm__ volatile ("sync");
282
283 /* find RAM size */
284 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200285 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke35745b2004-04-18 23:32:11 +0000286 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200287 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke35745b2004-04-18 23:32:11 +0000288 if (test1 > test2) {
289 sdram_start(0);
290 dramsize = test1;
291 } else {
292 dramsize = test2;
293 }
294
295 /* set SDRAM end address according to size */
296 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
wdenk5cf91d62004-04-23 20:32:05 +0000297
wdenke35745b2004-04-18 23:32:11 +0000298#else /* CFG_RAMBOOT */
299
300 /* Retrieve amount of SDRAM available */
301 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
302
303#endif /* CFG_RAMBOOT */
304
wdenke0ac62d2003-08-17 18:55:18 +0000305 return dramsize;
wdenk945af8d2003-07-16 21:53:01 +0000306}
307
wdenke35745b2004-04-18 23:32:11 +0000308#else
309#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
310#endif
311
wdenk945af8d2003-07-16 21:53:01 +0000312int checkboard (void)
313{
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100314#if defined (CONFIG_LITE5200B)
315 puts ("Board: Freescale Lite5200B\n");
316#elif defined(CONFIG_MPC5200)
wdenk945af8d2003-07-16 21:53:01 +0000317 puts ("Board: Motorola MPC5200 (IceCube)\n");
318#elif defined(CONFIG_MGT5100)
319 puts ("Board: Motorola MGT5100 (IceCube)\n");
320#endif
321 return 0;
322}
323
324void flash_preinit(void)
325{
326 /*
327 * Now, when we are in RAM, enable flash write
328 * access for detection process.
329 * Note that CS_BOOT cannot be cleared when
330 * executing in flash.
331 */
332#if defined(CONFIG_MGT5100)
333 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
334 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
335#endif
336 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
337}
wdenk96e48cf2003-08-05 18:22:44 +0000338
wdenk7152b1d2003-09-05 23:19:14 +0000339void flash_afterinit(ulong size)
340{
341 if (size == 0x800000) { /* adjust mapping */
wdenk42d1f032003-10-15 23:53:47 +0000342 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
wdenk7152b1d2003-09-05 23:19:14 +0000343 START_REG(CFG_BOOTCS_START | size);
wdenk42d1f032003-10-15 23:53:47 +0000344 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
wdenk7152b1d2003-09-05 23:19:14 +0000345 STOP_REG(CFG_BOOTCS_START | size, size);
346 }
347}
348
wdenk96e48cf2003-08-05 18:22:44 +0000349#ifdef CONFIG_PCI
350static struct pci_controller hose;
351
352extern void pci_mpc5xxx_init(struct pci_controller *);
353
354void pci_init_board(void)
355{
356 pci_mpc5xxx_init(&hose);
357}
358#endif
wdenkc3f9d492004-03-14 00:59:59 +0000359
Jon Loeliger77a31852007-07-10 10:39:10 -0500360#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
wdenkc3f9d492004-03-14 00:59:59 +0000361
wdenkc3f9d492004-03-14 00:59:59 +0000362void init_ide_reset (void)
363{
wdenk4d13cba2004-03-14 14:09:05 +0000364 debug ("init_ide_reset\n");
wdenk42dfe7a2004-03-14 22:25:36 +0000365
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100366 /* Configure PSC1_4 as GPIO output for ATA reset */
wdenkc3f9d492004-03-14 00:59:59 +0000367 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
wdenk4d13cba2004-03-14 14:09:05 +0000368 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000369 /* Deassert reset */
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100370 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000371}
372
373void ide_set_reset (int idereset)
374{
wdenk4d13cba2004-03-14 14:09:05 +0000375 debug ("ide_reset(%d)\n", idereset);
376
wdenkc3f9d492004-03-14 00:59:59 +0000377 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100378 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000379 /* Make a delay. MPC5200 spec says 25 usec min */
380 udelay(500000);
wdenkc3f9d492004-03-14 00:59:59 +0000381 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100382 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000383 }
384}
Jon Loeliger77a31852007-07-10 10:39:10 -0500385#endif
Stefan Roesee59581c2006-11-28 17:55:49 +0100386
Grant Likelycf2817a2007-09-06 09:46:23 -0600387#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Stefan Roesee59581c2006-11-28 17:55:49 +0100388void
389ft_board_setup(void *blob, bd_t *bd)
390{
391 ft_cpu_setup(blob, bd);
392}
393#endif
Ben Warren19403632008-08-31 10:03:22 -0700394
395int board_eth_init(bd_t *bis)
396{
397 return pci_eth_init(bis);
398}