blob: 90abe14f24914fe47c203f1ef4d44af0a1fb1e05 [file] [log] [blame]
Stefan Roesed96f41e2005-11-30 13:06:40 +01001/*
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +02002 * (C) Copyright 2007
3 * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
4 *
Stefan Roesed96f41e2005-11-30 13:06:40 +01005 * (C) Copyright 2005
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * Wolfgang Denk <wd@denx.de>
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2002,2003 Motorola,Inc.
11 * Xianghua Xiao <X.Xiao@motorola.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32/*
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +020033 * TQM85xx (8560/40/55/41/48) board configuration file
Stefan Roesed96f41e2005-11-30 13:06:40 +010034 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/* High Level Configuration Options */
40#define CONFIG_BOOKE 1 /* BOOKE */
41#define CONFIG_E500 1 /* BOOKE e500 family */
42#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
43
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +010044#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
Wolfgang Grandeggerad7ee5d2009-02-11 18:38:21 +010045#define CONFIG_TQM8548
46#endif
47
Stefan Roesed96f41e2005-11-30 13:06:40 +010048#define CONFIG_PCI
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +010049#ifndef CONFIG_TQM8548_AG
Wolfgang Grandeggera3182342009-02-11 18:38:20 +010050#define CONFIG_PCI1 /* PCI/PCI-X controller */
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +010051#endif
Wolfgang Grandeggera3182342009-02-11 18:38:20 +010052#ifdef CONFIG_TQM8548
53#define CONFIG_PCIE1 /* PCI Express interface */
54#endif
55
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020056#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
57#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020058#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020059
Stefan Roesed96f41e2005-11-30 13:06:40 +010060#define CONFIG_TSEC_ENET /* tsec ethernet support */
61
62#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
63
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +020064 /*
65 * Configuration for big NOR Flashes
66 *
67 * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
68 * Please be aware, that this changes the whole memory map (new CCSRBAR
69 * address, etc). You have to use an adapted Linux kernel or FDT blob
70 * if this option is set.
71 */
72#undef CONFIG_TQM_BIGFLASH
73
Stefan Roesed96f41e2005-11-30 13:06:40 +010074/*
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +020075 * NAND flash support (disabled by default)
76 *
77 * Warning: NAND support will likely increase the U-Boot image size
78 * to more than 256 KB. Please adjust TEXT_BASE if necessary.
79 */
Wolfgang Grandeggerad7ee5d2009-02-11 18:38:21 +010080#ifdef CONFIG_TQM8548_BE
81#define CONFIG_NAND
82#endif
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +020083
84/*
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +020085 * MPC8540 and MPC8548 don't have CPM module
Stefan Roesed96f41e2005-11-30 13:06:40 +010086 */
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +020087#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
Stefan Roesed96f41e2005-11-30 13:06:40 +010088#define CONFIG_CPM2 1 /* has CPM2 */
89#endif
90
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020091#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Kumar Gala4d3521c2008-01-16 09:15:29 -060092
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +010093#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
Wolfgang Grandeggerad7ee5d2009-02-11 18:38:21 +010094#define CONFIG_CAN_DRIVER /* CAN Driver support */
95#endif
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +020096
Stefan Roesed96f41e2005-11-30 13:06:40 +010097/*
98 * sysclk for MPC85xx
99 *
100 * Two valid values are:
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200101 * 33333333
102 * 66666666
Stefan Roesed96f41e2005-11-30 13:06:40 +0100103 *
104 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
105 * is likely the desired value here, so that is now the default.
106 * The board, however, can run at 66MHz. In any event, this value
107 * must match the settings of some switches. Details can be found
108 * in the README.mpc85xxads.
109 */
110
111#ifndef CONFIG_SYS_CLK_FREQ
112#define CONFIG_SYS_CLK_FREQ 33333333
113#endif
114
115/*
116 * These can be toggled for performance analysis, otherwise use default.
117 */
118#define CONFIG_L2_CACHE /* toggle L2 cache */
119#define CONFIG_BTB /* toggle branch predition */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
124#define CONFIG_SYS_MEMTEST_START 0x00000000
125#define CONFIG_SYS_MEMTEST_END 0x10000000
Stefan Roesed96f41e2005-11-30 13:06:40 +0100126
127/*
128 * Base addresses -- Note these are effective addresses where the
129 * actual resources get mapped (not physical addresses)
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200132#ifdef CONFIG_TQM_BIGFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_CCSRBAR 0xA0000000 /* relocated CCSRBAR */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200134#else /* !CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200136#endif /* CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
138#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
141#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
142#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200143
Stefan Roesed96f41e2005-11-30 13:06:40 +0100144/*
145 * DDR Setup
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
148#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +0100149#ifdef CONFIG_TQM8548_AG
150#define CONFIG_VERY_BIG_RAM
151#endif
Stefan Roesed96f41e2005-11-30 13:06:40 +0100152
Kumar Gala457caec2008-08-27 01:05:35 -0500153#define CONFIG_NUM_DDR_CONTROLLERS 1
154#define CONFIG_DIMM_SLOTS_PER_CTLR 1
155#define CONFIG_CHIP_SELECTS_PER_CTRL 2
156
Stefan Roesed96f41e2005-11-30 13:06:40 +0100157#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
158/* TQM8540 & 8560 need DLL-override */
159#define CONFIG_DDR_DLL /* DLL fix needed */
160#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200161#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100162
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200163#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
164 defined(CONFIG_TQM8548)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100165#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200166#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100167
168/*
169 * Flash on the Local Bus
170 */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200171#ifdef CONFIG_TQM_BIGFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH0 0xE0000000
173#define CONFIG_SYS_FLASH1 0xC0000000
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200174#else /* !CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH0 0xFC000000
176#define CONFIG_SYS_FLASH1 0xF8000000
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200177#endif /* CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Stefan Roesed96f41e2005-11-30 13:06:40 +0100179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
181#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100182
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200183/* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
184 *
185 * Note: According to timing specifications external addr latch delay
186 * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
187 *
188 * For other Local Bus Clocks see following table:
189 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 * Clock/MHz CONFIG_SYS_ORx_PRELIM
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200191 * 166 0x.....CA5
192 * 133 0x.....C85
193 * 100 0x.....C65
194 * 83 0x.....FA2
195 * 66 0x.....C82
196 * 50 0x.....C60
197 * 42 0x.....040
198 * 33 0x.....030
199 * 25 0x.....020
200 *
201 */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200202#ifdef CONFIG_TQM_BIGFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BR0_PRELIM 0xE0001801 /* port size 32bit */
204#define CONFIG_SYS_OR0_PRELIM 0xE0000040 /* 512MB Flash */
205#define CONFIG_SYS_BR1_PRELIM 0xC0001801 /* port size 32bit */
206#define CONFIG_SYS_OR1_PRELIM 0xE0000040 /* 512MB Flash */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200207#else /* !CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_BR0_PRELIM 0xfc001801 /* port size 32bit */
209#define CONFIG_SYS_OR0_PRELIM 0xfc000040 /* 64MB Flash */
210#define CONFIG_SYS_BR1_PRELIM 0xf8001801 /* port size 32bit */
211#define CONFIG_SYS_OR1_PRELIM 0xfc000040 /* 64MB Flash */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200212#endif /* CONFIG_TQM_BIGFLASH */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200215#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
217#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
218#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
221#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
222#undef CONFIG_SYS_FLASH_CHECKSUM
223#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
224#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100227
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200228/*
229 * Note: when changing the Local Bus clock divider you have to
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230 * change the timing values in CONFIG_SYS_ORx_PRELIM.
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200231 *
232 * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
233 * LCRR[16:17] EADC : External address delay cycles. It should be set to 2
234 * for Local Bus Clock > 83.3 MHz.
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_LBC_LCRR 0x00030008 /* LB clock ratio reg */
237#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
238#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
239#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
Stefan Roesed96f41e2005-11-30 13:06:40 +0100240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_INIT_RAM_LOCK 1
242#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200243 + 0x04010000) /* Initial RAM address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
247#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
248#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesed96f41e2005-11-30 13:06:40 +0100249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */
251#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100252
253/* Serial Port */
254#if defined(CONFIG_TQM8560)
255
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200256#define CONFIG_CONS_ON_SCC /* define if console on SCC */
257#undef CONFIG_CONS_NONE /* define if console on something else */
258#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100259
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200260#else /* !CONFIG_TQM8560 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100261
262#define CONFIG_CONS_INDEX 1
263#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_NS16550
265#define CONFIG_SYS_NS16550_SERIAL
266#define CONFIG_SYS_NS16550_REG_SIZE 1
267#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
270#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100271
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200272/* PS/2 Keyboard */
273#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
274#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
275#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200277#define CONFIG_BOARD_EARLY_INIT_R 1
278
Wolfgang Denk966083e2006-07-21 15:24:56 +0200279#endif /* CONFIG_TQM8560 */
280
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200281#define CONFIG_BAUDRATE 115200
Wolfgang Denk966083e2006-07-21 15:24:56 +0200282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_BAUDRATE_TABLE \
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200284 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Wolfgang Denk966083e2006-07-21 15:24:56 +0200285
Wolfgang Denk2751a952006-10-28 02:29:14 +0200286#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
288#ifdef CONFIG_SYS_HUSH_PARSER
289#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Stefan Roesed96f41e2005-11-30 13:06:40 +0100290#endif
291
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200292/* pass open firmware flat tree */
293#define CONFIG_OF_LIBFDT 1
294#define CONFIG_OF_BOARD_SETUP 1
295#define CONFIG_OF_STDOUT_VIA_ALIAS 1
296
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200297/* CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_CAN_BASE (CONFIG_SYS_CCSRBAR \
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200299 + 0x03000000) /* CAN base address */
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200300#ifdef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
302#define CONFIG_SYS_OR2_CAN (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
303#define CONFIG_SYS_BR2_CAN ((CONFIG_SYS_CAN_BASE & BR_BA) | \
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200304 BR_PS_8 | BR_MS_UPMC | BR_V)
305#endif /* CONFIG_CAN_DRIVER */
306
Jon Loeliger20476722006-10-20 15:50:15 -0500307/*
308 * I2C
309 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200310#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100311#define CONFIG_HARD_I2C /* I2C with hardware support */
312#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
314#define CONFIG_SYS_I2C_SLAVE 0x7F
315#define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */
316#define CONFIG_SYS_I2C_OFFSET 0x3000
Stefan Roesed96f41e2005-11-30 13:06:40 +0100317
318/* I2C RTC */
319#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100321
322/* I2C EEPROM */
323/*
324 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
327#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
328#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
329#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
330#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100331
332/* I2C SYSMON (LM75) */
333#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
334#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_DTT_MAX_TEMP 70
336#define CONFIG_SYS_DTT_LOW_TEMP -30
337#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roesed96f41e2005-11-30 13:06:40 +0100338
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200339#ifndef CONFIG_PCIE1
Stefan Roesed96f41e2005-11-30 13:06:40 +0100340/* RapidIO MMU */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200341#ifdef CONFIG_TQM_BIGFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_RIO_MEM_BASE 0xb0000000 /* base address */
343#define CONFIG_SYS_RIO_MEM_SIZE 0x10000000 /* 256M */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200344#else /* !CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
346#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200347#endif /* CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200349#endif /* CONFIG_PCIE1 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100350
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200351/* NAND FLASH */
352#ifdef CONFIG_NAND
353
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200354#define CONFIG_NAND_FSL_UPM 1
355
356#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
357
358/* address distance between chip selects */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_NAND_SELECT_DEVICE 1
360#define CONFIG_SYS_NAND_CS_DIST 0x200
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_NAND_SIZE 0x8000
Wolfgang Grandegger16f2f5a2009-02-11 18:38:24 +0100363#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200364
Wolfgang Grandegger16f2f5a2009-02-11 18:38:24 +0100365#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
366#define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200367
368/* CS3 for NAND Flash */
Wolfgang Grandegger16f2f5a2009-02-11 18:38:24 +0100369#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \
370 BR_PS_8 | BR_MS_UPMB | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200372
Wolfgang Grandegger16f2f5a2009-02-11 18:38:24 +0100373#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200374
375#endif /* CONFIG_NAND */
376
Stefan Roesed96f41e2005-11-30 13:06:40 +0100377/*
378 * General PCI
379 * Addresses are mapped 1-1.
380 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
382#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
383#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
384#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
385#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
386#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100387
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200388#ifdef CONFIG_PCIE1
389/*
390 * General PCI express
391 * Addresses are mapped 1-1.
392 */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200393#ifdef CONFIG_TQM_BIGFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000
395#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
396#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200397#else /* !CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
399#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
400#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200401#endif /* CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
403#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE
404#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200405#endif /* CONFIG_PCIE1 */
406
Stefan Roesed96f41e2005-11-30 13:06:40 +0100407#if defined(CONFIG_PCI)
408
409#define CONFIG_PCI_PNP /* do pci plug-and-play */
410
411#define CONFIG_EEPRO100
412#undef CONFIG_TULIP
413
414#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100416
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200417#endif /* CONFIG_PCI */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100418
419#define CONFIG_NET_MULTI 1
420
421#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500422#define CONFIG_TSEC1 1
423#define CONFIG_TSEC1_NAME "TSEC0"
424#define CONFIG_TSEC2 1
425#define CONFIG_TSEC2_NAME "TSEC1"
Stefan Roesed96f41e2005-11-30 13:06:40 +0100426#define TSEC1_PHY_ADDR 2
427#define TSEC2_PHY_ADDR 1
428#define TSEC1_PHYIDX 0
429#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500430#define TSEC1_FLAGS TSEC_GIGABIT
431#define TSEC2_FLAGS TSEC_GIGABIT
Stefan Roesed96f41e2005-11-30 13:06:40 +0100432#define FEC_PHY_ADDR 3
433#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500434#define FEC_FLAGS 0
Andy Fleming10327dc2007-08-16 16:35:02 -0500435#define CONFIG_HAS_ETH0
Stefan Roesed96f41e2005-11-30 13:06:40 +0100436#define CONFIG_HAS_ETH1
437#define CONFIG_HAS_ETH2
438
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200439#ifdef CONFIG_TQM8548
440/*
441 * TQM8548 has 4 ethernet ports. 4 ETSEC's.
442 *
443 * On the STK85xx Starterkit the ETSEC3/4 ports are on an
444 * additional adapter (AIO) between module and Starterkit.
445 */
446#define CONFIG_TSEC3 1
447#define CONFIG_TSEC3_NAME "TSEC2"
448#define CONFIG_TSEC4 1
449#define CONFIG_TSEC4_NAME "TSEC3"
450#define TSEC3_PHY_ADDR 4
451#define TSEC4_PHY_ADDR 5
452#define TSEC3_PHYIDX 0
453#define TSEC4_PHYIDX 0
454#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
455#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
456#define CONFIG_HAS_ETH3
457#define CONFIG_HAS_ETH4
458#endif /* CONFIG_TQM8548 */
459
Stefan Roesed96f41e2005-11-30 13:06:40 +0100460/* Options are TSEC[0-1], FEC */
461#define CONFIG_ETHPRIME "TSEC0"
462
463#if defined(CONFIG_TQM8540)
464/*
465 * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
466 * The FEC port is connected on the same signals as the FCC3 port
467 * of the TQM8560 to the baseboard (STK85xx Starterkit).
468 *
469 * On the STK85xx Starterkit the X47/X50 jumper has to be set to
470 * a - d (X50.2 - 3) to enable the FEC port.
471 */
472#define CONFIG_MPC85XX_FEC 1
473#define CONFIG_MPC85XX_FEC_NAME "FEC"
474#endif
475
476#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
477/*
478 * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
479 * can be used at once, since only one FCC port is available on the STK85xx
480 * Starterkit.
481 *
482 * To use this port you have to configure U-Boot to use the FCC port 1...2
483 * and set the X47/X50 jumper to:
484 * FCC1: a - b (X47.2 - X50.2)
485 * FCC2: a - c (X50.2 - 1)
486 */
487#define CONFIG_ETHER_ON_FCC
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200488#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100489#endif
490
491#if defined(CONFIG_TQM8560)
492/*
493 * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
494 * can be used at once, since only one FCC port is available on the STK85xx
495 * Starterkit.
496 *
497 * To use this port you have to configure U-Boot to use the FCC port 1...3
498 * and set the X47/X50 jumper to:
499 * FCC1: a - b (X47.2 - X50.2)
500 * FCC2: a - c (X50.2 - 1)
501 * FCC3: a - d (X50.2 - 3)
502 */
503#define CONFIG_ETHER_ON_FCC
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200504#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100505#endif
506
507#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
508#define CONFIG_ETHER_ON_FCC1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200510 CMXFCR_TF1CS_MSK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
512#define CONFIG_SYS_CPMFCR_RAMTYPE 0
513#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100514#endif
515
516#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
517#define CONFIG_ETHER_ON_FCC2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200519 CMXFCR_TF2CS_MSK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
521#define CONFIG_SYS_CPMFCR_RAMTYPE 0
522#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100523#endif
524
525#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
526#define CONFIG_ETHER_ON_FCC3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200528 CMXFCR_TF3CS_MSK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
530#define CONFIG_SYS_CPMFCR_RAMTYPE 0
531#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100532#endif
533
534/*
535 * Environment
536 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200537#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Grandegger46346f22008-06-05 13:12:02 +0200538
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200539#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200541#define CONFIG_ENV_SIZE 0x2000
542#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
543#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100544
545#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100547
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200548#define CONFIG_TIMESTAMP /* Print image info with ts */
Jon Loeliger2835e512007-06-13 13:22:08 -0500549
550/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500551 * BOOTP options
552 */
553#define CONFIG_BOOTP_BOOTFILESIZE
554#define CONFIG_BOOTP_BOOTPATH
555#define CONFIG_BOOTP_GATEWAY
556#define CONFIG_BOOTP_HOSTNAME
557
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200558#ifdef CONFIG_NAND
559/*
560 * Use NAND-FLash as JFFS2 device
561 */
562#define CONFIG_CMD_NAND
563#define CONFIG_CMD_JFFS2
564
565#define CONFIG_JFFS2_NAND 1
566
Stefan Roese68d7d652009-03-19 13:30:36 +0100567#ifdef CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200568#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
569#define CONFIG_FLASH_CFI_MTD
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200570#define MTDIDS_DEFAULT "nand0=TQM85xx-nand"
571#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-"
572#else
573#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
574#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
575#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100576#endif /* CONFIG_CMD_MTDPARTS */
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200577
578#endif /* CONFIG_NAND */
579
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500580/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500581 * Command line configuration.
582 */
583#include <config_cmd_default.h>
584
585#define CONFIG_CMD_PING
586#define CONFIG_CMD_I2C
587#define CONFIG_CMD_DHCP
588#define CONFIG_CMD_NFS
589#define CONFIG_CMD_SNTP
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +0100590#ifndef CONFIG_TQM8548_AG
Jon Loeliger2835e512007-06-13 13:22:08 -0500591#define CONFIG_CMD_DATE
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +0100592#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500593#define CONFIG_CMD_EEPROM
594#define CONFIG_CMD_DTT
595#define CONFIG_CMD_MII
Becky Bruce199e2622010-06-17 11:37:25 -0500596#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500597
Stefan Roesed96f41e2005-11-30 13:06:40 +0100598#if defined(CONFIG_PCI)
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200599#define CONFIG_CMD_PCI
Stefan Roesed96f41e2005-11-30 13:06:40 +0100600#endif
601
Stefan Roesed96f41e2005-11-30 13:06:40 +0100602#undef CONFIG_WATCHDOG /* watchdog disabled */
603
604/*
605 * Miscellaneous configurable options
606 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_LONGHELP /* undef to save memory */
608#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
609#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100610
Jon Loeliger2835e512007-06-13 13:22:08 -0500611#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100613#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100615#endif
616
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200617#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
618 sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buf Size */
619#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
620#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
621#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100622
623/*
624 * For booting Linux, the board info and command line data
625 * have to be in the first 8 MB of memory, since this is
626 * the maximum mapped by the Linux kernel during initialization.
627 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200628#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100629
Stefan Roesed96f41e2005-11-30 13:06:40 +0100630/*
631 * Internal Definitions
632 *
633 * Boot Flags
634 */
635#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
636#define BOOTFLAG_WARM 0x02 /* Software reboot */
637
Jon Loeliger2835e512007-06-13 13:22:08 -0500638#if defined(CONFIG_CMD_KGDB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100639#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
640#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
641#endif
642
Stefan Roesed96f41e2005-11-30 13:06:40 +0100643#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
644
645#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
646
647#define CONFIG_PREBOOT "echo;" \
Wolfgang Denkd8519dc2006-08-11 17:33:42 +0200648 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100649 "echo"
650
651#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
652
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200653
654/*
655 * Setup some board specific values for the default environment variables
656 */
657#ifdef CONFIG_CPM2
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200658#define CONFIG_ENV_CONSDEV "consdev=ttyCPM0\0"
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200659#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200660#define CONFIG_ENV_CONSDEV "consdev=ttyS0\0"
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200661#endif
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200662#define CONFIG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200663 MK_STR(CONFIG_HOSTNAME)".dtb\0"
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200664#define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
665#define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200666 "uboot_addr="MK_STR(TEXT_BASE)"\0"
667
Stefan Roesed96f41e2005-11-30 13:06:40 +0100668#define CONFIG_EXTRA_ENV_SETTINGS \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200669 CONFIG_ENV_BOOTFILE \
670 CONFIG_ENV_FDT_FILE \
Wolfgang Denk7a2063b2009-05-15 00:16:02 +0200671 CONFIG_ENV_CONSDEV \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100672 "netdev=eth0\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100673 "nfsargs=setenv bootargs root=/dev/nfs rw " \
674 "nfsroot=$serverip:$rootpath\0" \
675 "ramargs=setenv bootargs root=/dev/ram rw\0" \
676 "addip=setenv bootargs $bootargs " \
677 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
678 ":$hostname:$netdev:off panic=1\0" \
679 "addcons=setenv bootargs $bootargs " \
680 "console=$consdev,$baudrate\0" \
681 "flash_nfs=run nfsargs addip addcons;" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200682 "bootm $kernel_addr - $fdt_addr\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100683 "flash_self=run ramargs addip addcons;" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200684 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
685 "net_nfs=tftp $kernel_addr_r $bootfile;" \
686 "tftp $fdt_addr_r $fdt_file;" \
687 "run nfsargs addip addcons;" \
688 "bootm $kernel_addr_r - $fdt_addr_r\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100689 "rootpath=/opt/eldk/ppc_85xx\0" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200690 "fdt_addr_r=900000\0" \
691 "kernel_addr_r=1000000\0" \
692 "fdt_addr=ffec0000\0" \
693 "kernel_addr=ffd00000\0" \
694 "ramdisk_addr=ff800000\0" \
Wolfgang Denk7a2063b2009-05-15 00:16:02 +0200695 CONFIG_ENV_UBOOT \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200696 "load=tftp 100000 $uboot\0" \
697 "update=protect off $uboot_addr +$filesize;" \
698 "erase $uboot_addr +$filesize;" \
Wolfgang Denk7a2063b2009-05-15 00:16:02 +0200699 "cp.b 100000 $uboot_addr $filesize" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100700 "upd=run load update\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100701 ""
702#define CONFIG_BOOTCOMMAND "run flash_self"
703
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200704#endif /* __CONFIG_H */