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Pavel Machek5095ee02014-09-08 14:08:45 +02001/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
7#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
8
9#define CONFIG_SYS_GENERIC_BOARD
10
11/* Virtual target or real hardware */
12#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
13
Pavel Machek5095ee02014-09-08 14:08:45 +020014#define CONFIG_SYS_THUMB_BUILD
15
16#define CONFIG_SOCFPGA
17
18/*
19 * High level configuration
20 */
21#define CONFIG_DISPLAY_CPUINFO
22#define CONFIG_DISPLAY_BOARDINFO
23#define CONFIG_BOARD_EARLY_INIT_F
Marek Vasutfc520892014-10-18 03:52:36 +020024#define CONFIG_ARCH_EARLY_INIT_R
Pavel Machek5095ee02014-09-08 14:08:45 +020025#define CONFIG_SYS_NO_FLASH
26#define CONFIG_CLOCKS
27
28#define CONFIG_FIT
29#define CONFIG_OF_LIBFDT
30#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
31
32#define CONFIG_TIMESTAMP /* Print image info with timestamp */
33
34/*
35 * Memory configurations
36 */
37#define CONFIG_NR_DRAM_BANKS 1
38#define PHYS_SDRAM_1 0x0
Marek Vasut0223a952014-11-04 04:25:09 +010039#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
Pavel Machek5095ee02014-09-08 14:08:45 +020040#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
41#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
42
43#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
44#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
45#define CONFIG_SYS_INIT_SP_ADDR \
46 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
47 GENERATED_GBL_DATA_SIZE)
48
49#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
50#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
51#define CONFIG_SYS_TEXT_BASE 0x08000040
52#else
53#define CONFIG_SYS_TEXT_BASE 0x01000040
54#endif
55
56/*
57 * U-Boot general configurations
58 */
59#define CONFIG_SYS_LONGHELP
60#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
61#define CONFIG_SYS_PBSIZE \
62 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
63 /* Print buffer size */
64#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
65#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
66 /* Boot argument buffer size */
67#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
68#define CONFIG_AUTO_COMPLETE /* Command auto complete */
69#define CONFIG_CMDLINE_EDITING /* Command history etc */
70#define CONFIG_SYS_HUSH_PARSER
71
72/*
73 * Cache
74 */
75#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
76#define CONFIG_SYS_CACHELINE_SIZE 32
77#define CONFIG_SYS_L2_PL310
78#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
79
80/*
Marek Vasut8a78ca92014-09-27 01:18:29 +020081 * EPCS/EPCQx1 Serial Flash Controller
82 */
83#ifdef CONFIG_ALTERA_SPI
84#define CONFIG_CMD_SPI
85#define CONFIG_CMD_SF
86#define CONFIG_SF_DEFAULT_SPEED 30000000
87#define CONFIG_SPI_FLASH
88#define CONFIG_SPI_FLASH_STMICRO
89#define CONFIG_SPI_FLASH_BAR
90/*
91 * The base address is configurable in QSys, each board must specify the
92 * base address based on it's particular FPGA configuration. Please note
93 * that the address here is incremented by 0x400 from the Base address
94 * selected in QSys, since the SPI registers are at offset +0x400.
95 * #define CONFIG_SYS_SPI_BASE 0xff240400
96 */
97#endif
98
99/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200100 * Ethernet on SoC (EMAC)
101 */
102#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
103#define CONFIG_DESIGNWARE_ETH
104#define CONFIG_NET_MULTI
105#define CONFIG_DW_ALTDESCRIPTOR
106#define CONFIG_MII
107#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
108#define CONFIG_PHYLIB
109#define CONFIG_PHY_GIGE
110#endif
111
112/*
113 * FPGA Driver
114 */
115#ifdef CONFIG_CMD_FPGA
116#define CONFIG_FPGA
117#define CONFIG_FPGA_ALTERA
118#define CONFIG_FPGA_SOCFPGA
119#define CONFIG_FPGA_COUNT 1
120#endif
121
122/*
123 * L4 OSC1 Timer 0
124 */
125/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
126#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
127#define CONFIG_SYS_TIMER_COUNTS_DOWN
128#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
129#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
130#define CONFIG_SYS_TIMER_RATE 2400000
131#else
132#define CONFIG_SYS_TIMER_RATE 25000000
133#endif
134
135/*
136 * L4 Watchdog
137 */
138#ifdef CONFIG_HW_WATCHDOG
139#define CONFIG_DESIGNWARE_WATCHDOG
140#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
141#define CONFIG_DW_WDT_CLOCK_KHZ 25000
142#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000
143#endif
144
145/*
146 * MMC Driver
147 */
148#ifdef CONFIG_CMD_MMC
149#define CONFIG_MMC
150#define CONFIG_BOUNCE_BUFFER
151#define CONFIG_GENERIC_MMC
152#define CONFIG_DWMMC
153#define CONFIG_SOCFPGA_DWMMC
154#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
155#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
156#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
157/* FIXME */
158/* using smaller max blk cnt to avoid flooding the limited stack we have */
159#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
160#endif
161
Stefan Roeseebcaf962014-10-30 09:33:13 +0100162 /*
163 * I2C support
164 */
165#define CONFIG_SYS_I2C
166#define CONFIG_SYS_I2C_DW
167#define CONFIG_SYS_I2C_BUS_MAX 4
168#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
169#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
170#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
171#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
172/* Using standard mode which the speed up to 100Kb/s */
173#define CONFIG_SYS_I2C_SPEED 100000
174#define CONFIG_SYS_I2C_SPEED1 100000
175#define CONFIG_SYS_I2C_SPEED2 100000
176#define CONFIG_SYS_I2C_SPEED3 100000
177/* Address of device when used as slave */
178#define CONFIG_SYS_I2C_SLAVE 0x02
179#define CONFIG_SYS_I2C_SLAVE1 0x02
180#define CONFIG_SYS_I2C_SLAVE2 0x02
181#define CONFIG_SYS_I2C_SLAVE3 0x02
182#ifndef __ASSEMBLY__
183/* Clock supplied to I2C controller in unit of MHz */
184unsigned int cm_get_l4_sp_clk_hz(void);
185#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
186#endif
187#define CONFIG_CMD_I2C
188
Pavel Machek5095ee02014-09-08 14:08:45 +0200189/*
190 * Serial Driver
191 */
192#define CONFIG_SYS_NS16550
193#define CONFIG_SYS_NS16550_SERIAL
194#define CONFIG_SYS_NS16550_REG_SIZE -4
195#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
196#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
197#define CONFIG_SYS_NS16550_CLK 1000000
198#else
199#define CONFIG_SYS_NS16550_CLK 100000000
200#endif
201#define CONFIG_CONS_INDEX 1
202#define CONFIG_BAUDRATE 115200
203
204/*
Marek Vasut20cadbb2014-10-24 23:34:25 +0200205 * USB
206 */
207#ifdef CONFIG_CMD_USB
208#define CONFIG_USB_DWC2
209#define CONFIG_USB_STORAGE
210/*
211 * NOTE: User must define either of the following to select which
212 * of the two USB controllers available on SoCFPGA to use.
213 * The DWC2 driver doesn't support multiple USB controllers.
214 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
215 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
216 */
217#endif
218
219/*
Marek Vasut0223a952014-11-04 04:25:09 +0100220 * USB Gadget (DFU, UMS)
221 */
222#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
223#define CONFIG_USB_GADGET
224#define CONFIG_USB_GADGET_S3C_UDC_OTG
225#define CONFIG_USB_GADGET_DUALSPEED
226#define CONFIG_USB_GADGET_VBUS_DRAW 2
227
228/* USB Composite download gadget - g_dnl */
229#define CONFIG_USBDOWNLOAD_GADGET
230#define CONFIG_USB_GADGET_MASS_STORAGE
231
232#define CONFIG_DFU_FUNCTION
233#define CONFIG_DFU_MMC
234#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
235#define DFU_DEFAULT_POLL_TIMEOUT 300
236
237/* USB IDs */
238#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
239#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
240#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
241#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
242#ifndef CONFIG_G_DNL_MANUFACTURER
243#define CONFIG_G_DNL_MANUFACTURER "Altera"
244#endif
245#endif
246
247/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200248 * U-Boot environment
249 */
250#define CONFIG_SYS_CONSOLE_IS_IN_ENV
251#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
252#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
253#define CONFIG_ENV_IS_NOWHERE
254#define CONFIG_ENV_SIZE 4096
255
256/*
257 * SPL
Marek Vasut34584d12014-10-16 12:25:40 +0200258 *
259 * SRAM Memory layout:
260 *
261 * 0xFFFF_0000 ...... Start of SRAM
262 * 0xFFFF_xxxx ...... Top of stack (grows down)
263 * 0xFFFF_yyyy ...... Malloc area
264 * 0xFFFF_zzzz ...... Global Data
265 * 0xFFFF_FF00 ...... End of SRAM
Pavel Machek5095ee02014-09-08 14:08:45 +0200266 */
267#define CONFIG_SPL_FRAMEWORK
268#define CONFIG_SPL_BOARD_INIT
269#define CONFIG_SPL_RAM_DEVICE
Marek Vasut34584d12014-10-16 12:25:40 +0200270#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
271#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
272#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
Pavel Machek5095ee02014-09-08 14:08:45 +0200273
274#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
275#define CONFIG_CRC32_VERIFY
276
277/* Linker script for SPL */
278#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
279
280#define CONFIG_SPL_LIBCOMMON_SUPPORT
281#define CONFIG_SPL_LIBGENERIC_SUPPORT
282#define CONFIG_SPL_WATCHDOG_SUPPORT
283#define CONFIG_SPL_SERIAL_SUPPORT
284
285#ifdef CONFIG_SPL_BUILD
286#undef CONFIG_PARTITIONS
287#endif
288
289#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */