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wdenk5c952cf2004-10-10 21:27:30 +00001/*
2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __ASM_NIOS2_CACHE_H_
25#define __ASM_NIOS2_CACHE_H_
26
27extern void flush_dcache (unsigned long start, unsigned long size);
28extern void flush_icache (unsigned long start, unsigned long size);
29
Anton Staaf6fa60352011-10-17 16:46:05 -070030/*
31 * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
32 * bytes. If the board configuration has not specified one we default to the
33 * largest of these values for alignment of DMA buffers.
34 */
35#ifdef CONFIG_SYS_CACHELINE_SIZE
36#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
37#else
38#define ARCH_DMA_MINALIGN 32
39#endif
40
wdenk5c952cf2004-10-10 21:27:30 +000041#endif /* __ASM_NIOS2_CACHE_H_ */