blob: f5c52c95c9399495899433869df0854165382e22 [file] [log] [blame]
wdenkdb01a2e2004-04-15 23:14:49 +00001/*
2 * Copyright (c) 2004 Picture Elements, Inc.
3 * Stephen Williams (steve@icarus.com)
4 *
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 */
20
21# include <common.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020022# include <asm/ppc4xx.h>
wdenkdb01a2e2004-04-15 23:14:49 +000023# include <asm/processor.h>
24# include <asm/io.h>
25# include "jse_priv.h"
26
27/*
28 * This function is run very early, out of flash, and before devices are
Stefan Roesea47a12b2010-04-15 16:07:28 +020029 * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
wdenkdb01a2e2004-04-15 23:14:49 +000030 * of being in the init_sequence array.
31 *
32 * The SDRAM has been initialized already -- start.S:start called
33 * init.S:init_sdram early on -- but it is not yet being used for
34 * anything, not even stack. So be careful.
35 */
36int board_early_init_f (void)
37{
38 /*-------------------------------------------------------------------------+
39 | Interrupt controller setup for the JSE board.
40 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
41 | IRQ 16 405GP internally generated; active low; level sensitive
42 | IRQ 17-24 RESERVED/UNUSED
43 | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
44 | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
45 | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
46 | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
47 | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
48 | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
49 | IRQ 31 (EXT IRQ 6) (unused)
50 +-------------------------------------------------------------------------*/
Stefan Roese952e7762009-09-24 09:55:50 +020051 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
52 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
53 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
54 mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */
55 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
56 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
wdenkdb01a2e2004-04-15 23:14:49 +000057
58 /* Configure the interface to the SystemACE MCU port.
59 The SystemACE is fast, but there is no reason to have
60 excessivly tight timings. So the settings are slightly
61 generous. */
62
63 /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
64 WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020065 mtdcr (EBC0_CFGADDR, PB1AP);
66 mtdcr (EBC0_CFGDATA, 0x01011000);
wdenkdb01a2e2004-04-15 23:14:49 +000067
68 /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
Stefan Roesed1c3b272009-09-09 16:25:29 +020069 mtdcr (EBC0_CFGADDR, PB1CR);
70 mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
wdenkdb01a2e2004-04-15 23:14:49 +000071
72 /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
73 /* CPC0_CR1 |= PCIPW */
74 mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
75
76 return 0;
77}
78
79#ifdef CONFIG_BOARD_PRE_INIT
80int board_pre_init (void)
81{
82 return board_early_init_f ();
83}
84
85#endif
86
87/*
Stefan Roesea47a12b2010-04-15 16:07:28 +020088 * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is
wdenkdb01a2e2004-04-15 23:14:49 +000089 * also in the init_sequence array) but later. Many more things are
90 * configured, but we are still running from flash.
91 */
92int checkboard (void)
93{
94 unsigned vers, status;
95
96 /* check that the SystemACE chip is alive. */
97 printf ("ACE: ");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098 vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16);
wdenkdb01a2e2004-04-15 23:14:49 +000099 printf ("SystemACE %u.%u (build %u)",
100 (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
wdenkdb01a2e2004-04-15 23:14:49 +0000103#ifdef DEBUG
104 printf (" STATUS=0x%08x", status);
105#endif
106 /* If the flash card is present and there is an initial error,
107 then force a restart of the program. */
108 if (status & 0x00000010) {
109 printf (" CFDETECT");
110
111 if (status & 0x04) {
112 /* CONTROLREG = CFGPROG */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
wdenkdb01a2e2004-04-15 23:14:49 +0000114 udelay (500);
115 /* CONTROLREG = CFGRESET */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116 writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
wdenkdb01a2e2004-04-15 23:14:49 +0000117 udelay (500);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
wdenkdb01a2e2004-04-15 23:14:49 +0000119 /* CONTROLREG = CFGSTART */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120 writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
wdenkdb01a2e2004-04-15 23:14:49 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122 status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
wdenkdb01a2e2004-04-15 23:14:49 +0000123 }
124 }
125
126 /* Wait for the SystemACE to program its chain of devices. */
127 while ((status & 0x84) == 0x00) {
128 udelay (500);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
wdenkdb01a2e2004-04-15 23:14:49 +0000130 }
131
132 if (status & 0x04)
133 printf (" CFG-ERROR");
134 if (status & 0x80)
135 printf (" CFGDONE");
136
137 printf ("\n");
138
139 /* Force /RTS to active. The board it not wired quite
140 correctly to use cts/rtc flow control, so just force the
141 /RST active and forget about it. */
142 writeb (readb (0xef600404) | 0x03, 0xef600404);
143
144 printf ("JSE: ready\n");
145
146 return 0;
147}
148
149/* **** No more functions called by board_init_f. **** */
150
151/*
Stefan Roesea47a12b2010-04-15 16:07:28 +0200152 * This function is called by arch/powerpc/lib/board.c:board_init_r. At this
wdenkdb01a2e2004-04-15 23:14:49 +0000153 * point, basic setup is done, U-Boot has been moved into SDRAM and
154 * PCI has been set up. From here we done late setup.
155 */
156int misc_init_r (void)
157{
158 host_bridge_init ();
159 return 0;
160}