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Marek Vasut0ec005f2012-07-03 03:02:20 +00001/*
2 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3 * on behalf of DENX Software Engineering GmbH
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301 USA
22 */
23
24#include <common.h>
25#include <miiphy.h>
26#include <asm/arch/cpu.h>
27#include <asm/arch/kirkwood.h>
28#include <asm/arch/mpp.h>
29#include <asm/io.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33#define TK71_OE_LOW (~0)
34#define TK71_OE_HIGH (~0)
35#define TK71_OE_VAL_LOW (0)
36#define TK71_OE_VAL_HIGH (0)
37
38int board_early_init_f(void)
39{
40 /*
41 * default gpio configuration
42 * There are maximum 64 gpios controlled through 2 sets of registers
43 * the below configuration configures mainly initial LED status
44 */
45 kw_config_gpio(TK71_OE_VAL_LOW,
46 TK71_OE_VAL_HIGH,
47 TK71_OE_LOW, TK71_OE_HIGH);
48
49 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD9d86f0c2012-11-26 11:27:36 +000050 static const u32 kwmpp_config[] = {
Marek Vasut0ec005f2012-07-03 03:02:20 +000051 MPP0_NF_IO2,
52 MPP1_NF_IO3,
53 MPP2_NF_IO4,
54 MPP3_NF_IO5,
55 MPP4_NF_IO6,
56 MPP5_NF_IO7,
57 MPP6_SYSRST_OUTn,
58 MPP7_GPO,
59 MPP8_TW_SDA,
60 MPP9_TW_SCK,
61 MPP10_UART0_TXD,
62 MPP11_UART0_RXD,
63 MPP12_SD_CLK,
64 MPP13_SD_CMD,
65 MPP14_SD_D0,
66 MPP15_SD_D1,
67 MPP16_SD_D2,
68 MPP17_SD_D3,
69 MPP18_NF_IO0,
70 MPP19_NF_IO1,
71 MPP20_GE1_0,
72 MPP21_GE1_1,
73 MPP22_GE1_2,
74 MPP23_GE1_3,
75 MPP24_GE1_4,
76 MPP25_GE1_5,
77 MPP26_GE1_6,
78 MPP27_GE1_7,
79 MPP28_GPIO,
80 MPP29_GPIO,
81 MPP30_GE1_10,
82 MPP31_GE1_11,
83 MPP32_GE1_12,
84 MPP33_GE1_13,
85 MPP34_GPIO,
86 MPP35_GPIO,
87 MPP36_GPIO,
88 MPP37_GPIO,
89 MPP38_GPIO,
90 MPP39_GPIO,
91 MPP40_GPIO,
92 MPP41_GPIO,
93 MPP42_GPIO,
94 MPP43_GPIO,
95 MPP44_GPIO,
96 MPP45_GPIO,
97 MPP46_GPIO,
98 MPP47_GPIO,
99 MPP48_GPIO,
100 MPP49_GPIO,
101 0
102 };
103 kirkwood_mpp_conf(kwmpp_config, NULL);
104
105 return 0;
106}
107
108int board_init(void)
109{
110 /*
111 * arch number of board
112 */
113 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
114
115 /* adress of boot parameters */
116 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
117
118 return 0;
119}
120
121#ifdef CONFIG_CMD_NET
122
123#define MV88E1116_MAC_CTRL2_REG 21
124#define MV88E1116_PGADR_REG 22
125#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
126#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
127
128static void mv_phy_88e1118_init(char *name)
129{
130 u16 reg;
131 u16 devadr;
132
133 if (miiphy_set_current_dev(name))
134 return;
135
136 /* command to read PHY dev address */
137 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
138 printf("Err..%s could not read PHY dev address\n",
139 __func__);
140 return;
141 }
142
143 /*
144 * Enable RGMII delay on Tx and Rx for CPU port
145 * Ref: sec 4.7.2 of chip datasheet
146 */
147 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
148 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
149 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
150 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
151 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
152
153 /* reset the phy */
154 miiphy_reset(name, devadr);
155
156 printf("88E1118 Initialized on %s\n", name);
157}
158
159/* Configure and enable Switch and PHY */
160void reset_phy(void)
161{
162 /* configure and initialize PHY */
163 mv_phy_88e1118_init("egiga0");
164
165}
166#endif