blob: 98f2c52ee3313ce5b0f4c2e52b349a9e1bf9d22f [file] [log] [blame]
Stefano Babic9f472e62012-02-22 00:24:39 +00001/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc.
21 *
22 */
23
24#include <libata.h>
25#include <ahci.h>
26#include <fis.h>
Pavel Herrmanne46a4352012-09-27 23:18:04 +000027#include <sata.h>
Stefano Babic9f472e62012-02-22 00:24:39 +000028
29#include <common.h>
30#include <malloc.h>
31#include <linux/ctype.h>
32#include <asm/errno.h>
33#include <asm/io.h>
34#include <linux/bitops.h>
35#include <asm/arch/clock.h>
36#include "dwc_ahsata.h"
37
38struct sata_port_regs {
39 u32 clb;
40 u32 clbu;
41 u32 fb;
42 u32 fbu;
43 u32 is;
44 u32 ie;
45 u32 cmd;
46 u32 res1[1];
47 u32 tfd;
48 u32 sig;
49 u32 ssts;
50 u32 sctl;
51 u32 serr;
52 u32 sact;
53 u32 ci;
54 u32 sntf;
55 u32 res2[1];
56 u32 dmacr;
57 u32 res3[1];
58 u32 phycr;
59 u32 physr;
60};
61
62struct sata_host_regs {
63 u32 cap;
64 u32 ghc;
65 u32 is;
66 u32 pi;
67 u32 vs;
68 u32 ccc_ctl;
69 u32 ccc_ports;
70 u32 res1[2];
71 u32 cap2;
72 u32 res2[30];
73 u32 bistafr;
74 u32 bistcr;
75 u32 bistfctr;
76 u32 bistsr;
77 u32 bistdecr;
78 u32 res3[2];
79 u32 oobr;
80 u32 res4[8];
81 u32 timer1ms;
82 u32 res5[1];
83 u32 gparam1r;
84 u32 gparam2r;
85 u32 pparamr;
86 u32 testr;
87 u32 versionr;
88 u32 idr;
89};
90
91#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
92#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
93
94#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
95
96static int is_ready;
97
98static inline u32 ahci_port_base(u32 base, u32 port)
99{
100 return base + 0x100 + (port * 0x80);
101}
102
103static int waiting_for_cmd_completed(u8 *offset,
104 int timeout_msec,
105 u32 sign)
106{
107 int i;
108 u32 status;
109
110 for (i = 0;
111 ((status = readl(offset)) & sign) && i < timeout_msec;
112 ++i)
113 mdelay(1);
114
115 return (i < timeout_msec) ? 0 : -1;
116}
117
118static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
119 int clk)
120{
121 struct sata_host_regs *host_mmio =
122 (struct sata_host_regs *)probe_ent->mmio_base;
123
124 writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
125 writel(0x02060b14, &(host_mmio->oobr));
126
127 return 0;
128}
129
130static int ahci_host_init(struct ahci_probe_ent *probe_ent)
131{
132 u32 tmp, cap_save, num_ports;
133 int i, j, timeout = 1000;
134 struct sata_port_regs *port_mmio = NULL;
135 struct sata_host_regs *host_mmio =
136 (struct sata_host_regs *)probe_ent->mmio_base;
137 int clk = mxc_get_clock(MXC_SATA_CLK);
138
139 cap_save = readl(&(host_mmio->cap));
140 cap_save |= SATA_HOST_CAP_SSS;
141
142 /* global controller reset */
143 tmp = readl(&(host_mmio->ghc));
144 if ((tmp & SATA_HOST_GHC_HR) == 0)
145 writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
146
147 while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
148 && --timeout)
149 ;
150
151 if (timeout <= 0) {
152 debug("controller reset failed (0x%x)\n", tmp);
153 return -1;
154 }
155
156 /* Set timer 1ms */
157 writel(clk / 1000, &(host_mmio->timer1ms));
158
159 ahci_setup_oobr(probe_ent, 0);
160
161 writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
162 writel(cap_save, &(host_mmio->cap));
163 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
164 writel_with_flush((1 << num_ports) - 1,
165 &(host_mmio->pi));
166
167 /*
168 * Determine which Ports are implemented by the DWC_ahsata,
169 * by reading the PI register. This bit map value aids the
170 * software to determine how many Ports are available and
171 * which Port registers need to be initialized.
172 */
173 probe_ent->cap = readl(&(host_mmio->cap));
174 probe_ent->port_map = readl(&(host_mmio->pi));
175
176 /* Determine how many command slots the HBA supports */
177 probe_ent->n_ports =
178 (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1;
179
180 debug("cap 0x%x port_map 0x%x n_ports %d\n",
181 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
182
183 for (i = 0; i < probe_ent->n_ports; i++) {
184 probe_ent->port[i].port_mmio =
185 ahci_port_base((u32)host_mmio, i);
186 port_mmio =
187 (struct sata_port_regs *)probe_ent->port[i].port_mmio;
188
189 /* Ensure that the DWC_ahsata is in idle state */
190 tmp = readl(&(port_mmio->cmd));
191
192 /*
193 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
194 * are all cleared, the Port is in an idle state.
195 */
196 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
197 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
198
199 /*
200 * System software places a Port into the idle state by
201 * clearing P#CMD.ST and waiting for P#CMD.CR to return
202 * 0 when read.
203 */
204 tmp &= ~SATA_PORT_CMD_ST;
205 writel_with_flush(tmp, &(port_mmio->cmd));
206
207 /*
208 * spec says 500 msecs for each bit, so
209 * this is slightly incorrect.
210 */
211 mdelay(500);
212
213 timeout = 1000;
214 while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
215 && --timeout)
216 ;
217
218 if (timeout <= 0) {
219 debug("port reset failed (0x%x)\n", tmp);
220 return -1;
221 }
222 }
223
224 /* Spin-up device */
225 tmp = readl(&(port_mmio->cmd));
226 writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
227
228 /* Wait for spin-up to finish */
229 timeout = 1000;
230 while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
231 && --timeout)
232 ;
233 if (timeout <= 0) {
234 debug("Spin-Up can't finish!\n");
235 return -1;
236 }
237
238 for (j = 0; j < 100; ++j) {
239 mdelay(10);
240 tmp = readl(&(port_mmio->ssts));
241 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
242 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
243 break;
244 }
245
246 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
247 timeout = 1000;
248 while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
249 && --timeout)
250 ;
251 if (timeout <= 0) {
252 debug("Can't find DIAG_X set!\n");
253 return -1;
254 }
255
256 /*
257 * For each implemented Port, clear the P#SERR
258 * register, by writing ones to each implemented\
259 * bit location.
260 */
261 tmp = readl(&(port_mmio->serr));
262 debug("P#SERR 0x%x\n",
263 tmp);
264 writel(tmp, &(port_mmio->serr));
265
266 /* Ack any pending irq events for this port */
267 tmp = readl(&(host_mmio->is));
268 debug("IS 0x%x\n", tmp);
269 if (tmp)
270 writel(tmp, &(host_mmio->is));
271
272 writel(1 << i, &(host_mmio->is));
273
274 /* set irq mask (enables interrupts) */
275 writel(DEF_PORT_IRQ, &(port_mmio->ie));
276
277 /* register linkup ports */
278 tmp = readl(&(port_mmio->ssts));
279 debug("Port %d status: 0x%x\n", i, tmp);
280 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
281 probe_ent->link_port_map |= (0x01 << i);
282 }
283
284 tmp = readl(&(host_mmio->ghc));
285 debug("GHC 0x%x\n", tmp);
286 writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
287 tmp = readl(&(host_mmio->ghc));
288 debug("GHC 0x%x\n", tmp);
289
290 return 0;
291}
292
293static void ahci_print_info(struct ahci_probe_ent *probe_ent)
294{
295 struct sata_host_regs *host_mmio =
296 (struct sata_host_regs *)probe_ent->mmio_base;
297 u32 vers, cap, impl, speed;
298 const char *speed_s;
299 const char *scc_s;
300
301 vers = readl(&(host_mmio->vs));
302 cap = probe_ent->cap;
303 impl = probe_ent->port_map;
304
305 speed = (cap & SATA_HOST_CAP_ISS_MASK)
306 >> SATA_HOST_CAP_ISS_OFFSET;
307 if (speed == 1)
308 speed_s = "1.5";
309 else if (speed == 2)
310 speed_s = "3";
311 else
312 speed_s = "?";
313
314 scc_s = "SATA";
315
316 printf("AHCI %02x%02x.%02x%02x "
317 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
318 (vers >> 24) & 0xff,
319 (vers >> 16) & 0xff,
320 (vers >> 8) & 0xff,
321 vers & 0xff,
322 ((cap >> 8) & 0x1f) + 1,
323 (cap & 0x1f) + 1,
324 speed_s,
325 impl,
326 scc_s);
327
328 printf("flags: "
329 "%s%s%s%s%s%s"
330 "%s%s%s%s%s%s%s\n",
331 cap & (1 << 31) ? "64bit " : "",
332 cap & (1 << 30) ? "ncq " : "",
333 cap & (1 << 28) ? "ilck " : "",
334 cap & (1 << 27) ? "stag " : "",
335 cap & (1 << 26) ? "pm " : "",
336 cap & (1 << 25) ? "led " : "",
337 cap & (1 << 24) ? "clo " : "",
338 cap & (1 << 19) ? "nz " : "",
339 cap & (1 << 18) ? "only " : "",
340 cap & (1 << 17) ? "pmp " : "",
341 cap & (1 << 15) ? "pio " : "",
342 cap & (1 << 14) ? "slum " : "",
343 cap & (1 << 13) ? "part " : "");
344}
345
346static int ahci_init_one(int pdev)
347{
348 int rc;
349 struct ahci_probe_ent *probe_ent = NULL;
350
351 probe_ent = malloc(sizeof(struct ahci_probe_ent));
352 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
353 probe_ent->dev = pdev;
354
355 probe_ent->host_flags = ATA_FLAG_SATA
356 | ATA_FLAG_NO_LEGACY
357 | ATA_FLAG_MMIO
358 | ATA_FLAG_PIO_DMA
359 | ATA_FLAG_NO_ATAPI;
360
361 probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
362
363 /* initialize adapter */
364 rc = ahci_host_init(probe_ent);
365 if (rc)
366 goto err_out;
367
368 ahci_print_info(probe_ent);
369
370 /* Save the private struct to block device struct */
371 sata_dev_desc[pdev].priv = (void *)probe_ent;
372
373 return 0;
374
375err_out:
376 return rc;
377}
378
379static int ahci_fill_sg(struct ahci_probe_ent *probe_ent,
380 u8 port, unsigned char *buf, int buf_len)
381{
382 struct ahci_ioports *pp = &(probe_ent->port[port]);
383 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
384 u32 sg_count, max_bytes;
385 int i;
386
387 max_bytes = MAX_DATA_BYTES_PER_SG;
388 sg_count = ((buf_len - 1) / max_bytes) + 1;
389 if (sg_count > AHCI_MAX_SG) {
390 printf("Error:Too much sg!\n");
391 return -1;
392 }
393
394 for (i = 0; i < sg_count; i++) {
395 ahci_sg->addr =
396 cpu_to_le32((u32)buf + i * max_bytes);
397 ahci_sg->addr_hi = 0;
398 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
399 (buf_len < max_bytes
400 ? (buf_len - 1)
401 : (max_bytes - 1)));
402 ahci_sg++;
403 buf_len -= max_bytes;
404 }
405
406 return sg_count;
407}
408
409static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
410{
411 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
412 AHCI_CMD_SLOT_SZ * cmd_slot);
413
414 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
415 cmd_hdr->opts = cpu_to_le32(opts);
416 cmd_hdr->status = 0;
417 cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
418 cmd_hdr->tbl_addr_hi = 0;
419}
420
421#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
422
423static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
424 u8 port, struct sata_fis_h2d *cfis,
425 u8 *buf, u32 buf_len, s32 is_write)
426{
427 struct ahci_ioports *pp = &(probe_ent->port[port]);
428 struct sata_port_regs *port_mmio =
429 (struct sata_port_regs *)pp->port_mmio;
430 u32 opts;
431 int sg_count = 0, cmd_slot = 0;
432
433 cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
434 if (32 == cmd_slot) {
435 printf("Can't find empty command slot!\n");
436 return 0;
437 }
438
439 /* Check xfer length */
440 if (buf_len > MAX_BYTES_PER_TRANS) {
441 printf("Max transfer length is %dB\n\r",
442 MAX_BYTES_PER_TRANS);
443 return 0;
444 }
445
446 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
447 if (buf && buf_len)
448 sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
449 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700450 if (is_write) {
Stefano Babic9f472e62012-02-22 00:24:39 +0000451 opts |= 0x40;
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700452 flush_cache((ulong)buf, buf_len);
453 }
Stefano Babic9f472e62012-02-22 00:24:39 +0000454 ahci_fill_cmd_slot(pp, cmd_slot, opts);
455
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700456 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
Stefano Babic9f472e62012-02-22 00:24:39 +0000457 writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
458
459 if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
460 10000, 0x1 << cmd_slot)) {
461 printf("timeout exit!\n");
462 return -1;
463 }
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700464 invalidate_dcache_range((int)(pp->cmd_slot),
465 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
Stefano Babic9f472e62012-02-22 00:24:39 +0000466 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
467 pp->cmd_slot->status);
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700468 if (!is_write)
469 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
Stefano Babic9f472e62012-02-22 00:24:39 +0000470
471 return buf_len;
472}
473
474static void ahci_set_feature(u8 dev, u8 port)
475{
476 struct ahci_probe_ent *probe_ent =
477 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700478 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
479 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic9f472e62012-02-22 00:24:39 +0000480
481 memset(cfis, 0, sizeof(struct sata_fis_h2d));
482 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
483 cfis->pm_port_c = 1 << 7;
484 cfis->command = ATA_CMD_SET_FEATURES;
485 cfis->features = SETFEATURES_XFER;
486 cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e;
487
488 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD);
489}
490
491static int ahci_port_start(struct ahci_probe_ent *probe_ent,
492 u8 port)
493{
494 struct ahci_ioports *pp = &(probe_ent->port[port]);
495 struct sata_port_regs *port_mmio =
496 (struct sata_port_regs *)pp->port_mmio;
497 u32 port_status;
498 u32 mem;
499 int timeout = 10000000;
500
501 debug("Enter start port: %d\n", port);
502 port_status = readl(&(port_mmio->ssts));
503 debug("Port %d status: %x\n", port, port_status);
504 if ((port_status & 0xf) != 0x03) {
505 printf("No Link on this port!\n");
506 return -1;
507 }
508
509 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
510 if (!mem) {
511 free(pp);
512 printf("No mem for table!\n");
513 return -ENOMEM;
514 }
515
516 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
517 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
518
519 /*
520 * First item in chunk of DMA memory: 32-slot command table,
521 * 32 bytes each in size
522 */
523 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
524 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
525 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
526
527 /*
528 * Second item: Received-FIS area, 256-Byte aligned
529 */
530 pp->rx_fis = mem;
531 mem += AHCI_RX_FIS_SZ;
532
533 /*
534 * Third item: data area for storing a single command
535 * and its scatter-gather table
536 */
537 pp->cmd_tbl = mem;
538 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
539
540 mem += AHCI_CMD_TBL_HDR;
541
542 writel_with_flush(0x00004444, &(port_mmio->dmacr));
543 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
544 writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
545 writel_with_flush(pp->rx_fis, &(port_mmio->fb));
546
547 /* Enable FRE */
548 writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
549 &(port_mmio->cmd));
550
551 /* Wait device ready */
552 while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
553 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
554 && --timeout)
555 ;
556 if (timeout <= 0) {
557 debug("Device not ready for BSY, DRQ and"
558 "ERR in TFD!\n");
559 return -1;
560 }
561
562 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
563 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
564 PORT_CMD_START, &(port_mmio->cmd));
565
566 debug("Exit start port %d\n", port);
567
568 return 0;
569}
570
571int init_sata(int dev)
572{
573 int i;
574 u32 linkmap;
575 struct ahci_probe_ent *probe_ent = NULL;
576
577 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
578 printf("The sata index %d is out of ranges\n\r", dev);
579 return -1;
580 }
581
582 ahci_init_one(dev);
583
584 probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
585 linkmap = probe_ent->link_port_map;
586
587 if (0 == linkmap) {
588 printf("No port device detected!\n");
589 return 1;
590 }
591
592 for (i = 0; i < probe_ent->n_ports; i++) {
593 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
594 if (ahci_port_start(probe_ent, (u8)i)) {
595 printf("Can not start port %d\n", i);
596 return 1;
597 }
598 probe_ent->hard_port_no = i;
599 break;
600 }
601 }
602
603 return 0;
604}
605
606static void dwc_ahsata_print_info(int dev)
607{
608 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
609
610 printf("SATA Device Info:\n\r");
611#ifdef CONFIG_SYS_64BIT_LBA
612 printf("S/N: %s\n\rProduct model number: %s\n\r"
613 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
614 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
615#else
616 printf("S/N: %s\n\rProduct model number: %s\n\r"
617 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
618 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
619#endif
620}
621
622static void dwc_ahsata_identify(int dev, u16 *id)
623{
624 struct ahci_probe_ent *probe_ent =
625 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700626 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
627 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic9f472e62012-02-22 00:24:39 +0000628 u8 port = probe_ent->hard_port_no;
629
630 memset(cfis, 0, sizeof(struct sata_fis_h2d));
631
632 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
633 cfis->pm_port_c = 0x80; /* is command */
634 cfis->command = ATA_CMD_ID_ATA;
635
636 ahci_exec_ata_cmd(probe_ent, port, cfis,
637 (u8 *)id, ATA_ID_WORDS * 2, READ_CMD);
638 ata_swap_buf_le16(id, ATA_ID_WORDS);
639}
640
641static void dwc_ahsata_xfer_mode(int dev, u16 *id)
642{
643 struct ahci_probe_ent *probe_ent =
644 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
645
646 probe_ent->pio_mask = id[ATA_ID_PIO_MODES];
647 probe_ent->udma_mask = id[ATA_ID_UDMA_MODES];
648 debug("pio %04x, udma %04x\n\r",
649 probe_ent->pio_mask, probe_ent->udma_mask);
650}
651
652static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
653 u8 *buffer, int is_write)
654{
655 struct ahci_probe_ent *probe_ent =
656 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700657 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
658 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic9f472e62012-02-22 00:24:39 +0000659 u8 port = probe_ent->hard_port_no;
660 u32 block;
661
662 block = start;
663
664 memset(cfis, 0, sizeof(struct sata_fis_h2d));
665
666 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
667 cfis->pm_port_c = 0x80; /* is command */
668 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
669 cfis->device = ATA_LBA;
670
671 cfis->device |= (block >> 24) & 0xf;
672 cfis->lba_high = (block >> 16) & 0xff;
673 cfis->lba_mid = (block >> 8) & 0xff;
674 cfis->lba_low = block & 0xff;
675 cfis->sector_count = (u8)(blkcnt & 0xff);
676
677 if (ahci_exec_ata_cmd(probe_ent, port, cfis,
678 buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0)
679 return blkcnt;
680 else
681 return 0;
682}
683
684void dwc_ahsata_flush_cache(int dev)
685{
686 struct ahci_probe_ent *probe_ent =
687 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700688 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
689 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic9f472e62012-02-22 00:24:39 +0000690 u8 port = probe_ent->hard_port_no;
691
692 memset(cfis, 0, sizeof(struct sata_fis_h2d));
693
694 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
695 cfis->pm_port_c = 0x80; /* is command */
696 cfis->command = ATA_CMD_FLUSH;
697
698 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
699}
700
701static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
702 u8 *buffer, int is_write)
703{
704 struct ahci_probe_ent *probe_ent =
705 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700706 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
707 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic9f472e62012-02-22 00:24:39 +0000708 u8 port = probe_ent->hard_port_no;
709 u64 block;
710
711 block = (u64)start;
712
713 memset(cfis, 0, sizeof(struct sata_fis_h2d));
714
715 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
716 cfis->pm_port_c = 0x80; /* is command */
717
718 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
719 : ATA_CMD_READ_EXT;
720
721 cfis->lba_high_exp = (block >> 40) & 0xff;
722 cfis->lba_mid_exp = (block >> 32) & 0xff;
723 cfis->lba_low_exp = (block >> 24) & 0xff;
724 cfis->lba_high = (block >> 16) & 0xff;
725 cfis->lba_mid = (block >> 8) & 0xff;
726 cfis->lba_low = block & 0xff;
727 cfis->device = ATA_LBA;
728 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
729 cfis->sector_count = blkcnt & 0xff;
730
731 if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer,
732 ATA_SECT_SIZE * blkcnt, is_write) > 0)
733 return blkcnt;
734 else
735 return 0;
736}
737
738u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
739 u8 *buffer, int is_write)
740{
741 struct ahci_probe_ent *probe_ent =
742 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700743 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
744 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic9f472e62012-02-22 00:24:39 +0000745 u8 port = probe_ent->hard_port_no;
746 u64 block;
747
748 if (sata_dev_desc[dev].lba48 != 1) {
749 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
750 return -1;
751 }
752
753 block = (u64)start;
754
755 memset(cfis, 0, sizeof(struct sata_fis_h2d));
756
757 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
758 cfis->pm_port_c = 0x80; /* is command */
759
760 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
761 : ATA_CMD_FPDMA_READ;
762
763 cfis->lba_high_exp = (block >> 40) & 0xff;
764 cfis->lba_mid_exp = (block >> 32) & 0xff;
765 cfis->lba_low_exp = (block >> 24) & 0xff;
766 cfis->lba_high = (block >> 16) & 0xff;
767 cfis->lba_mid = (block >> 8) & 0xff;
768 cfis->lba_low = block & 0xff;
769
770 cfis->device = ATA_LBA;
771 cfis->features_exp = (blkcnt >> 8) & 0xff;
772 cfis->features = blkcnt & 0xff;
773
774 /* Use the latest queue */
775 ahci_exec_ata_cmd(probe_ent, port, cfis,
776 buffer, ATA_SECT_SIZE * blkcnt, is_write);
777
778 return blkcnt;
779}
780
781void dwc_ahsata_flush_cache_ext(int dev)
782{
783 struct ahci_probe_ent *probe_ent =
784 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700785 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
786 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic9f472e62012-02-22 00:24:39 +0000787 u8 port = probe_ent->hard_port_no;
788
789 memset(cfis, 0, sizeof(struct sata_fis_h2d));
790
791 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
792 cfis->pm_port_c = 0x80; /* is command */
793 cfis->command = ATA_CMD_FLUSH_EXT;
794
795 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
796}
797
798static void dwc_ahsata_init_wcache(int dev, u16 *id)
799{
800 struct ahci_probe_ent *probe_ent =
801 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
802
803 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
804 probe_ent->flags |= SATA_FLAG_WCACHE;
805 if (ata_id_has_flush(id))
806 probe_ent->flags |= SATA_FLAG_FLUSH;
807 if (ata_id_has_flush_ext(id))
808 probe_ent->flags |= SATA_FLAG_FLUSH_EXT;
809}
810
811u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
Tom Rinidac87572012-09-29 07:53:06 -0700812 const void *buffer, int is_write)
Stefano Babic9f472e62012-02-22 00:24:39 +0000813{
814 u32 start, blks;
815 u8 *addr;
816 int max_blks;
817
818 start = blknr;
819 blks = blkcnt;
820 addr = (u8 *)buffer;
821
822 max_blks = ATA_MAX_SECTORS_LBA48;
823
824 do {
825 if (blks > max_blks) {
826 if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start,
827 max_blks, addr, is_write))
828 return 0;
829 start += max_blks;
830 blks -= max_blks;
831 addr += ATA_SECT_SIZE * max_blks;
832 } else {
833 if (blks != dwc_ahsata_rw_cmd_ext(dev, start,
834 blks, addr, is_write))
835 return 0;
836 start += blks;
837 blks = 0;
838 addr += ATA_SECT_SIZE * blks;
839 }
840 } while (blks != 0);
841
842 return blkcnt;
843}
844
845u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
Tom Rinidac87572012-09-29 07:53:06 -0700846 const void *buffer, int is_write)
Stefano Babic9f472e62012-02-22 00:24:39 +0000847{
848 u32 start, blks;
849 u8 *addr;
850 int max_blks;
851
852 start = blknr;
853 blks = blkcnt;
854 addr = (u8 *)buffer;
855
856 max_blks = ATA_MAX_SECTORS;
857 do {
858 if (blks > max_blks) {
859 if (max_blks != dwc_ahsata_rw_cmd(dev, start,
860 max_blks, addr, is_write))
861 return 0;
862 start += max_blks;
863 blks -= max_blks;
864 addr += ATA_SECT_SIZE * max_blks;
865 } else {
866 if (blks != dwc_ahsata_rw_cmd(dev, start,
867 blks, addr, is_write))
868 return 0;
869 start += blks;
870 blks = 0;
871 addr += ATA_SECT_SIZE * blks;
872 }
873 } while (blks != 0);
874
875 return blkcnt;
876}
877
878/*
879 * SATA interface between low level driver and command layer
880 */
Tom Rinidac87572012-09-29 07:53:06 -0700881ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
Stefano Babic9f472e62012-02-22 00:24:39 +0000882{
883 u32 rc;
884
885 if (sata_dev_desc[dev].lba48)
886 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
887 buffer, READ_CMD);
888 else
889 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
890 buffer, READ_CMD);
891 return rc;
892}
893
Tom Rinidac87572012-09-29 07:53:06 -0700894ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
Stefano Babic9f472e62012-02-22 00:24:39 +0000895{
896 u32 rc;
897 struct ahci_probe_ent *probe_ent =
898 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
899 u32 flags = probe_ent->flags;
900
901 if (sata_dev_desc[dev].lba48) {
902 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
903 buffer, WRITE_CMD);
904 if ((flags & SATA_FLAG_WCACHE) &&
905 (flags & SATA_FLAG_FLUSH_EXT))
906 dwc_ahsata_flush_cache_ext(dev);
907 } else {
908 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
909 buffer, WRITE_CMD);
910 if ((flags & SATA_FLAG_WCACHE) &&
911 (flags & SATA_FLAG_FLUSH))
912 dwc_ahsata_flush_cache(dev);
913 }
914 return rc;
915}
916
917int scan_sata(int dev)
918{
919 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
920 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
921 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
922 u16 *id;
923 u64 n_sectors;
924 struct ahci_probe_ent *probe_ent =
925 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
926 u8 port = probe_ent->hard_port_no;
927 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
928
Eric Nelson2dbe64c2013-06-15 16:09:55 -0700929 id = (u16 *)memalign(ARCH_DMA_MINALIGN,
930 roundup(ARCH_DMA_MINALIGN,
931 (ATA_ID_WORDS * 2)));
Stefano Babic9f472e62012-02-22 00:24:39 +0000932 if (!id) {
933 printf("id malloc failed\n\r");
934 return -1;
935 }
936
937 /* Identify device to get information */
938 dwc_ahsata_identify(dev, id);
939
940 /* Serial number */
941 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
942 memcpy(pdev->product, serial, sizeof(serial));
943
944 /* Firmware version */
945 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
946 memcpy(pdev->revision, firmware, sizeof(firmware));
947
948 /* Product model */
949 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
950 memcpy(pdev->vendor, product, sizeof(product));
951
952 /* Totoal sectors */
953 n_sectors = ata_id_n_sectors(id);
954 pdev->lba = (u32)n_sectors;
955
956 pdev->type = DEV_TYPE_HARDDISK;
957 pdev->blksz = ATA_SECT_SIZE;
958 pdev->lun = 0 ;
959
960 /* Check if support LBA48 */
961 if (ata_id_has_lba48(id)) {
962 pdev->lba48 = 1;
963 debug("Device support LBA48\n\r");
964 }
965
966 /* Get the NCQ queue depth from device */
967 probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK);
968 probe_ent->flags |= ata_id_queue_depth(id);
969
970 /* Get the xfer mode from device */
971 dwc_ahsata_xfer_mode(dev, id);
972
973 /* Get the write cache status from device */
974 dwc_ahsata_init_wcache(dev, id);
975
976 /* Set the xfer mode to highest speed */
977 ahci_set_feature(dev, port);
978
979 free((void *)id);
980
981 dwc_ahsata_print_info(dev);
982
983 is_ready = 1;
984
985 return 0;
986}