blob: 44ae7b1028cc4285954dd9980e2264accd25cc21 [file] [log] [blame]
Benoît Thébaudeau0f67e092013-04-23 10:17:41 +00001/*
2 * (C) Copyright 2009-2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
4 *
5 * Based on the mpc512x iim code:
6 * Copyright 2008 Silicon Turnkey Express, Inc.
7 * Martha Marx <mmarx@silicontkx.com>
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Benoît Thébaudeau0f67e092013-04-23 10:17:41 +000010 */
11
12#include <common.h>
13#include <fuse.h>
14#include <asm/errno.h>
15#include <asm/io.h>
16#ifndef CONFIG_MPC512X
17#include <asm/arch/imx-regs.h>
18#endif
19
20/* FSL IIM-specific constants */
21#define STAT_BUSY 0x80
22#define STAT_PRGD 0x02
23#define STAT_SNSD 0x01
24
25#define STATM_PRGD_M 0x02
26#define STATM_SNSD_M 0x01
27
28#define ERR_PRGE 0x80
29#define ERR_WPE 0x40
30#define ERR_OPE 0x20
31#define ERR_RPE 0x10
32#define ERR_WLRE 0x08
33#define ERR_SNSE 0x04
34#define ERR_PARITYE 0x02
35
36#define EMASK_PRGE_M 0x80
37#define EMASK_WPE_M 0x40
38#define EMASK_OPE_M 0x20
39#define EMASK_RPE_M 0x10
40#define EMASK_WLRE_M 0x08
41#define EMASK_SNSE_M 0x04
42#define EMASK_PARITYE_M 0x02
43
44#define FCTL_DPC 0x80
45#define FCTL_PRG_LENGTH_MASK 0x70
46#define FCTL_ESNS_N 0x08
47#define FCTL_ESNS_0 0x04
48#define FCTL_ESNS_1 0x02
49#define FCTL_PRG 0x01
50
51#define UA_A_BANK_MASK 0x38
52#define UA_A_ROWH_MASK 0x07
53
54#define LA_A_ROWL_MASK 0xf8
55#define LA_A_BIT_MASK 0x07
56
57#define PREV_PROD_REV_MASK 0xf8
58#define PREV_PROD_VT_MASK 0x07
59
60/* Select the correct accessors depending on endianness */
61#if __BYTE_ORDER == __LITTLE_ENDIAN
62#define iim_read32 in_le32
63#define iim_write32 out_le32
64#define iim_clrsetbits32 clrsetbits_le32
65#define iim_clrbits32 clrbits_le32
66#define iim_setbits32 setbits_le32
67#elif __BYTE_ORDER == __BIG_ENDIAN
68#define iim_read32 in_be32
69#define iim_write32 out_be32
70#define iim_clrsetbits32 clrsetbits_be32
71#define iim_clrbits32 clrbits_be32
72#define iim_setbits32 setbits_be32
73#else
74#error Endianess is not defined: please fix to continue
75#endif
76
77/* IIM control registers */
78struct fsl_iim {
79 u32 stat;
80 u32 statm;
81 u32 err;
82 u32 emask;
83 u32 fctl;
84 u32 ua;
85 u32 la;
86 u32 sdat;
87 u32 prev;
88 u32 srev;
89 u32 prg_p;
90 u32 scs[0x1f5];
91 struct {
92 u32 word[0x100];
93 } bank[8];
94};
95
96static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
97 const char *caller)
98{
99 *regs = (struct fsl_iim *)IIM_BASE_ADDR;
100
101 if (bank >= ARRAY_SIZE((*regs)->bank) ||
102 word >= ARRAY_SIZE((*regs)->bank[0].word) ||
103 !assert) {
104 printf("fsl_iim %s(): Invalid argument\n", caller);
105 return -EINVAL;
106 }
107
108 return 0;
109}
110
111static void clear_status(struct fsl_iim *regs)
112{
113 iim_setbits32(&regs->stat, 0);
114 iim_setbits32(&regs->err, 0);
115}
116
117static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
118{
119 *stat = iim_read32(&regs->stat);
120 *err = iim_read32(&regs->err);
121 clear_status(regs);
122}
123
124static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
125 const char *caller)
126{
127 int ret;
128
129 ret = prepare_access(regs, bank, word, val != NULL, caller);
130 if (ret)
131 return ret;
132
133 clear_status(*regs);
134
135 return 0;
136}
137
138int fuse_read(u32 bank, u32 word, u32 *val)
139{
140 struct fsl_iim *regs;
141 u32 stat, err;
142 int ret;
143
144 ret = prepare_read(&regs, bank, word, val, __func__);
145 if (ret)
146 return ret;
147
148 *val = iim_read32(&regs->bank[bank].word[word]);
149 finish_access(regs, &stat, &err);
150
151 if (err & ERR_RPE) {
152 puts("fsl_iim fuse_read(): Read protect error\n");
153 return -EIO;
154 }
155
156 return 0;
157}
158
159static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
160 u32 fctl, u32 *stat, u32 *err)
161{
162 iim_write32(&regs->ua, bank << 3 | word >> 5);
163 iim_write32(&regs->la, (word << 3 | bit) & 0xff);
164 if (fctl == FCTL_PRG)
165 iim_write32(&regs->prg_p, 0xaa);
166 iim_setbits32(&regs->fctl, fctl);
167 while (iim_read32(&regs->stat) & STAT_BUSY)
168 udelay(20);
169 finish_access(regs, stat, err);
170}
171
172int fuse_sense(u32 bank, u32 word, u32 *val)
173{
174 struct fsl_iim *regs;
175 u32 stat, err;
176 int ret;
177
178 ret = prepare_read(&regs, bank, word, val, __func__);
179 if (ret)
180 return ret;
181
182 direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
183
184 if (err & ERR_SNSE) {
185 puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
186 return -EIO;
187 }
188
189 if (!(stat & STAT_SNSD)) {
190 puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
191 return -EIO;
192 }
193
194 *val = iim_read32(&regs->sdat);
195 return 0;
196}
197
198static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
199{
200 u32 stat, err;
201
202 clear_status(regs);
203 direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
204 iim_write32(&regs->prg_p, 0x00);
205
206 if (err & ERR_PRGE) {
207 puts("fsl_iim fuse_prog(): Program error\n");
208 return -EIO;
209 }
210
211 if (err & ERR_WPE) {
212 puts("fsl_iim fuse_prog(): Write protect error\n");
213 return -EIO;
214 }
215
216 if (!(stat & STAT_PRGD)) {
217 puts("fsl_iim fuse_prog(): Program did not complete\n");
218 return -EIO;
219 }
220
221 return 0;
222}
223
224static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
225 const char *caller)
226{
227 return prepare_access(regs, bank, word, !(val & ~0xff), caller);
228}
229
230int fuse_prog(u32 bank, u32 word, u32 val)
231{
232 struct fsl_iim *regs;
233 u32 bit;
234 int ret;
235
236 ret = prepare_write(&regs, bank, word, val, __func__);
237 if (ret)
238 return ret;
239
240 for (bit = 0; val; bit++, val >>= 1)
241 if (val & 0x01) {
242 ret = prog_bit(regs, bank, word, bit);
243 if (ret)
244 return ret;
245 }
246
247 return 0;
248}
249
250int fuse_override(u32 bank, u32 word, u32 val)
251{
252 struct fsl_iim *regs;
253 u32 stat, err;
254 int ret;
255
256 ret = prepare_write(&regs, bank, word, val, __func__);
257 if (ret)
258 return ret;
259
260 clear_status(regs);
261 iim_write32(&regs->bank[bank].word[word], val);
262 finish_access(regs, &stat, &err);
263
264 if (err & ERR_OPE) {
265 puts("fsl_iim fuse_override(): Override protect error\n");
266 return -EIO;
267 }
268
269 return 0;
270}