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Daniel Hellstromc2b7da52008-03-28 20:22:53 +01001/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
2 *
3 * Driver use polling mode (no Interrupt)
4 *
5 * (C) Copyright 2007
6 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstromc2b7da52008-03-28 20:22:53 +01009 */
10
Daniel Hellstrom6644c192010-10-27 09:24:13 +020011/* #define DEBUG */
12
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010013#include <common.h>
14#include <command.h>
Joe Hershberger92ac5202015-05-04 14:55:14 -050015#include <errno.h>
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010016#include <net.h>
Ben Warren89973f82008-08-31 22:22:04 -070017#include <netdev.h>
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010018#include <malloc.h>
19#include <asm/processor.h>
20#include <ambapp.h>
21#include <asm/leon.h>
22
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010023#include "greth.h"
24
25/* Default to 3s timeout on autonegotiation */
26#ifndef GRETH_PHY_TIMEOUT_MS
27#define GRETH_PHY_TIMEOUT_MS 3000
28#endif
29
Daniel Hellstrome780d822010-10-22 11:26:49 +020030/* Default to PHY adrress 0 not not specified */
31#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
32#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
33#else
34#define GRETH_PHY_ADR_DEFAULT 0
35#endif
36
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010037/* ByPass Cache when reading regs */
38#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
39/* Write-through cache ==> no bypassing needed on writes */
Daniel Hellstrome3ce6862010-10-27 09:39:46 +020040#define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010041#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
42#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
43
44#define GRETH_RXBD_CNT 4
45#define GRETH_TXBD_CNT 1
46
47#define GRETH_RXBUF_SIZE 1540
48#define GRETH_BUF_ALIGN 4
49#define GRETH_RXBUF_EFF_SIZE \
50 ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
51
52typedef struct {
53 greth_regs *regs;
54 int irq;
55 struct eth_device *dev;
56
57 /* Hardware info */
58 unsigned char phyaddr;
59 int gbit_mac;
60
61 /* Current operating Mode */
62 int gb; /* GigaBit */
63 int fd; /* Full Duplex */
64 int sp; /* 10/100Mbps speed (1=100,0=10) */
65 int auto_neg; /* Auto negotiate done */
66
67 unsigned char hwaddr[6]; /* MAC Address */
68
69 /* Descriptors */
70 greth_bd *rxbd_base, *rxbd_max;
71 greth_bd *txbd_base, *txbd_max;
72
73 greth_bd *rxbd_curr;
74
75 /* rx buffers in rx descriptors */
76 void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
77
78 /* unused for gbit_mac, temp buffer for sending packets with unligned
79 * start.
80 * Pointer to packet allocated with malloc.
81 */
82 void *txbuf;
83
84 struct {
85 /* rx status */
86 unsigned int rx_packets,
87 rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
88
89 /* tx stats */
90 unsigned int tx_packets,
91 tx_latecol_errors,
92 tx_underrun_errors, tx_limit_errors, tx_errors;
93 } stats;
94} greth_priv;
95
96/* Read MII register 'addr' from core 'regs' */
Daniel Hellstrome780d822010-10-22 11:26:49 +020097static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010098{
99 while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
100 }
101
Daniel Hellstrome780d822010-10-22 11:26:49 +0200102 GRETH_REGSAVE(&regs->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100103
104 while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
105 }
106
107 if (!(GRETH_REGLOAD(&regs->mdio) & GRETH_MII_NVALID)) {
108 return (GRETH_REGLOAD(&regs->mdio) >> 16) & 0xFFFF;
109 } else {
110 return -1;
111 }
112}
113
Daniel Hellstrome780d822010-10-22 11:26:49 +0200114static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100115{
116 while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
117 }
118
119 GRETH_REGSAVE(&regs->mdio,
Daniel Hellstrome780d822010-10-22 11:26:49 +0200120 ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
121 ((regaddr & 0x1F) << 6) | 1);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100122
123 while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
124 }
125
126}
127
128/* init/start hardware and allocate descriptor buffers for rx side
129 *
130 */
131int greth_init(struct eth_device *dev, bd_t * bis)
132{
133 int i;
134
135 greth_priv *greth = dev->priv;
136 greth_regs *regs = greth->regs;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200137
138 debug("greth_init\n");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100139
Daniel Hellstrom533b67d2010-10-22 11:34:01 +0200140 /* Reset core */
141 GRETH_REGSAVE(&regs->control, (GRETH_RESET | (greth->gb << 8) |
142 (greth->sp << 7) | (greth->fd << 4)));
143
144 /* Wait for Reset to complete */
145 while ( GRETH_REGLOAD(&regs->control) & GRETH_RESET) ;
146
147 GRETH_REGSAVE(&regs->control,
148 ((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));
149
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100150 if (!greth->rxbd_base) {
151
152 /* allocate descriptors */
153 greth->rxbd_base = (greth_bd *)
154 memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
155 greth->txbd_base = (greth_bd *)
Daniel Hellstromed52d122010-10-22 11:36:39 +0200156 memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100157
158 /* allocate buffers to all descriptors */
159 greth->rxbuf_base =
160 malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
161 }
162
163 /* initate rx decriptors */
164 for (i = 0; i < GRETH_RXBD_CNT; i++) {
165 greth->rxbd_base[i].addr = (unsigned int)
166 greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
167 /* enable desciptor & set wrap bit if last descriptor */
168 if (i >= (GRETH_RXBD_CNT - 1)) {
169 greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
170 } else {
171 greth->rxbd_base[i].stat = GRETH_BD_EN;
172 }
173 }
174
175 /* initiate indexes */
176 greth->rxbd_curr = greth->rxbd_base;
177 greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
178 greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
179 /*
180 * greth->txbd_base->addr = 0;
181 * greth->txbd_base->stat = GRETH_BD_WR;
182 */
183
184 /* initate tx decriptors */
185 for (i = 0; i < GRETH_TXBD_CNT; i++) {
186 greth->txbd_base[i].addr = 0;
187 /* enable desciptor & set wrap bit if last descriptor */
Daniel Hellstromed52d122010-10-22 11:36:39 +0200188 if (i >= (GRETH_TXBD_CNT - 1)) {
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100189 greth->txbd_base[i].stat = GRETH_BD_WR;
190 } else {
191 greth->txbd_base[i].stat = 0;
192 }
193 }
194
195 /**** SET HARDWARE REGS ****/
196
197 /* Set pointer to tx/rx descriptor areas */
198 GRETH_REGSAVE(&regs->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
199 GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
200
201 /* Enable Transmitter, GRETH will now scan descriptors for packets
202 * to transmitt */
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200203 debug("greth_init: enabling receiver\n");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100204 GRETH_REGORIN(&regs->control, GRETH_RXEN);
205
206 return 0;
207}
208
209/* Initiate PHY to a relevant speed
210 * return:
211 * - 0 = success
212 * - 1 = timeout/fail
213 */
214int greth_init_phy(greth_priv * dev, bd_t * bis)
215{
216 greth_regs *regs = dev->regs;
217 int tmp, tmp1, tmp2, i;
218 unsigned int start, timeout;
Daniel Hellstrome780d822010-10-22 11:26:49 +0200219 int phyaddr = GRETH_PHY_ADR_DEFAULT;
220
221#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
222 /* If BSP doesn't provide a hardcoded PHY address the driver will
223 * try to autodetect PHY address by stopping the search on the first
224 * PHY address which has REG0 implemented.
225 */
226 for (i=0; i<32; i++) {
227 tmp = read_mii(i, 0, regs);
228 if ( (tmp != 0) && (tmp != 0xffff) ) {
229 phyaddr = i;
230 break;
231 }
232 }
233#endif
234
235 /* Save PHY Address */
236 dev->phyaddr = phyaddr;
237
238 debug("GRETH PHY ADDRESS: %d\n", phyaddr);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100239
240 /* X msecs to ticks */
241 timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);
242
243 /* Get system timer0 current value
244 * Total timeout is 5s
245 */
246 start = get_timer(0);
247
248 /* get phy control register default values */
249
Daniel Hellstrome780d822010-10-22 11:26:49 +0200250 while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
251 if (get_timer(start) > timeout) {
252 debug("greth_init_phy: PHY read 1 failed\n");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100253 return 1; /* Fail */
Daniel Hellstrome780d822010-10-22 11:26:49 +0200254 }
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100255 }
256
257 /* reset PHY and wait for completion */
Daniel Hellstrome780d822010-10-22 11:26:49 +0200258 write_mii(phyaddr, 0, 0x8000 | tmp, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100259
Daniel Hellstrome780d822010-10-22 11:26:49 +0200260 while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
261 if (get_timer(start) > timeout) {
262 debug("greth_init_phy: PHY read 2 failed\n");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100263 return 1; /* Fail */
Daniel Hellstrome780d822010-10-22 11:26:49 +0200264 }
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100265 }
266
267 /* Check if PHY is autoneg capable and then determine operating
268 * mode, otherwise force it to 10 Mbit halfduplex
269 */
270 dev->gb = 0;
271 dev->fd = 0;
272 dev->sp = 0;
273 dev->auto_neg = 0;
274 if (!((tmp >> 12) & 1)) {
Daniel Hellstrome780d822010-10-22 11:26:49 +0200275 write_mii(phyaddr, 0, 0, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100276 } else {
277 /* wait for auto negotiation to complete and then check operating mode */
278 dev->auto_neg = 1;
279 i = 0;
Daniel Hellstrome780d822010-10-22 11:26:49 +0200280 while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100281 if (get_timer(start) > timeout) {
282 printf("Auto negotiation timed out. "
283 "Selecting default config\n");
Daniel Hellstrome780d822010-10-22 11:26:49 +0200284 tmp = read_mii(phyaddr, 0, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100285 dev->gb = ((tmp >> 6) & 1)
286 && !((tmp >> 13) & 1);
287 dev->sp = !((tmp >> 6) & 1)
288 && ((tmp >> 13) & 1);
289 dev->fd = (tmp >> 8) & 1;
290 goto auto_neg_done;
291 }
292 }
293 if ((tmp >> 8) & 1) {
Daniel Hellstrome780d822010-10-22 11:26:49 +0200294 tmp1 = read_mii(phyaddr, 9, regs);
295 tmp2 = read_mii(phyaddr, 10, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100296 if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
297 (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
298 dev->gb = 1;
299 dev->fd = 1;
300 }
301 if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
302 (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
303 dev->gb = 1;
304 dev->fd = 0;
305 }
306 }
307 if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
Daniel Hellstrome780d822010-10-22 11:26:49 +0200308 tmp1 = read_mii(phyaddr, 4, regs);
309 tmp2 = read_mii(phyaddr, 5, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100310 if ((tmp1 & GRETH_MII_100TXFD) &&
311 (tmp2 & GRETH_MII_100TXFD)) {
312 dev->sp = 1;
313 dev->fd = 1;
314 }
315 if ((tmp1 & GRETH_MII_100TXHD) &&
316 (tmp2 & GRETH_MII_100TXHD)) {
317 dev->sp = 1;
318 dev->fd = 0;
319 }
320 if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
321 dev->fd = 1;
322 }
323 if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
324 dev->gb = 0;
325 dev->fd = 0;
Daniel Hellstrome780d822010-10-22 11:26:49 +0200326 write_mii(phyaddr, 0, dev->sp << 13, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100327 }
328 }
329
330 }
331 auto_neg_done:
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200332 debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100333 %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100334 /* Read out PHY info if extended registers are available */
335 if (tmp & 1) {
Daniel Hellstrome780d822010-10-22 11:26:49 +0200336 tmp1 = read_mii(phyaddr, 2, regs);
337 tmp2 = read_mii(phyaddr, 3, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100338 tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
339 tmp = tmp2 & 0xF;
340
341 tmp2 = (tmp2 >> 4) & 0x3F;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200342 debug("PHY: Vendor %x Device %x Revision %d\n", tmp1,
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100343 tmp2, tmp);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100344 } else {
345 printf("PHY info not available\n");
346 }
347
348 /* set speed and duplex bits in control register */
349 GRETH_REGORIN(&regs->control,
350 (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
351
352 return 0;
353}
354
355void greth_halt(struct eth_device *dev)
356{
357 greth_priv *greth;
358 greth_regs *regs;
359 int i;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200360
361 debug("greth_halt\n");
362
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100363 if (!dev || !dev->priv)
364 return;
365
366 greth = dev->priv;
367 regs = greth->regs;
368
369 if (!regs)
370 return;
371
372 /* disable receiver/transmitter by clearing the enable bits */
373 GRETH_REGANDIN(&regs->control, ~(GRETH_RXEN | GRETH_TXEN));
374
375 /* reset rx/tx descriptors */
376 if (greth->rxbd_base) {
377 for (i = 0; i < GRETH_RXBD_CNT; i++) {
378 greth->rxbd_base[i].stat =
379 (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
380 }
381 }
382
383 if (greth->txbd_base) {
384 for (i = 0; i < GRETH_TXBD_CNT; i++) {
385 greth->txbd_base[i].stat =
386 (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
387 }
388 }
389}
390
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000391int greth_send(struct eth_device *dev, void *eth_data, int data_length)
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100392{
393 greth_priv *greth = dev->priv;
394 greth_regs *regs = greth->regs;
395 greth_bd *txbd;
396 void *txbuf;
397 unsigned int status;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200398
399 debug("greth_send\n");
400
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100401 /* send data, wait for data to be sent, then return */
402 if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
403 && !greth->gbit_mac) {
404 /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
405 * and copy data to before giving it to GRETH.
406 */
407 if (!greth->txbuf) {
408 greth->txbuf = malloc(GRETH_RXBUF_SIZE);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100409 }
410
411 txbuf = greth->txbuf;
412
413 /* copy data info buffer */
414 memcpy((char *)txbuf, (char *)eth_data, data_length);
415
416 /* keep buffer to next time */
417 } else {
418 txbuf = (void *)eth_data;
419 }
420 /* get descriptor to use, only 1 supported... hehe easy */
421 txbd = greth->txbd_base;
422
423 /* setup descriptor to wrap around to it self */
424 txbd->addr = (unsigned int)txbuf;
425 txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
426
427 /* Remind Core which descriptor to use when sending */
428 GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)txbd);
429
430 /* initate send by enabling transmitter */
431 GRETH_REGORIN(&regs->control, GRETH_TXEN);
432
433 /* Wait for data to be sent */
434 while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
435 ;
436 }
437
438 /* was the packet transmitted succesfully? */
439 if (status & GRETH_TXBD_ERR_AL) {
440 greth->stats.tx_limit_errors++;
441 }
442
443 if (status & GRETH_TXBD_ERR_UE) {
444 greth->stats.tx_underrun_errors++;
445 }
446
447 if (status & GRETH_TXBD_ERR_LC) {
448 greth->stats.tx_latecol_errors++;
449 }
450
451 if (status &
452 (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
453 /* any error */
454 greth->stats.tx_errors++;
455 return -1;
456 }
457
458 /* bump tx packet counter */
459 greth->stats.tx_packets++;
460
461 /* return succefully */
462 return 0;
463}
464
465int greth_recv(struct eth_device *dev)
466{
467 greth_priv *greth = dev->priv;
468 greth_regs *regs = greth->regs;
469 greth_bd *rxbd;
470 unsigned int status, len = 0, bad;
Marek Vasutfa2afe02012-07-27 08:04:32 +0000471 char *d;
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100472 int enable = 0;
473 int i;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200474
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100475 /* Receive One packet only, but clear as many error packets as there are
476 * available.
477 */
478 {
479 /* current receive descriptor */
480 rxbd = greth->rxbd_curr;
481
482 /* get status of next received packet */
483 status = GRETH_REGLOAD(&rxbd->stat);
484
485 bad = 0;
486
487 /* stop if no more packets received */
488 if (status & GRETH_BD_EN) {
489 goto done;
490 }
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200491
Marek Vasutfa2afe02012-07-27 08:04:32 +0000492 debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100493 (unsigned int)rxbd, status, status & GRETH_BD_LEN);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100494
495 /* Check status for errors.
496 */
497 if (status & GRETH_RXBD_ERR_FT) {
498 greth->stats.rx_length_errors++;
499 bad = 1;
500 }
501 if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
502 greth->stats.rx_frame_errors++;
503 bad = 1;
504 }
505 if (status & GRETH_RXBD_ERR_CRC) {
506 greth->stats.rx_crc_errors++;
507 bad = 1;
508 }
509 if (bad) {
510 greth->stats.rx_errors++;
511 printf
512 ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
513 greth->stats.rx_length_errors,
514 greth->stats.rx_frame_errors,
515 greth->stats.rx_crc_errors, status,
516 greth->stats.rx_packets);
517 /* print all rx descriptors */
518 for (i = 0; i < GRETH_RXBD_CNT; i++) {
519 printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
520 GRETH_REGLOAD(&greth->rxbd_base[i].stat),
Daniel Hellstrome780d822010-10-22 11:26:49 +0200521 GRETH_REGLOAD(&greth->rxbd_base[i].addr));
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100522 }
523 } else {
524 /* Process the incoming packet. */
525 len = status & GRETH_BD_LEN;
526 d = (char *)rxbd->addr;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200527
528 debug
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100529 ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
530 len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
531 d[7]);
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200532
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100533 /* flush all data cache to make sure we're not reading old packet data */
534 sparc_dcache_flush_all();
535
536 /* pass packet on to network subsystem */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500537 net_process_received_packet((void *)d, len);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100538
539 /* bump stats counters */
540 greth->stats.rx_packets++;
541
542 /* bad is now 0 ==> will stop loop */
543 }
544
545 /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
546 rxbd->stat =
547 GRETH_BD_EN |
548 (((unsigned int)greth->rxbd_curr >=
549 (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
550 enable = 1;
551
552 /* increase index */
553 greth->rxbd_curr =
554 ((unsigned int)greth->rxbd_curr >=
555 (unsigned int)greth->rxbd_max) ? greth->
556 rxbd_base : (greth->rxbd_curr + 1);
557
Daniel Hellstrome780d822010-10-22 11:26:49 +0200558 }
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100559
560 if (enable) {
561 GRETH_REGORIN(&regs->control, GRETH_RXEN);
562 }
563 done:
Mike Williams16263082011-07-22 04:01:30 +0000564 /* return positive length of packet or 0 if non received */
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100565 return len;
566}
567
568void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
569{
570 /* save new MAC address */
571 greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
572 greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
573 greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
574 greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
575 greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
576 greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
577 greth->regs->esa_msb = (mac[0] << 8) | mac[1];
578 greth->regs->esa_lsb =
579 (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200580
581 debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100582 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100583}
584
585int greth_initialize(bd_t * bis)
586{
587 greth_priv *greth;
588 ambapp_apbdev apbdev;
589 struct eth_device *dev;
590 int i;
591 char *addr_str, *end;
592 unsigned char addr[6];
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200593
594 debug("Scanning for GRETH\n");
595
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100596 /* Find Device & IRQ via AMBA Plug&Play information */
597 if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
598 return -1; /* GRETH not found */
599 }
600
601 greth = (greth_priv *) malloc(sizeof(greth_priv));
602 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
603 memset(dev, 0, sizeof(struct eth_device));
604 memset(greth, 0, sizeof(greth_priv));
605
606 greth->regs = (greth_regs *) apbdev.address;
607 greth->irq = apbdev.irq;
Marek Vasutfa2afe02012-07-27 08:04:32 +0000608 debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100609 dev->priv = (void *)greth;
610 dev->iobase = (unsigned int)greth->regs;
611 dev->init = greth_init;
612 dev->halt = greth_halt;
613 dev->send = greth_send;
614 dev->recv = greth_recv;
615 greth->dev = dev;
616
617 /* Reset Core */
618 GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
619
620 /* Wait for core to finish reset cycle */
621 while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
622
623 /* Get the phy address which assumed to have been set
624 correctly with the reset value in hardware */
625 greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
626
627 /* Check if mac is gigabit capable */
628 greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
629
630 /* Make descriptor string */
631 if (greth->gbit_mac) {
Daniel Hellstrom64394662010-10-21 15:08:11 +0200632 sprintf(dev->name, "GRETH_10/100/GB");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100633 } else {
Daniel Hellstrom64394662010-10-21 15:08:11 +0200634 sprintf(dev->name, "GRETH_10/100");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100635 }
636
637 /* initiate PHY, select speed/duplex depending on connected PHY */
638 if (greth_init_phy(greth, bis)) {
639 /* Failed to init PHY (timedout) */
Marek Vasutfa2afe02012-07-27 08:04:32 +0000640 debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100641 return -1;
642 }
643
644 /* Register Device to EtherNet subsystem */
645 eth_register(dev);
646
647 /* Get MAC address */
648 if ((addr_str = getenv("ethaddr")) != NULL) {
649 for (i = 0; i < 6; i++) {
650 addr[i] =
651 addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
652 if (addr_str) {
653 addr_str = (*end) ? end + 1 : end;
654 }
655 }
656 } else {
Joe Hershberger92ac5202015-05-04 14:55:14 -0500657 /* No ethaddr set */
658 return -EINVAL;
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100659 }
660
661 /* set and remember MAC address */
662 greth_set_hwaddr(greth, addr);
663
Marek Vasutfa2afe02012-07-27 08:04:32 +0000664 debug("GRETH[%p]: Initialized successfully\n", greth->regs);
Ben Warrenfc363ce2008-07-09 01:04:19 -0700665 return 0;
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100666}