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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 2657c52e08872f3c726185ecc5e8e6064ffbc3d5 / . / arch / arm / dts / am437x-gp-evm.dts
blob: 8dd49335a5ccecbb87904a4366027d367d0acc7d [file] [log] [blame]
Andrew Davisad841292023-04-11 13:24:55 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]2/*
Andrew Davisad841292023-04-11 13:24:55 -0500[diff] [blame]3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]4 */
5
6/* AM437x GP EVM */
7
8/dts-v1/;
9
10#include "am4372.dtsi"
11#include <dt-bindings/pinctrl/am43xx.h>
12#include <dt-bindings/pwm/pwm.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "TI AM437x GP EVM";
17 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
18
19 aliases {
20 display0 = &lcd0;
21 serial3 = &uart3;
22 };
23
24 chosen {
25 stdout-path = &uart0;
Mugunthan V Nff9e6122015-12-24 16:08:11 +0530[diff] [blame]26 tick-timer = &timer2;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]27 };
28
29 vmmcsd_fixed: fixedregulator-sd {
30 compatible = "regulator-fixed";
31 regulator-name = "vmmcsd_fixed";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 enable-active-high;
35 };
36
37 vtt_fixed: fixedregulator-vtt {
38 compatible = "regulator-fixed";
39 regulator-name = "vtt_fixed";
40 regulator-min-microvolt = <1500000>;
41 regulator-max-microvolt = <1500000>;
42 regulator-always-on;
43 regulator-boot-on;
44 enable-active-high;
45 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
46 };
47
48 vmmcwl_fixed: fixedregulator-mmcwl {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmcwl_fixed";
51 regulator-min-microvolt = <1800000>;
52 regulator-max-microvolt = <1800000>;
53 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
54 enable-active-high;
55 };
56
57 backlight {
58 compatible = "pwm-backlight";
59 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
60 brightness-levels = <0 51 53 56 62 75 101 152 255>;
61 default-brightness-level = <8>;
62 };
63
64 matrix_keypad: matrix_keypad@0 {
65 compatible = "gpio-matrix-keypad";
66 debounce-delay-ms = <5>;
67 col-scan-delay-us = <2>;
68
69 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
70 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
71 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
72
73 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
74 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
75
76 linux,keymap = <0x00000201 /* P1 */
77 0x00010202 /* P2 */
78 0x01000067 /* UP */
79 0x0101006a /* RIGHT */
80 0x02000069 /* LEFT */
81 0x0201006c>; /* DOWN */
82 };
83
84 lcd0: display {
85 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
86 label = "lcd";
87
88 pinctrl-names = "default";
89 pinctrl-0 = <&lcd_pins>;
90
91 /*
92 * SelLCDorHDMI, LOW to select HDMI. This is not really the
93 * panel's enable GPIO, but we don't have HDMI driver support nor
94 * support to switch between two displays, so using this gpio as
95 * panel's enable should be safe.
96 */
97 enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
98
99 panel-timing {
100 clock-frequency = <33000000>;
101 hactive = <800>;
102 vactive = <480>;
103 hfront-porch = <210>;
104 hback-porch = <16>;
105 hsync-len = <30>;
106 vback-porch = <10>;
107 vfront-porch = <22>;
108 vsync-len = <13>;
109 hsync-active = <0>;
110 vsync-active = <0>;
111 de-active = <1>;
112 pixelclk-active = <1>;
113 };
114
115 port {
116 lcd_in: endpoint {
117 remote-endpoint = <&dpi_out>;
118 };
119 };
120 };
121
122 /* fixed 12MHz oscillator */
123 refclk: oscillator {
124 #clock-cells = <0>;
125 compatible = "fixed-clock";
126 clock-frequency = <12000000>;
127 };
128
129};
130
131&am43xx_pinmux {
132 pinctrl-names = "default", "sleep";
133 pinctrl-0 = <&wlan_pins_default>;
134 pinctrl-1 = <&wlan_pins_sleep>;
135
136 i2c0_pins: i2c0_pins {
137 pinctrl-single,pins = <
138 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
139 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
140 >;
141 };
142
143 i2c1_pins: i2c1_pins {
144 pinctrl-single,pins = <
145 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
146 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
147 >;
148 };
149
150 mmc1_pins: pinmux_mmc1_pins {
151 pinctrl-single,pins = <
152 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
153 >;
154 };
155
156 ecap0_pins: backlight_pins {
157 pinctrl-single,pins = <
158 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
159 >;
160 };
161
162 pixcir_ts_pins: pixcir_ts_pins {
163 pinctrl-single,pins = <
164 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
165 >;
166 };
167
168 cpsw_default: cpsw_default {
169 pinctrl-single,pins = <
170 /* Slave 1 */
171 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
172 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
173 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
174 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
175 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
176 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
177 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
178 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
179 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
180 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
181 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
182 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
183 >;
184 };
185
186 cpsw_sleep: cpsw_sleep {
187 pinctrl-single,pins = <
188 /* Slave 1 reset value */
189 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
190 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
191 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
192 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
193 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
194 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
195 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
196 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
197 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
198 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
199 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
200 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
201 >;
202 };
203
204 davinci_mdio_default: davinci_mdio_default {
205 pinctrl-single,pins = <
206 /* MDIO */
207 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
208 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
209 >;
210 };
211
212 davinci_mdio_sleep: davinci_mdio_sleep {
213 pinctrl-single,pins = <
214 /* MDIO reset value */
215 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
216 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
217 >;
218 };
219
220 nand_flash_x8: nand_flash_x8 {
221 pinctrl-single,pins = <
222 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
223 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
224 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
225 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
226 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
227 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
228 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
229 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
230 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
231 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
232 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
233 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
234 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
235 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
236 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
237 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
238 >;
239 };
240
241 dss_pins: dss_pins {
242 pinctrl-single,pins = <
243 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
244 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
245 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
246 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
247 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
248 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
249 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
250 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
251 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
252 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
253 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
254 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
255 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
256 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
257 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
258 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
259 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
260 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
261 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
262 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
263 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
264 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
265 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
266 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
267 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
268 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
269 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
270 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
271
272 >;
273 };
274
275 lcd_pins: lcd_pins {
276 pinctrl-single,pins = <
277 /* GPIO 5_8 to select LCD / HDMI */
278 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
279 >;
280 };
281
282 dcan0_default: dcan0_default_pins {
283 pinctrl-single,pins = <
284 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
285 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
286 >;
287 };
288
289 dcan1_default: dcan1_default_pins {
290 pinctrl-single,pins = <
291 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
292 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
293 >;
294 };
295
296 vpfe0_pins_default: vpfe0_pins_default {
297 pinctrl-single,pins = <
298 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
299 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
300 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
301 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
302 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
303 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
304 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
305 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
306 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
307 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
308 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
309 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
310 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
311 >;
312 };
313
314 vpfe0_pins_sleep: vpfe0_pins_sleep {
315 pinctrl-single,pins = <
316 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
317 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
318 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
319 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
320 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
321 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
322 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
323 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
324 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
325 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
326 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
327 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
328 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
329 >;
330 };
331
332 vpfe1_pins_default: vpfe1_pins_default {
333 pinctrl-single,pins = <
334 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
335 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
336 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
337 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
338 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
339 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
340 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
341 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
342 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
343 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
344 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
345 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
346 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
347 >;
348 };
349
350 vpfe1_pins_sleep: vpfe1_pins_sleep {
351 pinctrl-single,pins = <
352 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
353 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
354 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
355 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
356 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
357 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
358 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
359 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
360 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
361 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
362 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
363 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
364 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
365 >;
366 };
367
368 mmc3_pins_default: pinmux_mmc3_pins_default {
369 pinctrl-single,pins = <
370 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
371 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
372 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
373 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
374 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
375 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
376 >;
377 };
378
379 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
380 pinctrl-single,pins = <
381 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
382 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
383 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
384 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
385 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
386 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
387 >;
388 };
389
390 wlan_pins_default: pinmux_wlan_pins_default {
391 pinctrl-single,pins = <
392 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
393 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
394 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
395 >;
396 };
397
398 wlan_pins_sleep: pinmux_wlan_pins_sleep {
399 pinctrl-single,pins = <
400 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
401 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
402 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
403 >;
404 };
405
406 uart3_pins: uart3_pins {
407 pinctrl-single,pins = <
408 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
409 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
410 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
411 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
412 >;
413 };
414};
415
416&i2c0 {
417 status = "okay";
418 pinctrl-names = "default";
419 pinctrl-0 = <&i2c0_pins>;
420 clock-frequency = <100000>;
421
422 tps65218: tps65218@24 {
423 reg = <0x24>;
424 compatible = "ti,tps65218";
425 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
426 interrupt-controller;
427 #interrupt-cells = <2>;
428
429 dcdc1: regulator-dcdc1 {
430 compatible = "ti,tps65218-dcdc1";
431 regulator-name = "vdd_core";
432 regulator-min-microvolt = <912000>;
433 regulator-max-microvolt = <1144000>;
434 regulator-boot-on;
435 regulator-always-on;
436 };
437
438 dcdc2: regulator-dcdc2 {
439 compatible = "ti,tps65218-dcdc2";
440 regulator-name = "vdd_mpu";
441 regulator-min-microvolt = <912000>;
442 regulator-max-microvolt = <1378000>;
443 regulator-boot-on;
444 regulator-always-on;
445 };
446
447 dcdc3: regulator-dcdc3 {
448 compatible = "ti,tps65218-dcdc3";
449 regulator-name = "vdcdc3";
450 regulator-min-microvolt = <1500000>;
451 regulator-max-microvolt = <1500000>;
452 regulator-boot-on;
453 regulator-always-on;
454 };
455 dcdc5: regulator-dcdc5 {
456 compatible = "ti,tps65218-dcdc5";
457 regulator-name = "v1_0bat";
458 regulator-min-microvolt = <1000000>;
459 regulator-max-microvolt = <1000000>;
460 };
461
462 dcdc6: regulator-dcdc6 {
463 compatible = "ti,tps65218-dcdc6";
464 regulator-name = "v1_8bat";
465 regulator-min-microvolt = <1800000>;
466 regulator-max-microvolt = <1800000>;
467 };
468
469 ldo1: regulator-ldo1 {
470 compatible = "ti,tps65218-ldo1";
471 regulator-min-microvolt = <1800000>;
472 regulator-max-microvolt = <1800000>;
473 regulator-boot-on;
474 regulator-always-on;
475 };
476 };
477
478 ov2659@30 {
479 compatible = "ovti,ov2659";
480 reg = <0x30>;
481
482 clocks = <&refclk 0>;
483 clock-names = "xvclk";
484
485 port {
486 ov2659_0: endpoint {
487 remote-endpoint = <&vpfe1_ep>;
488 link-frequencies = /bits/ 64 <70000000>;
489 };
490 };
491 };
492};
493
494&i2c1 {
495 status = "okay";
496 pinctrl-names = "default";
497 pinctrl-0 = <&i2c1_pins>;
498 pixcir_ts@5c {
499 compatible = "pixcir,pixcir_tangoc";
500 pinctrl-names = "default";
501 pinctrl-0 = <&pixcir_ts_pins>;
502 reg = <0x5c>;
503 interrupt-parent = <&gpio3>;
504 interrupts = <22 0>;
505
506 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
507
508 touchscreen-size-x = <1024>;
509 touchscreen-size-y = <600>;
510 };
511
512 ov2659@30 {
513 compatible = "ovti,ov2659";
514 reg = <0x30>;
515
516 clocks = <&refclk 0>;
517 clock-names = "xvclk";
518
519 port {
520 ov2659_1: endpoint {
521 remote-endpoint = <&vpfe0_ep>;
522 link-frequencies = /bits/ 64 <70000000>;
523 };
524 };
525 };
526};
527
528&epwmss0 {
529 status = "okay";
530};
531
532&tscadc {
533 status = "okay";
534
535 adc {
536 ti,adc-channels = <0 1 2 3 4 5 6 7>;
537 };
538};
539
540&ecap0 {
541 status = "okay";
542 pinctrl-names = "default";
543 pinctrl-0 = <&ecap0_pins>;
544};
545
546&gpio0 {
547 status = "okay";
548};
549
550&gpio1 {
551 status = "okay";
552};
553
554&gpio3 {
555 status = "okay";
556};
557
558&gpio4 {
559 status = "okay";
560};
561
562&gpio5 {
563 status = "okay";
564 ti,no-reset-on-init;
565};
566
567&mmc1 {
568 status = "okay";
569 vmmc-supply = <&vmmcsd_fixed>;
570 bus-width = <4>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&mmc1_pins>;
Mugunthan V N103afa22016-04-04 17:28:02 +0530[diff] [blame]573 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]574};
575
576&mmc3 {
577 /* disable MMC3 as SDIO is not supported in U-Boot */
578 status = "disabled";
579 /* these are on the crossbar and are outlined in the
580 xbar-event-map element */
581 dmas = <&edma 30
582 &edma 31>;
583 dma-names = "tx", "rx";
584 vmmc-supply = <&vmmcwl_fixed>;
585 bus-width = <4>;
586 pinctrl-names = "default", "sleep";
587 pinctrl-0 = <&mmc3_pins_default>;
588 pinctrl-1 = <&mmc3_pins_sleep>;
589 cap-power-off-card;
590 keep-power-in-suspend;
591 ti,non-removable;
592
593 #address-cells = <1>;
594 #size-cells = <0>;
595 wlcore: wlcore@0 {
596 compatible = "ti,wl1835";
597 reg = <2>;
598 interrupt-parent = <&gpio1>;
599 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
600 };
601};
602
603&edma {
604 ti,edma-xbar-event-map = /bits/ 16 <1 30
605 2 31>;
606};
607
608&uart3 {
609 status = "okay";
610 pinctrl-names = "default";
611 pinctrl-0 = <&uart3_pins>;
612};
613
614&usb2_phy1 {
615 status = "okay";
616};
617
618&usb1 {
619 dr_mode = "peripheral";
620 status = "okay";
621};
622
623&usb2_phy2 {
624 status = "okay";
625};
626
627&usb2 {
628 dr_mode = "host";
629 status = "okay";
630};
631
632&mac {
633 slaves = <1>;
634 pinctrl-names = "default", "sleep";
635 pinctrl-0 = <&cpsw_default>;
636 pinctrl-1 = <&cpsw_sleep>;
637 status = "okay";
638};
639
640&davinci_mdio {
641 pinctrl-names = "default", "sleep";
642 pinctrl-0 = <&davinci_mdio_default>;
643 pinctrl-1 = <&davinci_mdio_sleep>;
644 status = "okay";
Grygorii Strashkob1fe4fe2019-08-31 10:30:33 +0300[diff] [blame]645
646 ethphy0: ethernet-phy@0 {
647 reg = <0>;
648 };
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]649};
650
651&cpsw_emac0 {
Grygorii Strashkob1fe4fe2019-08-31 10:30:33 +0300[diff] [blame]652 phy-handle = <&ethphy0>;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]653 phy-mode = "rgmii";
654};
655
656&elm {
657 status = "okay";
658};
659
660&gpmc {
661 status = "okay";
662 pinctrl-names = "default";
663 pinctrl-0 = <&nand_flash_x8>;
664 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
665 nand@0,0 {
666 reg = <0 0 4>; /* device IO registers */
667 ti,nand-ecc-opt = "bch16";
668 ti,elm-id = <&elm>;
669 nand-bus-width = <8>;
670 gpmc,device-width = <1>;
671 gpmc,sync-clk-ps = <0>;
672 gpmc,cs-on-ns = <0>;
673 gpmc,cs-rd-off-ns = <40>;
674 gpmc,cs-wr-off-ns = <40>;
675 gpmc,adv-on-ns = <0>;
676 gpmc,adv-rd-off-ns = <25>;
677 gpmc,adv-wr-off-ns = <25>;
678 gpmc,we-on-ns = <0>;
679 gpmc,we-off-ns = <20>;
680 gpmc,oe-on-ns = <3>;
681 gpmc,oe-off-ns = <30>;
682 gpmc,access-ns = <30>;
683 gpmc,rd-cycle-ns = <40>;
684 gpmc,wr-cycle-ns = <40>;
685 gpmc,wait-pin = <0>;
686 gpmc,bus-turnaround-ns = <0>;
687 gpmc,cycle2cycle-delay-ns = <0>;
688 gpmc,clk-activation-ns = <0>;
689 gpmc,wait-monitoring-ns = <0>;
690 gpmc,wr-access-ns = <40>;
691 gpmc,wr-data-mux-bus-ns = <0>;
692 /* MTD partition table */
693 /* All SPL-* partitions are sized to minimal length
694 * which can be independently programmable. For
695 * NAND flash this is equal to size of erase-block */
696 #address-cells = <1>;
697 #size-cells = <1>;
698 partition@0 {
699 label = "NAND.SPL";
700 reg = <0x00000000 0x00040000>;
701 };
702 partition@1 {
703 label = "NAND.SPL.backup1";
704 reg = <0x00040000 0x00040000>;
705 };
706 partition@2 {
707 label = "NAND.SPL.backup2";
708 reg = <0x00080000 0x00040000>;
709 };
710 partition@3 {
711 label = "NAND.SPL.backup3";
712 reg = <0x000c0000 0x00040000>;
713 };
714 partition@4 {
715 label = "NAND.u-boot-spl-os";
716 reg = <0x00100000 0x00080000>;
717 };
718 partition@5 {
719 label = "NAND.u-boot";
720 reg = <0x00180000 0x00100000>;
721 };
722 partition@6 {
723 label = "NAND.u-boot-env";
724 reg = <0x00280000 0x00040000>;
725 };
726 partition@7 {
727 label = "NAND.u-boot-env.backup1";
728 reg = <0x002c0000 0x00040000>;
729 };
730 partition@8 {
731 label = "NAND.kernel";
732 reg = <0x00300000 0x00700000>;
733 };
734 partition@9 {
735 label = "NAND.file-system";
736 reg = <0x00a00000 0x1f600000>;
737 };
738 };
739};
740
741&dss {
Roger Quadros72f78c62021-08-24 14:07:27 +0300[diff] [blame]742 status = "okay";
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]743
744 pinctrl-names = "default";
745 pinctrl-0 = <&dss_pins>;
746
747 port {
748 dpi_out: endpoint@0 {
749 remote-endpoint = <&lcd_in>;
750 data-lines = <24>;
751 };
752 };
753};
754
755&dcan0 {
756 pinctrl-names = "default";
757 pinctrl-0 = <&dcan0_default>;
758 status = "okay";
759};
760
761&dcan1 {
762 pinctrl-names = "default";
763 pinctrl-0 = <&dcan1_default>;
764 status = "okay";
765};
766
767&vpfe0 {
768 status = "okay";
769 pinctrl-names = "default", "sleep";
770 pinctrl-0 = <&vpfe0_pins_default>;
771 pinctrl-1 = <&vpfe0_pins_sleep>;
772
773 port {
774 vpfe0_ep: endpoint {
775 remote-endpoint = <&ov2659_1>;
776 ti,am437x-vpfe-interface = <0>;
777 bus-width = <8>;
778 hsync-active = <0>;
779 vsync-active = <0>;
780 };
781 };
782};
783
784&vpfe1 {
785 status = "okay";
786 pinctrl-names = "default", "sleep";
787 pinctrl-0 = <&vpfe1_pins_default>;
788 pinctrl-1 = <&vpfe1_pins_sleep>;
789
790 port {
791 vpfe1_ep: endpoint {
792 remote-endpoint = <&ov2659_0>;
793 ti,am437x-vpfe-interface = <0>;
794 bus-width = <8>;
795 hsync-active = <0>;
796 vsync-active = <0>;
797 };
798 };
799};