blob: 455709338cea5d90a51e9db6db78dca7d5e9ee17 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
4 *
Stephen Warrenba4dfef2016-10-21 14:46:47 -06005 * Portions based on U-Boot's rtl8169.c.
6 */
7
8/*
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
12 *
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
20 * field.
21 *
22 * The following configurations are currently supported:
23 * tegra186:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
28 */
Stephen Warrenba4dfef2016-10-21 14:46:47 -060029#include <common.h>
30#include <clk.h>
31#include <dm.h>
32#include <errno.h>
33#include <memalign.h>
34#include <miiphy.h>
35#include <net.h>
36#include <netdev.h>
37#include <phy.h>
38#include <reset.h>
39#include <wait_bit.h>
40#include <asm/gpio.h>
41#include <asm/io.h>
42
43/* Core registers */
44
45#define EQOS_MAC_REGS_BASE 0x000
46struct eqos_mac_regs {
47 uint32_t configuration; /* 0x000 */
48 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
49 uint32_t q0_tx_flow_ctrl; /* 0x070 */
50 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
51 uint32_t rx_flow_ctrl; /* 0x090 */
52 uint32_t unused_094; /* 0x094 */
53 uint32_t txq_prty_map0; /* 0x098 */
54 uint32_t unused_09c; /* 0x09c */
55 uint32_t rxq_ctrl0; /* 0x0a0 */
56 uint32_t unused_0a4; /* 0x0a4 */
57 uint32_t rxq_ctrl2; /* 0x0a8 */
58 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
59 uint32_t us_tic_counter; /* 0x0dc */
60 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
61 uint32_t hw_feature0; /* 0x11c */
62 uint32_t hw_feature1; /* 0x120 */
63 uint32_t hw_feature2; /* 0x124 */
64 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
65 uint32_t mdio_address; /* 0x200 */
66 uint32_t mdio_data; /* 0x204 */
67 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
68 uint32_t address0_high; /* 0x300 */
69 uint32_t address0_low; /* 0x304 */
70};
71
72#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
73#define EQOS_MAC_CONFIGURATION_CST BIT(21)
74#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
75#define EQOS_MAC_CONFIGURATION_WD BIT(19)
76#define EQOS_MAC_CONFIGURATION_JD BIT(17)
77#define EQOS_MAC_CONFIGURATION_JE BIT(16)
78#define EQOS_MAC_CONFIGURATION_PS BIT(15)
79#define EQOS_MAC_CONFIGURATION_FES BIT(14)
80#define EQOS_MAC_CONFIGURATION_DM BIT(13)
81#define EQOS_MAC_CONFIGURATION_TE BIT(1)
82#define EQOS_MAC_CONFIGURATION_RE BIT(0)
83
84#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
85#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
86#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
87
88#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
89
90#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
91#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
92
93#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
94#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
95#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
96#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
Christophe Roullierac2d4ef2019-05-17 15:08:44 +020097#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
Stephen Warrenba4dfef2016-10-21 14:46:47 -060098
99#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
100#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
101
102#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
103#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
104#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
105#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
106
107#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
108#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
109#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
110#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200111#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600112#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
113#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
114#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
115#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
116#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
117#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
118
119#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
120
121#define EQOS_MTL_REGS_BASE 0xd00
122struct eqos_mtl_regs {
123 uint32_t txq0_operation_mode; /* 0xd00 */
124 uint32_t unused_d04; /* 0xd04 */
125 uint32_t txq0_debug; /* 0xd08 */
126 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
127 uint32_t txq0_quantum_weight; /* 0xd18 */
128 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
129 uint32_t rxq0_operation_mode; /* 0xd30 */
130 uint32_t unused_d34; /* 0xd34 */
131 uint32_t rxq0_debug; /* 0xd38 */
132};
133
134#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
135#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
136#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
137#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
138#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
139#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
140#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
141
142#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
143#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
144#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
145
146#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
147#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
148#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
149#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
150#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
151#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
152#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
153#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
154
155#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
156#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
157#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
158#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
159
160#define EQOS_DMA_REGS_BASE 0x1000
161struct eqos_dma_regs {
162 uint32_t mode; /* 0x1000 */
163 uint32_t sysbus_mode; /* 0x1004 */
164 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
165 uint32_t ch0_control; /* 0x1100 */
166 uint32_t ch0_tx_control; /* 0x1104 */
167 uint32_t ch0_rx_control; /* 0x1108 */
168 uint32_t unused_110c; /* 0x110c */
169 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
170 uint32_t ch0_txdesc_list_address; /* 0x1114 */
171 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
172 uint32_t ch0_rxdesc_list_address; /* 0x111c */
173 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
174 uint32_t unused_1124; /* 0x1124 */
175 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
176 uint32_t ch0_txdesc_ring_length; /* 0x112c */
177 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
178};
179
180#define EQOS_DMA_MODE_SWR BIT(0)
181
182#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
183#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
184#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
185#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
186#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
187#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
188
189#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
190
191#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
192#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
193#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
194#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
195
196#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
197#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
198#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
199#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
200#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
201
202/* These registers are Tegra186-specific */
203#define EQOS_TEGRA186_REGS_BASE 0x8800
204struct eqos_tegra186_regs {
205 uint32_t sdmemcomppadctrl; /* 0x8800 */
206 uint32_t auto_cal_config; /* 0x8804 */
207 uint32_t unused_8808; /* 0x8808 */
208 uint32_t auto_cal_status; /* 0x880c */
209};
210
211#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
212
213#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
214#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
215
216#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
217
218/* Descriptors */
219
220#define EQOS_DESCRIPTOR_WORDS 4
221#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
222/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
223#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
224#define EQOS_DESCRIPTORS_TX 4
225#define EQOS_DESCRIPTORS_RX 4
226#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
227#define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
228 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
229#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
230#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
231#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
232
233/*
234 * Warn if the cache-line size is larger than the descriptor size. In such
235 * cases the driver will likely fail because the CPU needs to flush the cache
236 * when requeuing RX buffers, therefore descriptors written by the hardware
237 * may be discarded. Architectures with full IO coherence, such as x86, do not
238 * experience this issue, and hence are excluded from this condition.
239 *
240 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
241 * the driver to allocate descriptors from a pool of non-cached memory.
242 */
243#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
244#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
Trevor Woerner10015022019-05-03 09:41:00 -0400245 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600246#warning Cache line size is larger than descriptor size
247#endif
248#endif
249
250struct eqos_desc {
251 u32 des0;
252 u32 des1;
253 u32 des2;
254 u32 des3;
255};
256
257#define EQOS_DESC3_OWN BIT(31)
258#define EQOS_DESC3_FD BIT(29)
259#define EQOS_DESC3_LD BIT(28)
260#define EQOS_DESC3_BUF1V BIT(24)
261
262struct eqos_config {
263 bool reg_access_always_ok;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200264 int mdio_wait;
265 int swr_wait;
266 int config_mac;
267 int config_mac_mdio;
268 phy_interface_t (*interface)(struct udevice *dev);
269 struct eqos_ops *ops;
270};
271
272struct eqos_ops {
273 void (*eqos_inval_desc)(void *desc);
274 void (*eqos_flush_desc)(void *desc);
275 void (*eqos_inval_buffer)(void *buf, size_t size);
276 void (*eqos_flush_buffer)(void *buf, size_t size);
277 int (*eqos_probe_resources)(struct udevice *dev);
278 int (*eqos_remove_resources)(struct udevice *dev);
279 int (*eqos_stop_resets)(struct udevice *dev);
280 int (*eqos_start_resets)(struct udevice *dev);
281 void (*eqos_stop_clks)(struct udevice *dev);
282 int (*eqos_start_clks)(struct udevice *dev);
283 int (*eqos_calibrate_pads)(struct udevice *dev);
284 int (*eqos_disable_calibration)(struct udevice *dev);
285 int (*eqos_set_tx_clk_speed)(struct udevice *dev);
286 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600287};
288
289struct eqos_priv {
290 struct udevice *dev;
291 const struct eqos_config *config;
292 fdt_addr_t regs;
293 struct eqos_mac_regs *mac_regs;
294 struct eqos_mtl_regs *mtl_regs;
295 struct eqos_dma_regs *dma_regs;
296 struct eqos_tegra186_regs *tegra186_regs;
297 struct reset_ctl reset_ctl;
298 struct gpio_desc phy_reset_gpio;
299 struct clk clk_master_bus;
300 struct clk clk_rx;
301 struct clk clk_ptp_ref;
302 struct clk clk_tx;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200303 struct clk clk_ck;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600304 struct clk clk_slave_bus;
305 struct mii_dev *mii;
306 struct phy_device *phy;
307 void *descs;
308 struct eqos_desc *tx_descs;
309 struct eqos_desc *rx_descs;
310 int tx_desc_idx, rx_desc_idx;
311 void *tx_dma_buf;
312 void *rx_dma_buf;
313 void *rx_pkt;
314 bool started;
315 bool reg_access_ok;
316};
317
318/*
319 * TX and RX descriptors are 16 bytes. This causes problems with the cache
320 * maintenance on CPUs where the cache-line size exceeds the size of these
321 * descriptors. What will happen is that when the driver receives a packet
322 * it will be immediately requeued for the hardware to reuse. The CPU will
323 * therefore need to flush the cache-line containing the descriptor, which
324 * will cause all other descriptors in the same cache-line to be flushed
325 * along with it. If one of those descriptors had been written to by the
326 * device those changes (and the associated packet) will be lost.
327 *
328 * To work around this, we make use of non-cached memory if available. If
329 * descriptors are mapped uncached there's no need to manually flush them
330 * or invalidate them.
331 *
332 * Note that this only applies to descriptors. The packet data buffers do
333 * not have the same constraints since they are 1536 bytes large, so they
334 * are unlikely to share cache-lines.
335 */
336static void *eqos_alloc_descs(unsigned int num)
337{
338#ifdef CONFIG_SYS_NONCACHED_MEMORY
339 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
340 EQOS_DESCRIPTOR_ALIGN);
341#else
342 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
343#endif
344}
345
346static void eqos_free_descs(void *descs)
347{
348#ifdef CONFIG_SYS_NONCACHED_MEMORY
349 /* FIXME: noncached_alloc() has no opposite */
350#else
351 free(descs);
352#endif
353}
354
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200355static void eqos_inval_desc_tegra186(void *desc)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600356{
357#ifndef CONFIG_SYS_NONCACHED_MEMORY
358 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
359 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
360 ARCH_DMA_MINALIGN);
361
362 invalidate_dcache_range(start, end);
363#endif
364}
365
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200366static void eqos_inval_desc_stm32(void *desc)
367{
368#ifndef CONFIG_SYS_NONCACHED_MEMORY
369 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
370 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
371 ARCH_DMA_MINALIGN);
372
373 invalidate_dcache_range(start, end);
374#endif
375}
376
377static void eqos_flush_desc_tegra186(void *desc)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600378{
379#ifndef CONFIG_SYS_NONCACHED_MEMORY
380 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
381#endif
382}
383
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200384static void eqos_flush_desc_stm32(void *desc)
385{
386#ifndef CONFIG_SYS_NONCACHED_MEMORY
387 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
388 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
389 ARCH_DMA_MINALIGN);
390
391 flush_dcache_range(start, end);
392#endif
393}
394
395static void eqos_inval_buffer_tegra186(void *buf, size_t size)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600396{
397 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
398 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
399
400 invalidate_dcache_range(start, end);
401}
402
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200403static void eqos_inval_buffer_stm32(void *buf, size_t size)
404{
405 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
406 unsigned long end = roundup((unsigned long)buf + size,
407 ARCH_DMA_MINALIGN);
408
409 invalidate_dcache_range(start, end);
410}
411
412static void eqos_flush_buffer_tegra186(void *buf, size_t size)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600413{
414 flush_cache((unsigned long)buf, size);
415}
416
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200417static void eqos_flush_buffer_stm32(void *buf, size_t size)
418{
419 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
420 unsigned long end = roundup((unsigned long)buf + size,
421 ARCH_DMA_MINALIGN);
422
423 flush_dcache_range(start, end);
424}
425
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600426static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
427{
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100428 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
429 EQOS_MAC_MDIO_ADDRESS_GB, false,
430 1000000, true);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600431}
432
433static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
434 int mdio_reg)
435{
436 struct eqos_priv *eqos = bus->priv;
437 u32 val;
438 int ret;
439
440 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
441 mdio_reg);
442
443 ret = eqos_mdio_wait_idle(eqos);
444 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900445 pr_err("MDIO not idle at entry");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600446 return ret;
447 }
448
449 val = readl(&eqos->mac_regs->mdio_address);
450 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
451 EQOS_MAC_MDIO_ADDRESS_C45E;
452 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
453 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200454 (eqos->config->config_mac_mdio <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600455 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
456 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
457 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
458 EQOS_MAC_MDIO_ADDRESS_GB;
459 writel(val, &eqos->mac_regs->mdio_address);
460
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200461 udelay(eqos->config->mdio_wait);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600462
463 ret = eqos_mdio_wait_idle(eqos);
464 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900465 pr_err("MDIO read didn't complete");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600466 return ret;
467 }
468
469 val = readl(&eqos->mac_regs->mdio_data);
470 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
471
472 debug("%s: val=%x\n", __func__, val);
473
474 return val;
475}
476
477static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
478 int mdio_reg, u16 mdio_val)
479{
480 struct eqos_priv *eqos = bus->priv;
481 u32 val;
482 int ret;
483
484 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
485 mdio_addr, mdio_reg, mdio_val);
486
487 ret = eqos_mdio_wait_idle(eqos);
488 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900489 pr_err("MDIO not idle at entry");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600490 return ret;
491 }
492
493 writel(mdio_val, &eqos->mac_regs->mdio_data);
494
495 val = readl(&eqos->mac_regs->mdio_address);
496 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
497 EQOS_MAC_MDIO_ADDRESS_C45E;
498 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
499 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200500 (eqos->config->config_mac_mdio <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600501 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
502 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
503 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
504 EQOS_MAC_MDIO_ADDRESS_GB;
505 writel(val, &eqos->mac_regs->mdio_address);
506
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200507 udelay(eqos->config->mdio_wait);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600508
509 ret = eqos_mdio_wait_idle(eqos);
510 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900511 pr_err("MDIO read didn't complete");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600512 return ret;
513 }
514
515 return 0;
516}
517
518static int eqos_start_clks_tegra186(struct udevice *dev)
519{
520 struct eqos_priv *eqos = dev_get_priv(dev);
521 int ret;
522
523 debug("%s(dev=%p):\n", __func__, dev);
524
525 ret = clk_enable(&eqos->clk_slave_bus);
526 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900527 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600528 goto err;
529 }
530
531 ret = clk_enable(&eqos->clk_master_bus);
532 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900533 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600534 goto err_disable_clk_slave_bus;
535 }
536
537 ret = clk_enable(&eqos->clk_rx);
538 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900539 pr_err("clk_enable(clk_rx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600540 goto err_disable_clk_master_bus;
541 }
542
543 ret = clk_enable(&eqos->clk_ptp_ref);
544 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900545 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600546 goto err_disable_clk_rx;
547 }
548
549 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
550 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900551 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600552 goto err_disable_clk_ptp_ref;
553 }
554
555 ret = clk_enable(&eqos->clk_tx);
556 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900557 pr_err("clk_enable(clk_tx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600558 goto err_disable_clk_ptp_ref;
559 }
560
561 debug("%s: OK\n", __func__);
562 return 0;
563
564err_disable_clk_ptp_ref:
565 clk_disable(&eqos->clk_ptp_ref);
566err_disable_clk_rx:
567 clk_disable(&eqos->clk_rx);
568err_disable_clk_master_bus:
569 clk_disable(&eqos->clk_master_bus);
570err_disable_clk_slave_bus:
571 clk_disable(&eqos->clk_slave_bus);
572err:
573 debug("%s: FAILED: %d\n", __func__, ret);
574 return ret;
575}
576
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200577static int eqos_start_clks_stm32(struct udevice *dev)
578{
579 struct eqos_priv *eqos = dev_get_priv(dev);
580 int ret;
581
582 debug("%s(dev=%p):\n", __func__, dev);
583
584 ret = clk_enable(&eqos->clk_master_bus);
585 if (ret < 0) {
586 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
587 goto err;
588 }
589
590 ret = clk_enable(&eqos->clk_rx);
591 if (ret < 0) {
592 pr_err("clk_enable(clk_rx) failed: %d", ret);
593 goto err_disable_clk_master_bus;
594 }
595
596 ret = clk_enable(&eqos->clk_tx);
597 if (ret < 0) {
598 pr_err("clk_enable(clk_tx) failed: %d", ret);
599 goto err_disable_clk_rx;
600 }
601
602 if (clk_valid(&eqos->clk_ck)) {
603 ret = clk_enable(&eqos->clk_ck);
604 if (ret < 0) {
605 pr_err("clk_enable(clk_ck) failed: %d", ret);
606 goto err_disable_clk_tx;
607 }
608 }
609
610 debug("%s: OK\n", __func__);
611 return 0;
612
613err_disable_clk_tx:
614 clk_disable(&eqos->clk_tx);
615err_disable_clk_rx:
616 clk_disable(&eqos->clk_rx);
617err_disable_clk_master_bus:
618 clk_disable(&eqos->clk_master_bus);
619err:
620 debug("%s: FAILED: %d\n", __func__, ret);
621 return ret;
622}
623
Patrick Delaunay50d86e52019-08-01 11:29:02 +0200624static void eqos_stop_clks_tegra186(struct udevice *dev)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600625{
626 struct eqos_priv *eqos = dev_get_priv(dev);
627
628 debug("%s(dev=%p):\n", __func__, dev);
629
630 clk_disable(&eqos->clk_tx);
631 clk_disable(&eqos->clk_ptp_ref);
632 clk_disable(&eqos->clk_rx);
633 clk_disable(&eqos->clk_master_bus);
634 clk_disable(&eqos->clk_slave_bus);
635
636 debug("%s: OK\n", __func__);
637}
638
Patrick Delaunay50d86e52019-08-01 11:29:02 +0200639static void eqos_stop_clks_stm32(struct udevice *dev)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200640{
641 struct eqos_priv *eqos = dev_get_priv(dev);
642
643 debug("%s(dev=%p):\n", __func__, dev);
644
645 clk_disable(&eqos->clk_tx);
646 clk_disable(&eqos->clk_rx);
647 clk_disable(&eqos->clk_master_bus);
648 if (clk_valid(&eqos->clk_ck))
649 clk_disable(&eqos->clk_ck);
650
651 debug("%s: OK\n", __func__);
652}
653
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600654static int eqos_start_resets_tegra186(struct udevice *dev)
655{
656 struct eqos_priv *eqos = dev_get_priv(dev);
657 int ret;
658
659 debug("%s(dev=%p):\n", __func__, dev);
660
661 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
662 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900663 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600664 return ret;
665 }
666
667 udelay(2);
668
669 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
670 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900671 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600672 return ret;
673 }
674
675 ret = reset_assert(&eqos->reset_ctl);
676 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900677 pr_err("reset_assert() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600678 return ret;
679 }
680
681 udelay(2);
682
683 ret = reset_deassert(&eqos->reset_ctl);
684 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900685 pr_err("reset_deassert() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600686 return ret;
687 }
688
689 debug("%s: OK\n", __func__);
690 return 0;
691}
692
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200693static int eqos_start_resets_stm32(struct udevice *dev)
694{
695 return 0;
696}
697
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600698static int eqos_stop_resets_tegra186(struct udevice *dev)
699{
700 struct eqos_priv *eqos = dev_get_priv(dev);
701
702 reset_assert(&eqos->reset_ctl);
703 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
704
705 return 0;
706}
707
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200708static int eqos_stop_resets_stm32(struct udevice *dev)
709{
710 return 0;
711}
712
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600713static int eqos_calibrate_pads_tegra186(struct udevice *dev)
714{
715 struct eqos_priv *eqos = dev_get_priv(dev);
716 int ret;
717
718 debug("%s(dev=%p):\n", __func__, dev);
719
720 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
721 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
722
723 udelay(1);
724
725 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
726 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
727
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100728 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
729 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600730 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900731 pr_err("calibrate didn't start");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600732 goto failed;
733 }
734
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100735 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
736 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600737 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900738 pr_err("calibrate didn't finish");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600739 goto failed;
740 }
741
742 ret = 0;
743
744failed:
745 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
746 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
747
748 debug("%s: returns %d\n", __func__, ret);
749
750 return ret;
751}
752
753static int eqos_disable_calibration_tegra186(struct udevice *dev)
754{
755 struct eqos_priv *eqos = dev_get_priv(dev);
756
757 debug("%s(dev=%p):\n", __func__, dev);
758
759 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
760 EQOS_AUTO_CAL_CONFIG_ENABLE);
761
762 return 0;
763}
764
765static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
766{
767 struct eqos_priv *eqos = dev_get_priv(dev);
768
769 return clk_get_rate(&eqos->clk_slave_bus);
770}
771
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200772static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
773{
774 struct eqos_priv *eqos = dev_get_priv(dev);
775
776 return clk_get_rate(&eqos->clk_master_bus);
777}
778
779static int eqos_calibrate_pads_stm32(struct udevice *dev)
780{
781 return 0;
782}
783
784static int eqos_disable_calibration_stm32(struct udevice *dev)
785{
786 return 0;
787}
788
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600789static int eqos_set_full_duplex(struct udevice *dev)
790{
791 struct eqos_priv *eqos = dev_get_priv(dev);
792
793 debug("%s(dev=%p):\n", __func__, dev);
794
795 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
796
797 return 0;
798}
799
800static int eqos_set_half_duplex(struct udevice *dev)
801{
802 struct eqos_priv *eqos = dev_get_priv(dev);
803
804 debug("%s(dev=%p):\n", __func__, dev);
805
806 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
807
808 /* WAR: Flush TX queue when switching to half-duplex */
809 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
810 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
811
812 return 0;
813}
814
815static int eqos_set_gmii_speed(struct udevice *dev)
816{
817 struct eqos_priv *eqos = dev_get_priv(dev);
818
819 debug("%s(dev=%p):\n", __func__, dev);
820
821 clrbits_le32(&eqos->mac_regs->configuration,
822 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
823
824 return 0;
825}
826
827static int eqos_set_mii_speed_100(struct udevice *dev)
828{
829 struct eqos_priv *eqos = dev_get_priv(dev);
830
831 debug("%s(dev=%p):\n", __func__, dev);
832
833 setbits_le32(&eqos->mac_regs->configuration,
834 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
835
836 return 0;
837}
838
839static int eqos_set_mii_speed_10(struct udevice *dev)
840{
841 struct eqos_priv *eqos = dev_get_priv(dev);
842
843 debug("%s(dev=%p):\n", __func__, dev);
844
845 clrsetbits_le32(&eqos->mac_regs->configuration,
846 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
847
848 return 0;
849}
850
851static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
852{
853 struct eqos_priv *eqos = dev_get_priv(dev);
854 ulong rate;
855 int ret;
856
857 debug("%s(dev=%p):\n", __func__, dev);
858
859 switch (eqos->phy->speed) {
860 case SPEED_1000:
861 rate = 125 * 1000 * 1000;
862 break;
863 case SPEED_100:
864 rate = 25 * 1000 * 1000;
865 break;
866 case SPEED_10:
867 rate = 2.5 * 1000 * 1000;
868 break;
869 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900870 pr_err("invalid speed %d", eqos->phy->speed);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600871 return -EINVAL;
872 }
873
874 ret = clk_set_rate(&eqos->clk_tx, rate);
875 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900876 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600877 return ret;
878 }
879
880 return 0;
881}
882
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200883static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
884{
885 return 0;
886}
887
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600888static int eqos_adjust_link(struct udevice *dev)
889{
890 struct eqos_priv *eqos = dev_get_priv(dev);
891 int ret;
892 bool en_calibration;
893
894 debug("%s(dev=%p):\n", __func__, dev);
895
896 if (eqos->phy->duplex)
897 ret = eqos_set_full_duplex(dev);
898 else
899 ret = eqos_set_half_duplex(dev);
900 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900901 pr_err("eqos_set_*_duplex() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600902 return ret;
903 }
904
905 switch (eqos->phy->speed) {
906 case SPEED_1000:
907 en_calibration = true;
908 ret = eqos_set_gmii_speed(dev);
909 break;
910 case SPEED_100:
911 en_calibration = true;
912 ret = eqos_set_mii_speed_100(dev);
913 break;
914 case SPEED_10:
915 en_calibration = false;
916 ret = eqos_set_mii_speed_10(dev);
917 break;
918 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900919 pr_err("invalid speed %d", eqos->phy->speed);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600920 return -EINVAL;
921 }
922 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900923 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600924 return ret;
925 }
926
927 if (en_calibration) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200928 ret = eqos->config->ops->eqos_calibrate_pads(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600929 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200930 pr_err("eqos_calibrate_pads() failed: %d",
931 ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600932 return ret;
933 }
934 } else {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200935 ret = eqos->config->ops->eqos_disable_calibration(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600936 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200937 pr_err("eqos_disable_calibration() failed: %d",
938 ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600939 return ret;
940 }
941 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200942 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600943 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200944 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600945 return ret;
946 }
947
948 return 0;
949}
950
951static int eqos_write_hwaddr(struct udevice *dev)
952{
953 struct eth_pdata *plat = dev_get_platdata(dev);
954 struct eqos_priv *eqos = dev_get_priv(dev);
955 uint32_t val;
956
957 /*
958 * This function may be called before start() or after stop(). At that
959 * time, on at least some configurations of the EQoS HW, all clocks to
960 * the EQoS HW block will be stopped, and a reset signal applied. If
961 * any register access is attempted in this state, bus timeouts or CPU
962 * hangs may occur. This check prevents that.
963 *
964 * A simple solution to this problem would be to not implement
965 * write_hwaddr(), since start() always writes the MAC address into HW
966 * anyway. However, it is desirable to implement write_hwaddr() to
967 * support the case of SW that runs subsequent to U-Boot which expects
968 * the MAC address to already be programmed into the EQoS registers,
969 * which must happen irrespective of whether the U-Boot user (or
970 * scripts) actually made use of the EQoS device, and hence
971 * irrespective of whether start() was ever called.
972 *
973 * Note that this requirement by subsequent SW is not valid for
974 * Tegra186, and is likely not valid for any non-PCI instantiation of
975 * the EQoS HW block. This function is implemented solely as
976 * future-proofing with the expectation the driver will eventually be
977 * ported to some system where the expectation above is true.
978 */
979 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
980 return 0;
981
982 /* Update the MAC address */
983 val = (plat->enetaddr[5] << 8) |
984 (plat->enetaddr[4]);
985 writel(val, &eqos->mac_regs->address0_high);
986 val = (plat->enetaddr[3] << 24) |
987 (plat->enetaddr[2] << 16) |
988 (plat->enetaddr[1] << 8) |
989 (plat->enetaddr[0]);
990 writel(val, &eqos->mac_regs->address0_low);
991
992 return 0;
993}
994
995static int eqos_start(struct udevice *dev)
996{
997 struct eqos_priv *eqos = dev_get_priv(dev);
998 int ret, i;
999 ulong rate;
1000 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1001 ulong last_rx_desc;
1002
1003 debug("%s(dev=%p):\n", __func__, dev);
1004
1005 eqos->tx_desc_idx = 0;
1006 eqos->rx_desc_idx = 0;
1007
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001008 ret = eqos->config->ops->eqos_start_clks(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001009 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001010 pr_err("eqos_start_clks() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001011 goto err;
1012 }
1013
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001014 ret = eqos->config->ops->eqos_start_resets(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001015 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001016 pr_err("eqos_start_resets() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001017 goto err_stop_clks;
1018 }
1019
1020 udelay(10);
1021
1022 eqos->reg_access_ok = true;
1023
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +01001024 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001025 EQOS_DMA_MODE_SWR, false,
1026 eqos->config->swr_wait, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001027 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001028 pr_err("EQOS_DMA_MODE_SWR stuck");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001029 goto err_stop_resets;
1030 }
1031
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001032 ret = eqos->config->ops->eqos_calibrate_pads(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001033 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001034 pr_err("eqos_calibrate_pads() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001035 goto err_stop_resets;
1036 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001037 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001038
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001039 val = (rate / 1000000) - 1;
1040 writel(val, &eqos->mac_regs->us_tic_counter);
1041
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001042 /*
1043 * if PHY was already connected and configured,
1044 * don't need to reconnect/reconfigure again
1045 */
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001046 if (!eqos->phy) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001047 eqos->phy = phy_connect(eqos->mii, 0, dev,
1048 eqos->config->interface(dev));
1049 if (!eqos->phy) {
1050 pr_err("phy_connect() failed");
1051 goto err_stop_resets;
1052 }
1053 ret = phy_config(eqos->phy);
1054 if (ret < 0) {
1055 pr_err("phy_config() failed: %d", ret);
1056 goto err_shutdown_phy;
1057 }
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001058 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001059
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001060 ret = phy_startup(eqos->phy);
1061 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001062 pr_err("phy_startup() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001063 goto err_shutdown_phy;
1064 }
1065
1066 if (!eqos->phy->link) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001067 pr_err("No link");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001068 goto err_shutdown_phy;
1069 }
1070
1071 ret = eqos_adjust_link(dev);
1072 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001073 pr_err("eqos_adjust_link() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001074 goto err_shutdown_phy;
1075 }
1076
1077 /* Configure MTL */
1078
1079 /* Enable Store and Forward mode for TX */
1080 /* Program Tx operating mode */
1081 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1082 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1083 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1084 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1085
1086 /* Transmit Queue weight */
1087 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1088
1089 /* Enable Store and Forward mode for RX, since no jumbo frame */
1090 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1091 EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
1092
1093 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1094 val = readl(&eqos->mac_regs->hw_feature1);
1095 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1096 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1097 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1098 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1099
1100 /*
1101 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1102 * r/tqs is encoded as (n / 256) - 1.
1103 */
1104 tqs = (128 << tx_fifo_sz) / 256 - 1;
1105 rqs = (128 << rx_fifo_sz) / 256 - 1;
1106
1107 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1108 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1109 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1110 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1111 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1112 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1113 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1114 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1115
1116 /* Flow control used only if each channel gets 4KB or more FIFO */
1117 if (rqs >= ((4096 / 256) - 1)) {
1118 u32 rfd, rfa;
1119
1120 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1121 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1122
1123 /*
1124 * Set Threshold for Activating Flow Contol space for min 2
1125 * frames ie, (1500 * 1) = 1500 bytes.
1126 *
1127 * Set Threshold for Deactivating Flow Contol for space of
1128 * min 1 frame (frame size 1500bytes) in receive fifo
1129 */
1130 if (rqs == ((4096 / 256) - 1)) {
1131 /*
1132 * This violates the above formula because of FIFO size
1133 * limit therefore overflow may occur inspite of this.
1134 */
1135 rfd = 0x3; /* Full-3K */
1136 rfa = 0x1; /* Full-1.5K */
1137 } else if (rqs == ((8192 / 256) - 1)) {
1138 rfd = 0x6; /* Full-4K */
1139 rfa = 0xa; /* Full-6K */
1140 } else if (rqs == ((16384 / 256) - 1)) {
1141 rfd = 0x6; /* Full-4K */
1142 rfa = 0x12; /* Full-10K */
1143 } else {
1144 rfd = 0x6; /* Full-4K */
1145 rfa = 0x1E; /* Full-16K */
1146 }
1147
1148 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1149 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1150 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1151 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1152 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1153 (rfd <<
1154 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1155 (rfa <<
1156 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1157 }
1158
1159 /* Configure MAC */
1160
1161 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1162 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1163 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001164 eqos->config->config_mac <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001165 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1166
1167 /* Set TX flow control parameters */
1168 /* Set Pause Time */
1169 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1170 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1171 /* Assign priority for TX flow control */
1172 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1173 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1174 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1175 /* Assign priority for RX flow control */
1176 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1177 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1178 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1179 /* Enable flow control */
1180 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1181 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1182 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1183 EQOS_MAC_RX_FLOW_CTRL_RFE);
1184
1185 clrsetbits_le32(&eqos->mac_regs->configuration,
1186 EQOS_MAC_CONFIGURATION_GPSLCE |
1187 EQOS_MAC_CONFIGURATION_WD |
1188 EQOS_MAC_CONFIGURATION_JD |
1189 EQOS_MAC_CONFIGURATION_JE,
1190 EQOS_MAC_CONFIGURATION_CST |
1191 EQOS_MAC_CONFIGURATION_ACS);
1192
1193 eqos_write_hwaddr(dev);
1194
1195 /* Configure DMA */
1196
1197 /* Enable OSP mode */
1198 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1199 EQOS_DMA_CH0_TX_CONTROL_OSP);
1200
1201 /* RX buffer size. Must be a multiple of bus width */
1202 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1203 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1204 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1205 EQOS_MAX_PACKET_SIZE <<
1206 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1207
1208 setbits_le32(&eqos->dma_regs->ch0_control,
1209 EQOS_DMA_CH0_CONTROL_PBLX8);
1210
1211 /*
1212 * Burst length must be < 1/2 FIFO size.
1213 * FIFO size in tqs is encoded as (n / 256) - 1.
1214 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1215 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1216 */
1217 pbl = tqs + 1;
1218 if (pbl > 32)
1219 pbl = 32;
1220 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1221 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1222 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1223 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1224
1225 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1226 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1227 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1228 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1229
1230 /* DMA performance configuration */
1231 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1232 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1233 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1234 writel(val, &eqos->dma_regs->sysbus_mode);
1235
1236 /* Set up descriptors */
1237
1238 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
1239 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1240 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
1241 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1242 (i * EQOS_MAX_PACKET_SIZE));
1243 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1244 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001245 eqos->config->ops->eqos_flush_desc(eqos->descs);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001246
1247 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1248 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
1249 writel(EQOS_DESCRIPTORS_TX - 1,
1250 &eqos->dma_regs->ch0_txdesc_ring_length);
1251
1252 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1253 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
1254 writel(EQOS_DESCRIPTORS_RX - 1,
1255 &eqos->dma_regs->ch0_rxdesc_ring_length);
1256
1257 /* Enable everything */
1258
1259 setbits_le32(&eqos->mac_regs->configuration,
1260 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1261
1262 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1263 EQOS_DMA_CH0_TX_CONTROL_ST);
1264 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1265 EQOS_DMA_CH0_RX_CONTROL_SR);
1266
1267 /* TX tail pointer not written until we need to TX a packet */
1268 /*
1269 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1270 * first descriptor, implying all descriptors were available. However,
1271 * that's not distinguishable from none of the descriptors being
1272 * available.
1273 */
1274 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
1275 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1276
1277 eqos->started = true;
1278
1279 debug("%s: OK\n", __func__);
1280 return 0;
1281
1282err_shutdown_phy:
1283 phy_shutdown(eqos->phy);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001284err_stop_resets:
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001285 eqos->config->ops->eqos_stop_resets(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001286err_stop_clks:
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001287 eqos->config->ops->eqos_stop_clks(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001288err:
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001289 pr_err("FAILED: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001290 return ret;
1291}
1292
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001293static void eqos_stop(struct udevice *dev)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001294{
1295 struct eqos_priv *eqos = dev_get_priv(dev);
1296 int i;
1297
1298 debug("%s(dev=%p):\n", __func__, dev);
1299
1300 if (!eqos->started)
1301 return;
1302 eqos->started = false;
1303 eqos->reg_access_ok = false;
1304
1305 /* Disable TX DMA */
1306 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1307 EQOS_DMA_CH0_TX_CONTROL_ST);
1308
1309 /* Wait for TX all packets to drain out of MTL */
1310 for (i = 0; i < 1000000; i++) {
1311 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1312 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1313 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1314 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1315 if ((trcsts != 1) && (!txqsts))
1316 break;
1317 }
1318
1319 /* Turn off MAC TX and RX */
1320 clrbits_le32(&eqos->mac_regs->configuration,
1321 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1322
1323 /* Wait for all RX packets to drain out of MTL */
1324 for (i = 0; i < 1000000; i++) {
1325 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1326 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1327 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1328 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1329 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1330 if ((!prxq) && (!rxqsts))
1331 break;
1332 }
1333
1334 /* Turn off RX DMA */
1335 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1336 EQOS_DMA_CH0_RX_CONTROL_SR);
1337
1338 if (eqos->phy) {
1339 phy_shutdown(eqos->phy);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001340 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001341 eqos->config->ops->eqos_stop_resets(dev);
1342 eqos->config->ops->eqos_stop_clks(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001343
1344 debug("%s: OK\n", __func__);
1345}
1346
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001347static int eqos_send(struct udevice *dev, void *packet, int length)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001348{
1349 struct eqos_priv *eqos = dev_get_priv(dev);
1350 struct eqos_desc *tx_desc;
1351 int i;
1352
1353 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1354 length);
1355
1356 memcpy(eqos->tx_dma_buf, packet, length);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001357 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001358
1359 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
1360 eqos->tx_desc_idx++;
1361 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1362
1363 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1364 tx_desc->des1 = 0;
1365 tx_desc->des2 = length;
1366 /*
1367 * Make sure that if HW sees the _OWN write below, it will see all the
1368 * writes to the rest of the descriptor too.
1369 */
1370 mb();
1371 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001372 eqos->config->ops->eqos_flush_desc(tx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001373
1374 writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
1375
1376 for (i = 0; i < 1000000; i++) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001377 eqos->config->ops->eqos_inval_desc(tx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001378 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1379 return 0;
1380 udelay(1);
1381 }
1382
1383 debug("%s: TX timeout\n", __func__);
1384
1385 return -ETIMEDOUT;
1386}
1387
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001388static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001389{
1390 struct eqos_priv *eqos = dev_get_priv(dev);
1391 struct eqos_desc *rx_desc;
1392 int length;
1393
1394 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1395
1396 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1397 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1398 debug("%s: RX packet not available\n", __func__);
1399 return -EAGAIN;
1400 }
1401
1402 *packetp = eqos->rx_dma_buf +
1403 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1404 length = rx_desc->des3 & 0x7fff;
1405 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1406
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001407 eqos->config->ops->eqos_inval_buffer(*packetp, length);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001408
1409 return length;
1410}
1411
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001412static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001413{
1414 struct eqos_priv *eqos = dev_get_priv(dev);
1415 uchar *packet_expected;
1416 struct eqos_desc *rx_desc;
1417
1418 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1419
1420 packet_expected = eqos->rx_dma_buf +
1421 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1422 if (packet != packet_expected) {
1423 debug("%s: Unexpected packet (expected %p)\n", __func__,
1424 packet_expected);
1425 return -EINVAL;
1426 }
1427
1428 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1429 rx_desc->des0 = (u32)(ulong)packet;
1430 rx_desc->des1 = 0;
1431 rx_desc->des2 = 0;
1432 /*
1433 * Make sure that if HW sees the _OWN write below, it will see all the
1434 * writes to the rest of the descriptor too.
1435 */
1436 mb();
1437 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001438 eqos->config->ops->eqos_flush_desc(rx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001439
1440 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1441
1442 eqos->rx_desc_idx++;
1443 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1444
1445 return 0;
1446}
1447
1448static int eqos_probe_resources_core(struct udevice *dev)
1449{
1450 struct eqos_priv *eqos = dev_get_priv(dev);
1451 int ret;
1452
1453 debug("%s(dev=%p):\n", __func__, dev);
1454
1455 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
1456 EQOS_DESCRIPTORS_RX);
1457 if (!eqos->descs) {
1458 debug("%s: eqos_alloc_descs() failed\n", __func__);
1459 ret = -ENOMEM;
1460 goto err;
1461 }
1462 eqos->tx_descs = (struct eqos_desc *)eqos->descs;
1463 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
1464 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
1465 eqos->rx_descs);
1466
1467 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1468 if (!eqos->tx_dma_buf) {
1469 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1470 ret = -ENOMEM;
1471 goto err_free_descs;
1472 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001473 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001474
1475 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1476 if (!eqos->rx_dma_buf) {
1477 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1478 ret = -ENOMEM;
1479 goto err_free_tx_dma_buf;
1480 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001481 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001482
1483 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1484 if (!eqos->rx_pkt) {
1485 debug("%s: malloc(rx_pkt) failed\n", __func__);
1486 ret = -ENOMEM;
1487 goto err_free_rx_dma_buf;
1488 }
1489 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1490
1491 debug("%s: OK\n", __func__);
1492 return 0;
1493
1494err_free_rx_dma_buf:
1495 free(eqos->rx_dma_buf);
1496err_free_tx_dma_buf:
1497 free(eqos->tx_dma_buf);
1498err_free_descs:
1499 eqos_free_descs(eqos->descs);
1500err:
1501
1502 debug("%s: returns %d\n", __func__, ret);
1503 return ret;
1504}
1505
1506static int eqos_remove_resources_core(struct udevice *dev)
1507{
1508 struct eqos_priv *eqos = dev_get_priv(dev);
1509
1510 debug("%s(dev=%p):\n", __func__, dev);
1511
1512 free(eqos->rx_pkt);
1513 free(eqos->rx_dma_buf);
1514 free(eqos->tx_dma_buf);
1515 eqos_free_descs(eqos->descs);
1516
1517 debug("%s: OK\n", __func__);
1518 return 0;
1519}
1520
1521static int eqos_probe_resources_tegra186(struct udevice *dev)
1522{
1523 struct eqos_priv *eqos = dev_get_priv(dev);
1524 int ret;
1525
1526 debug("%s(dev=%p):\n", __func__, dev);
1527
1528 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1529 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001530 pr_err("reset_get_by_name(rst) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001531 return ret;
1532 }
1533
1534 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1535 &eqos->phy_reset_gpio,
1536 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1537 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001538 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001539 goto err_free_reset_eqos;
1540 }
1541
1542 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1543 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001544 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001545 goto err_free_gpio_phy_reset;
1546 }
1547
1548 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1549 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001550 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001551 goto err_free_clk_slave_bus;
1552 }
1553
1554 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1555 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001556 pr_err("clk_get_by_name(rx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001557 goto err_free_clk_master_bus;
1558 }
1559
1560 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1561 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001562 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001563 goto err_free_clk_rx;
1564 return ret;
1565 }
1566
1567 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1568 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001569 pr_err("clk_get_by_name(tx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001570 goto err_free_clk_ptp_ref;
1571 }
1572
1573 debug("%s: OK\n", __func__);
1574 return 0;
1575
1576err_free_clk_ptp_ref:
1577 clk_free(&eqos->clk_ptp_ref);
1578err_free_clk_rx:
1579 clk_free(&eqos->clk_rx);
1580err_free_clk_master_bus:
1581 clk_free(&eqos->clk_master_bus);
1582err_free_clk_slave_bus:
1583 clk_free(&eqos->clk_slave_bus);
1584err_free_gpio_phy_reset:
1585 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1586err_free_reset_eqos:
1587 reset_free(&eqos->reset_ctl);
1588
1589 debug("%s: returns %d\n", __func__, ret);
1590 return ret;
1591}
1592
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001593/* board-specific Ethernet Interface initializations. */
Patrick Delaunay53e3d522019-08-01 11:29:03 +02001594__weak int board_interface_eth_init(struct udevice *dev,
1595 phy_interface_t interface_type)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001596{
1597 return 0;
1598}
1599
1600static int eqos_probe_resources_stm32(struct udevice *dev)
1601{
1602 struct eqos_priv *eqos = dev_get_priv(dev);
1603 int ret;
1604 phy_interface_t interface;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001605
1606 debug("%s(dev=%p):\n", __func__, dev);
1607
1608 interface = eqos->config->interface(dev);
1609
1610 if (interface == PHY_INTERFACE_MODE_NONE) {
1611 pr_err("Invalid PHY interface\n");
1612 return -EINVAL;
1613 }
1614
Patrick Delaunay53e3d522019-08-01 11:29:03 +02001615 ret = board_interface_eth_init(dev, interface);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001616 if (ret)
1617 return -EINVAL;
1618
1619 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1620 if (ret) {
1621 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1622 goto err_probe;
1623 }
1624
1625 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1626 if (ret) {
1627 pr_err("clk_get_by_name(rx) failed: %d", ret);
1628 goto err_free_clk_master_bus;
1629 }
1630
1631 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1632 if (ret) {
1633 pr_err("clk_get_by_name(tx) failed: %d", ret);
1634 goto err_free_clk_rx;
1635 }
1636
1637 /* Get ETH_CLK clocks (optional) */
1638 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1639 if (ret)
1640 pr_warn("No phy clock provided %d", ret);
1641
1642 debug("%s: OK\n", __func__);
1643 return 0;
1644
1645err_free_clk_rx:
1646 clk_free(&eqos->clk_rx);
1647err_free_clk_master_bus:
1648 clk_free(&eqos->clk_master_bus);
1649err_probe:
1650
1651 debug("%s: returns %d\n", __func__, ret);
1652 return ret;
1653}
1654
1655static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
1656{
1657 const char *phy_mode;
1658 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1659
1660 debug("%s(dev=%p):\n", __func__, dev);
1661
1662 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1663 NULL);
1664 if (phy_mode)
1665 interface = phy_get_interface_by_name(phy_mode);
1666
1667 return interface;
1668}
1669
1670static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
1671{
1672 return PHY_INTERFACE_MODE_MII;
1673}
1674
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001675static int eqos_remove_resources_tegra186(struct udevice *dev)
1676{
1677 struct eqos_priv *eqos = dev_get_priv(dev);
1678
1679 debug("%s(dev=%p):\n", __func__, dev);
1680
1681 clk_free(&eqos->clk_tx);
1682 clk_free(&eqos->clk_ptp_ref);
1683 clk_free(&eqos->clk_rx);
1684 clk_free(&eqos->clk_slave_bus);
1685 clk_free(&eqos->clk_master_bus);
1686 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1687 reset_free(&eqos->reset_ctl);
1688
1689 debug("%s: OK\n", __func__);
1690 return 0;
1691}
1692
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001693static int eqos_remove_resources_stm32(struct udevice *dev)
1694{
1695 struct eqos_priv *eqos = dev_get_priv(dev);
1696
1697 debug("%s(dev=%p):\n", __func__, dev);
1698
1699 clk_free(&eqos->clk_tx);
1700 clk_free(&eqos->clk_rx);
1701 clk_free(&eqos->clk_master_bus);
1702 if (clk_valid(&eqos->clk_ck))
1703 clk_free(&eqos->clk_ck);
1704
1705 debug("%s: OK\n", __func__);
1706 return 0;
1707}
1708
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001709static int eqos_probe(struct udevice *dev)
1710{
1711 struct eqos_priv *eqos = dev_get_priv(dev);
1712 int ret;
1713
1714 debug("%s(dev=%p):\n", __func__, dev);
1715
1716 eqos->dev = dev;
1717 eqos->config = (void *)dev_get_driver_data(dev);
1718
Simon Glassa821c4a2017-05-17 17:18:05 -06001719 eqos->regs = devfdt_get_addr(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001720 if (eqos->regs == FDT_ADDR_T_NONE) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001721 pr_err("devfdt_get_addr() failed");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001722 return -ENODEV;
1723 }
1724 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
1725 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
1726 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
1727 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
1728
1729 ret = eqos_probe_resources_core(dev);
1730 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001731 pr_err("eqos_probe_resources_core() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001732 return ret;
1733 }
1734
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001735 ret = eqos->config->ops->eqos_probe_resources(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001736 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001737 pr_err("eqos_probe_resources() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001738 goto err_remove_resources_core;
1739 }
1740
1741 eqos->mii = mdio_alloc();
1742 if (!eqos->mii) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001743 pr_err("mdio_alloc() failed");
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001744 ret = -ENOMEM;
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001745 goto err_remove_resources_tegra;
1746 }
1747 eqos->mii->read = eqos_mdio_read;
1748 eqos->mii->write = eqos_mdio_write;
1749 eqos->mii->priv = eqos;
1750 strcpy(eqos->mii->name, dev->name);
1751
1752 ret = mdio_register(eqos->mii);
1753 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001754 pr_err("mdio_register() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001755 goto err_free_mdio;
1756 }
1757
1758 debug("%s: OK\n", __func__);
1759 return 0;
1760
1761err_free_mdio:
1762 mdio_free(eqos->mii);
1763err_remove_resources_tegra:
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001764 eqos->config->ops->eqos_remove_resources(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001765err_remove_resources_core:
1766 eqos_remove_resources_core(dev);
1767
1768 debug("%s: returns %d\n", __func__, ret);
1769 return ret;
1770}
1771
1772static int eqos_remove(struct udevice *dev)
1773{
1774 struct eqos_priv *eqos = dev_get_priv(dev);
1775
1776 debug("%s(dev=%p):\n", __func__, dev);
1777
1778 mdio_unregister(eqos->mii);
1779 mdio_free(eqos->mii);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001780 eqos->config->ops->eqos_remove_resources(dev);
1781
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001782 eqos_probe_resources_core(dev);
1783
1784 debug("%s: OK\n", __func__);
1785 return 0;
1786}
1787
1788static const struct eth_ops eqos_ops = {
1789 .start = eqos_start,
1790 .stop = eqos_stop,
1791 .send = eqos_send,
1792 .recv = eqos_recv,
1793 .free_pkt = eqos_free_pkt,
1794 .write_hwaddr = eqos_write_hwaddr,
1795};
1796
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001797static struct eqos_ops eqos_tegra186_ops = {
1798 .eqos_inval_desc = eqos_inval_desc_tegra186,
1799 .eqos_flush_desc = eqos_flush_desc_tegra186,
1800 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
1801 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
1802 .eqos_probe_resources = eqos_probe_resources_tegra186,
1803 .eqos_remove_resources = eqos_remove_resources_tegra186,
1804 .eqos_stop_resets = eqos_stop_resets_tegra186,
1805 .eqos_start_resets = eqos_start_resets_tegra186,
1806 .eqos_stop_clks = eqos_stop_clks_tegra186,
1807 .eqos_start_clks = eqos_start_clks_tegra186,
1808 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
1809 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
1810 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
1811 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
1812};
1813
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001814static const struct eqos_config eqos_tegra186_config = {
1815 .reg_access_always_ok = false,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001816 .mdio_wait = 10,
1817 .swr_wait = 10,
1818 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
1819 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
1820 .interface = eqos_get_interface_tegra186,
1821 .ops = &eqos_tegra186_ops
1822};
1823
1824static struct eqos_ops eqos_stm32_ops = {
1825 .eqos_inval_desc = eqos_inval_desc_stm32,
1826 .eqos_flush_desc = eqos_flush_desc_stm32,
1827 .eqos_inval_buffer = eqos_inval_buffer_stm32,
1828 .eqos_flush_buffer = eqos_flush_buffer_stm32,
1829 .eqos_probe_resources = eqos_probe_resources_stm32,
1830 .eqos_remove_resources = eqos_remove_resources_stm32,
1831 .eqos_stop_resets = eqos_stop_resets_stm32,
1832 .eqos_start_resets = eqos_start_resets_stm32,
1833 .eqos_stop_clks = eqos_stop_clks_stm32,
1834 .eqos_start_clks = eqos_start_clks_stm32,
1835 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
1836 .eqos_disable_calibration = eqos_disable_calibration_stm32,
1837 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
1838 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
1839};
1840
1841static const struct eqos_config eqos_stm32_config = {
1842 .reg_access_always_ok = false,
1843 .mdio_wait = 10000,
1844 .swr_wait = 50,
1845 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
1846 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
1847 .interface = eqos_get_interface_stm32,
1848 .ops = &eqos_stm32_ops
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001849};
1850
1851static const struct udevice_id eqos_ids[] = {
1852 {
1853 .compatible = "nvidia,tegra186-eqos",
1854 .data = (ulong)&eqos_tegra186_config
1855 },
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001856 {
1857 .compatible = "snps,dwmac-4.20a",
1858 .data = (ulong)&eqos_stm32_config
1859 },
1860
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001861 { }
1862};
1863
1864U_BOOT_DRIVER(eth_eqos) = {
1865 .name = "eth_eqos",
1866 .id = UCLASS_ETH,
1867 .of_match = eqos_ids,
1868 .probe = eqos_probe,
1869 .remove = eqos_remove,
1870 .ops = &eqos_ops,
1871 .priv_auto_alloc_size = sizeof(struct eqos_priv),
1872 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1873};