blob: 1a5ffd57099f214e24d619ebaec66a7a89849428 [file] [log] [blame]
Hannes Petermaier072cefe2014-02-07 14:06:50 +01001/*
2 * mux.c
3 *
4 * Pinmux Setting for B&R LEIT Board(s)
5 *
6 * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#include <common.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/arch/hardware.h>
15#include <asm/arch/mux.h>
16#include <asm/io.h>
17#include <i2c.h>
18
19static struct module_pin_mux usb0_pin_mux[] = {
20 {OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
21 /* USB0 DrvBus Receiver disable (from romcode 0x20) */
22 {OFFSET(usb0_drvvbus), (MODE(0))},
23 /* USB1 DrvBus as GPIO due to HW-Workaround */
24 {OFFSET(usb1_drvvbus), (MODE(7))},
25 {-1},
26};
27static struct module_pin_mux spi1_pin_mux[] = {
28 /* SPI1_SCLK */
29 {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
30 /* SPI1_D0 */
31 {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
32 /* SPI1_D1 */
33 {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
34 /* SPI1_CS0 */
35 {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
36 {-1},
37};
38
39static struct module_pin_mux dcan0_pin_mux[] = {
40 /* DCAN0 TX */
41 {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
42 /* DCAN0 RX */
43 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
44 {-1},
45};
46
47static struct module_pin_mux dcan1_pin_mux[] = {
48 /* DCAN1 TX */
49 {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
50 /* DCAN1 RX */
51 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
52 {-1},
53};
54
55static struct module_pin_mux gpios[] = {
56 /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
57 {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
58 /* GPIO0_4 (SPI D1) - TA602 */
59 {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
60 /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
61 {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
62 /* GPIO0_7 (PWW0 OUT) - CAN TERM */
63 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
64 /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
65 {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
66 /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
67 {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
68 /* GPIO0_30 (GPMC_WAIT0) - TA601 */
69 {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
70 /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
71 {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
72 /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
73 {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
74 /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
75 {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
76 /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
77 {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
78 /* GPIO2_4 (GPMC_nWE) - TST_BAST */
79 {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
80 /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
81 {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
82 /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
83 {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
84 /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
85 {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
86 {-1},
87};
88
89static struct module_pin_mux uart0_pin_mux[] = {
90 /* UART0_CTS */
91 {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
92 /* UART0_RXD */
93 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
94 /* UART0_TXD */
95 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
96 {-1},
97};
98
99static struct module_pin_mux i2c0_pin_mux[] = {
100 /* I2C_DATA */
101 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
102 /* I2C_SCLK */
103 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
104 {-1},
105};
106
107static struct module_pin_mux mii1_pin_mux[] = {
108 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
109 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
110 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
111 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
112 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
113 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
114 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
115 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
116 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
117 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
118 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
119 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
120 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
121 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
122 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
123 {-1},
124};
125
126static struct module_pin_mux mmc1_pin_mux[] = {
127 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
128 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
129 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
130 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
131 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
132 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
133 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
134 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
135
136 {-1},
137};
138
139static struct module_pin_mux lcd_pin_mux[] = {
140 {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
141 {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
142 {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
143 {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
144 {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
145 {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
146 {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
147 {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
148 {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
149 {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
150 {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
151 {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
152 {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
153 {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
154 {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
155 {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
156
157 {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
158 {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
159 {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
160 {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
161 {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
162 {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
163 {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
164 {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
165
166 {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
167 {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
168 {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
169 {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
170
171 {-1},
172};
173
174void enable_uart0_pin_mux(void)
175{
176 configure_module_pin_mux(uart0_pin_mux);
177}
178
179void enable_i2c0_pin_mux(void)
180{
181 configure_module_pin_mux(i2c0_pin_mux);
182}
183
184void enable_board_pin_mux(void)
185{
186 configure_module_pin_mux(i2c0_pin_mux);
187 configure_module_pin_mux(mii1_pin_mux);
188 configure_module_pin_mux(usb0_pin_mux);
189 configure_module_pin_mux(spi1_pin_mux);
190 configure_module_pin_mux(dcan0_pin_mux);
191 configure_module_pin_mux(dcan1_pin_mux);
192 configure_module_pin_mux(mmc1_pin_mux);
193 configure_module_pin_mux(lcd_pin_mux);
194 configure_module_pin_mux(gpios);
195}