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Michal Simek18a952c2018-03-27 10:36:39 +02001// SPDX-License-Identifier: GPL-2.0+
Michal Simek6c0c9582016-04-07 16:00:11 +02002/*
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
4 *
Michal Simekd31f1c92020-02-18 08:38:06 +01005 * (C) Copyright 2015 - 2020, Xilinx, Inc.
Michal Simek6c0c9582016-04-07 16:00:11 +02006 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
Michal Simek6c0c9582016-04-07 16:00:11 +02009 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
Michal Simekee4983f2017-12-08 14:50:42 +010014#include "zynqmp-clk-ccf.dtsi"
Michal Simek6c0c9582016-04-07 16:00:11 +020015/ {
16 model = "ZynqMP zc1751-xm019-dc5 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18
19 aliases {
20 ethernet0 = &gem1;
21 gpio0 = &gpio;
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 mmc0 = &sdhci0;
25 serial0 = &uart0;
26 serial1 = &uart1;
27 };
28
29 chosen {
Michal Simek9b28a5d2017-02-27 08:11:38 +010030 bootargs = "earlycon";
Michal Simek6c0c9582016-04-07 16:00:11 +020031 stdout-path = "serial0:115200n8";
32 };
33
Michal Simekc926e6f2016-11-11 13:21:04 +010034 memory@0 {
Michal Simek6c0c9582016-04-07 16:00:11 +020035 device_type = "memory";
36 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
37 };
38};
39
Michal Simek6c0c9582016-04-07 16:00:11 +020040&fpd_dma_chan1 {
41 status = "okay";
Michal Simek6c0c9582016-04-07 16:00:11 +020042};
43
44&fpd_dma_chan2 {
45 status = "okay";
Michal Simek6c0c9582016-04-07 16:00:11 +020046};
47
48&fpd_dma_chan3 {
49 status = "okay";
50};
51
52&fpd_dma_chan4 {
53 status = "okay";
Michal Simek6c0c9582016-04-07 16:00:11 +020054};
55
56&fpd_dma_chan5 {
57 status = "okay";
58};
59
60&fpd_dma_chan6 {
61 status = "okay";
Michal Simek6c0c9582016-04-07 16:00:11 +020062};
63
64&fpd_dma_chan7 {
65 status = "okay";
66};
67
68&fpd_dma_chan8 {
69 status = "okay";
Michal Simek6c0c9582016-04-07 16:00:11 +020070};
71
72&gem1 {
73 status = "okay";
Michal Simek6c0c9582016-04-07 16:00:11 +020074 phy-handle = <&phy0>;
75 phy-mode = "rgmii-id";
Michal Simek2975a422019-08-08 12:44:22 +020076 phy0: ethernet-phy@0 {
Michal Simek6c0c9582016-04-07 16:00:11 +020077 reg = <0>;
78 };
79};
80
81&gpio {
82 status = "okay";
83};
84
Michal Simek6c0c9582016-04-07 16:00:11 +020085&i2c0 {
86 status = "okay";
87};
88
Michal Simek6c0c9582016-04-07 16:00:11 +020089&i2c1 {
90 status = "okay";
91};
92
93&sdhci0 {
94 status = "okay";
Srinivas Goud1077dc22017-08-22 14:38:46 +053095 no-1-8-v;
Michal Simek6c0c9582016-04-07 16:00:11 +020096};
97
Michal Simek470f09c2018-03-27 16:10:25 +020098&ttc0 {
99 status = "okay";
100};
101
102&ttc1 {
103 status = "okay";
104};
105
106&ttc2 {
107 status = "okay";
108};
109
110&ttc3 {
111 status = "okay";
112};
113
Michal Simek6c0c9582016-04-07 16:00:11 +0200114&uart0 {
115 status = "okay";
116};
117
118&uart1 {
119 status = "okay";
120};
121
122&watchdog0 {
123 status = "okay";
124};