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TsiChung Liew536e7da2008-10-22 11:38:21 +00001/*
2 * m5301x.h -- Definitions for Freescale Coldfire 5301x
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef m5301x_h
27#define m5301x_h
28
29/* *** System Control Module (SCM) *** */
30#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
31#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
32#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
33#define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12)
34#define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8)
35#define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4)
36#define MPROT_MTR 4
37#define MPROT_MTW 2
38#define MPROT_MPL 1
39
40#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
41#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
42#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
43#define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8)
44
45#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
46#define SCM_PACRB_PACR13(x) (((x) & 0x0F) << 8)
47
48#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
49#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
50#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
51#define SCM_PACRC_PACR19(x) (((x) & 0x0F) << 16)
52#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
53#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
54#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
55
56#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
57#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
58#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
59#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
60#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
61#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
62#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
63
64#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
65#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
66#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
67#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
68#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
69#define SCM_PACRE_PACR37(x) (((x) & 0x0F) << 8)
70#define SCM_PACRE_PACR39(x) ((x) & 0x0F)
71
72#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
73#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
74#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
75#define SCM_PACRF_PACR43(x) (((x) & 0x0F) << 16)
76#define SCM_PACRF_PACR44(x) (((x) & 0x0F) << 12)
77#define SCM_PACRF_PACR45(x) (((x) & 0x0F) << 8)
78#define SCM_PACRF_PACR46(x) (((x) & 0x0F) << 4)
79#define SCM_PACRF_PACR47(x) ((x) & 0x0F)
80
81#define SCM_PACRG_PACR48(x) (((x) & 0x0F) << 28)
82#define SCM_PACRG_PACR49(x) (((x) & 0x0F) << 24)
83#define SCM_PACRG_PACR50(x) (((x) & 0x0F) << 20)
84#define SCM_PACRG_PACR51(x) (((x) & 0x0F) << 16)
85
86#define PACR_SP 4
87#define PACR_WP 2
88#define PACR_TP 1
89
90#define SCM_CWCR_RO (0x8000)
91#define SCM_CWCR_CWR_WH (0x0100)
92#define SCM_CWCR_CWE (0x0080)
93#define SCM_CWCR_CWRI_WINDOW (0x0060)
94#define SCM_CWCR_CWRI_RESET (0x0040)
95#define SCM_CWCR_CWRI_INT_RESET (0x0020)
96#define SCM_CWCR_CWRI_INT (0x0000)
97#define SCM_CWCR_CWT(x) (((x) & 0x001F))
98
99#define SCM_ISR_CFEI (0x02)
100#define SCM_ISR_CWIC (0x01)
101
102#define BCR_GBR (0x00000200)
103#define BCR_GBW (0x00000100)
104#define BCR_S7 (0x00000080)
105#define BCR_S6 (0x00000040)
106#define BCR_S4 (0x00000010)
107#define BCR_S1 (0x00000002)
108
109#define SCM_CFIER_ECFEI (0x01)
110
111#define SCM_CFLOC_LOC (0x80)
112
113#define SCM_CFATR_WRITE (0x80)
114#define SCM_CFATR_SZ32 (0x20)
115#define SCM_CFATR_SZ16 (0x10)
116#define SCM_CFATR_SZ08 (0x00)
117#define SCM_CFATR_CACHE (0x08)
118#define SCM_CFATR_MODE (0x02)
119#define SCM_CFATR_TYPE (0x01)
120
121/* *** Interrupt Controller (INTC) *** */
122#define INT0_LO_RSVD0 (0)
123#define INT0_LO_EPORT1 (1)
124#define INT0_LO_EPORT2 (2)
125#define INT0_LO_EPORT3 (3)
126#define INT0_LO_EPORT4 (4)
127#define INT0_LO_EPORT5 (5)
128#define INT0_LO_EPORT6 (6)
129#define INT0_LO_EPORT7 (7)
130#define INT0_LO_EDMA_00 (8)
131#define INT0_LO_EDMA_01 (9)
132#define INT0_LO_EDMA_02 (10)
133#define INT0_LO_EDMA_03 (11)
134#define INT0_LO_EDMA_04 (12)
135#define INT0_LO_EDMA_05 (13)
136#define INT0_LO_EDMA_06 (14)
137#define INT0_LO_EDMA_07 (15)
138#define INT0_LO_EDMA_08 (16)
139#define INT0_LO_EDMA_09 (17)
140#define INT0_LO_EDMA_10 (18)
141#define INT0_LO_EDMA_11 (19)
142#define INT0_LO_EDMA_12 (20)
143#define INT0_LO_EDMA_13 (21)
144#define INT0_LO_EDMA_14 (22)
145#define INT0_LO_EDMA_15 (23)
146#define INT0_LO_EDMA_ERR (24)
147#define INT0_LO_SCM_CWIC (25)
148#define INT0_LO_UART0 (26)
149#define INT0_LO_UART1 (27)
150#define INT0_LO_UART2 (28)
151#define INT0_LO_RSVD1 (29)
152#define INT0_LO_I2C (30)
153#define INT0_LO_DSPI (31)
154#define INT0_HI_DTMR0 (32)
155#define INT0_HI_DTMR1 (33)
156#define INT0_HI_DTMR2 (34)
157#define INT0_HI_DTMR3 (35)
158#define INT0_HI_FEC0_TXF (36)
159#define INT0_HI_FEC0_TXB (37)
160#define INT0_HI_FEC0_UN (38)
161#define INT0_HI_FEC0_RL (39)
162#define INT0_HI_FEC0_RXF (40)
163#define INT0_HI_FEC0_RXB (41)
164#define INT0_HI_FEC0_MII (42)
165#define INT0_HI_FEC0_LC (43)
166#define INT0_HI_FEC0_HBERR (44)
167#define INT0_HI_FEC0_GRA (45)
168#define INT0_HI_FEC0_EBERR (46)
169#define INT0_HI_FEC0_BABT (47)
170#define INT0_HI_FEC0_BABR (48)
171#define INT0_HI_FEC1_TXF (49)
172#define INT0_HI_FEC1_TXB (50)
173#define INT0_HI_FEC1_UN (51)
174#define INT0_HI_FEC1_RL (52)
175#define INT0_HI_FEC1_RXF (53)
176#define INT0_HI_FEC1_RXB (54)
177#define INT0_HI_FEC1_MII (55)
178#define INT0_HI_FEC1_LC (56)
179#define INT0_HI_FEC1_HBERR (57)
180#define INT0_HI_FEC1_GRA (58)
181#define INT0_HI_FEC1_EBERR (59)
182#define INT0_HI_FEC1_BABT (60)
183#define INT0_HI_FEC1_BABR (61)
184#define INT0_HI_SCM_CFEI (62)
185
186/* 0 - 24 reserved */
187#define INT1_LO_EPORT1_FLAG0 (25)
188#define INT1_LO_EPORT1_FLAG1 (26)
189#define INT1_LO_EPORT1_FLAG2 (27)
190#define INT1_LO_EPORT1_FLAG3 (28)
191#define INT1_LO_EPORT1_FLAG4 (29)
192#define INT1_LO_EPORT1_FLAG5 (30)
193#define INT1_LO_EPORT1_FLAG6 (31)
194#define INT1_LO_EPORT1_FLAG7 (32)
195#define INT1_HI_DSPI_EOQF (33)
196#define INT1_HI_DSPI_TFFF (34)
197#define INT1_HI_DSPI_TCF (35)
198#define INT1_HI_DSPI_TFUF (36)
199#define INT1_HI_DSPI_RFDF (37)
200#define INT1_HI_DSPI_RFOF (38)
201#define INT1_HI_DSPI_RFOF_TFUF (39)
202#define INT1_HI_RNG_EI (40)
203#define INT1_HI_PLL_LOCF (41)
204#define INT1_HI_PLL_LOLF (42)
205#define INT1_HI_PIT0 (43)
206#define INT1_HI_PIT1 (44)
207#define INT1_HI_PIT2 (45)
208#define INT1_HI_PIT3 (46)
209#define INT1_HI_USBOTG_STS (47)
210#define INT1_HI_USBHOST_STS (48)
211#define INT1_HI_SSI (49)
212/* 50 - 51 reserved */
213#define INT1_HI_RTC (52)
214#define INT1_HI_CCM_USBSTAT (53)
215#define INT1_HI_CODEC_OR (54)
216#define INT1_HI_CODEC_RF_TE (55)
217#define INT1_HI_CODEC_ROE (56)
218#define INT1_HI_CODEC_TUE (57)
219/* 58 reserved */
220#define INT1_HI_SIM1_DATA (59)
221#define INT1_HI_SIM1_GENERAL (60)
222/* 61 - 62 reserved */
223#define INT1_HI_SDHC (63)
224
225/* *** Reset Controller Module (RCM) *** */
226#define RCM_RCR_SOFTRST (0x80)
227#define RCM_RCR_FRCRSTOUT (0x40)
228
229#define RCM_RSR_SOFT (0x20)
230#define RCM_RSR_LOC (0x10)
231#define RCM_RSR_POR (0x08)
232#define RCM_RSR_EXT (0x04)
233#define RCM_RSR_WDR_CORE (0x02)
234#define RCM_RSR_LOL (0x01)
235
236/* *** Chip Configuration Module (CCM) *** */
237#define CCM_CCR_CSC (0x0020)
238#define CCM_CCR_BOOTPS (0x0010)
239#define CCM_CCR_LOAD (0x0008)
240#define CCM_CCR_OSC_MODE (0x0004)
241#define CCM_CCR_SDR_MODE (0x0002)
242#define CCM_CCR_RESERVED (0x0001)
243
244#define CCM_RCON_SDR_32BIT_UNIFIED (0x0012)
245#define CCM_RCON_DDR_8BIT_SPLIT (0x0010)
246#define CCM_RCON_SDR_16BIT_UNIFIED (0x0002)
247#define CCM_RCON_DDR_16BIT_SPLIT (0x0000)
248
249#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
250#define CCM_CIR_PRN(x) ((x) & 0x003F)
251
252#define CCM_MISCCR_FECM (0x8000)
253#define CCM_MISCCR_CDCSRC (0x4000)
254#define CCM_MISCCR_PLL_LOCK (0x2000)
255#define CCM_MISCCR_LIMP (0x1000)
256#define CCM_MISCCR_BME (0x8000)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600257#define CCM_MISCCR_BMT_UNMASK (0xF8FF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000258#define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8)
259#define CCM_MISCCR_BMT_512 (0x0700)
260#define CCM_MISCCR_BMT_1024 (0x0600)
261#define CCM_MISCCR_BMT_2048 (0x0500)
262#define CCM_MISCCR_BMT_4096 (0x0400)
263#define CCM_MISCCR_BMT_8192 (0x0300)
264#define CCM_MISCCR_BMT_16384 (0x0200)
265#define CCM_MISCCR_BMT_32768 (0x0100)
266#define CCM_MISCCR_BMT_65536 (0x0000)
267#define CCM_MISCCR_TIM_DMA (0x0020)
268#define CCM_MISCCR_SSI_SRC (0x0010)
269#define CCM_MISCCR_USBH_OC (0x0008)
270#define CCM_MISCCR_USBO_OC (0x0004)
271#define CCM_MISCCR_USB_PUE (0x0002)
272#define CCM_MISCCR_USB_SRC (0x0001)
273
274#define CCM_CDR_LPDIV(x) (((x) & 0x0F) << 8)
275#define CCM_CDR_SSIDIV(x) ((x) & 0xFF)
276
277#define CCM_UOCSR_DPPD (0x2000)
278#define CCM_UOCSR_DMPD (0x1000)
279#define CCM_UOCSR_DRV_VBUS (0x0800)
280#define CCM_UOCSR_CRG_VBUS (0x0400)
281#define CCM_UOCSR_DCR_VBUS (0x0200)
282#define CCM_UOCSR_DPPU (0x0100)
283#define CCM_UOCSR_AVLD (0x0080)
284#define CCM_UOCSR_BVLD (0x0040)
285#define CCM_UOCSR_VVLD (0x0020)
286#define CCM_UOCSR_SEND (0x0010)
287#define CCM_UOCSR_PWRFLT (0x0008)
288#define CCM_UOCSR_WKUP (0x0004)
289#define CCM_UOCSR_UOMIE (0x0002)
290#define CCM_UOCSR_XPDE (0x0001)
291
292#define CCM_UHCSR_PORTIND(x) (((x) & 0x0003) << 14)
293#define CCM_UHCSR_DRV_VBUS (0x0010)
294#define CCM_UHCSR_PWRFLT (0x0008)
295#define CCM_UHCSR_WKUP (0x0004)
296#define CCM_UHCSR_UHMIE (0x0002)
297#define CCM_UHCSR_XPDE (0x0001)
298
299#define CCM_CODCR_BGREN (0x8000)
300#define CCM_CODCR_REGEN (0x0080)
301
302#define CCM_MISC2_IGNLL (0x0008)
303#define CCM_MISC2_DPS (0x0001)
304
305/* *** General Purpose I/O (GPIO) *** */
306#define GPIO_PDR_FBCTL ((x) & 0x0F)
307#define GPIO_PDR_BE ((x) & 0x0F)
308#define GPIO_PDR_CS32 (((x) & 0x03) << 4)
309#define GPIO_PDR_CS10 (((x) & 0x03) << 4)
310#define GPIO_PDR_DSPI ((x) & 0x7F)
311#define GPIO_PDR_FEC0 ((x) & 0x7F)
312#define GPIO_PDR_FECI2C ((x) & 0x3F)
313#define GPIO_PDR_SIMP1 ((x) & 0x1F)
314#define GPIO_PDR_SIMP0 ((x) & 0x1F)
315#define GPIO_PDR_TIMER ((x) & 0x0F)
316#define GPIO_PDR_UART ((x) & 0x3F)
317#define GPIO_PDR_DEBUG (0x01)
318#define GPIO_PDR_SDHC ((x) & 0x3F)
319#define GPIO_PDR_SSI ((x) & 0x1F)
320
321#define GPIO_PAR_FBCTL_OE (0x80)
322#define GPIO_PAR_FBCTL_TA (0x40)
323#define GPIO_PAR_FBCTL_RWB (0x20)
324#define GPIO_PAR_FBCTL_TS (0x18)
325
326#define GPIO_PAR_BE3 (0x40)
327#define GPIO_PAR_BE2 (0x10)
328#define GPIO_PAR_BE1 (0x04)
329#define GPIO_PAR_BE0 (0x01)
330
331#define GPIO_PAR_CS5 (0x40)
332#define GPIO_PAR_CS4 (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600333#define GPIO_PAR_CS1_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000334#define GPIO_PAR_CS1_CS1 (0x0C)
335#define GPIO_PAR_CS1_SDCS1 (0x08)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600336#define GPIO_PAR_CS0_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000337#define GPIO_PAR_CS0_CS0 (0x03)
338#define GPIO_PAR_CS0_CS4 (0x02)
339
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600340#define GPIO_PAR_DSPIH_SIN_UNMASK (0x3F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000341#define GPIO_PAR_DSPIH_SIN (0xC0)
342#define GPIO_PAR_DSPIH_SIN_U2RXD (0x80)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600343#define GPIO_PAR_DSPIH_SOUT_UNMASK (0xCF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000344#define GPIO_PAR_DSPIH_SOUT (0x30)
345#define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600346#define GPIO_PAR_DSPIH_SCK_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000347#define GPIO_PAR_DSPIH_SCK (0x0C)
348#define GPIO_PAR_DSPIH_SCK_U2CTS (0x08)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600349#define GPIO_PAR_DSPIH_PCS0_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000350#define GPIO_PAR_DSPIH_PCS0 (0x03)
351#define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02)
352
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600353#define GPIO_PAR_DSPIL_PCS1_UNMASK (0x3F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000354#define GPIO_PAR_DSPIL_PCS1 (0xC0)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600355#define GPIO_PAR_DSPIL_PCS2_UNMASK (0xCF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000356#define GPIO_PAR_DSPIL_PCS2 (0x30)
357#define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600358#define GPIO_PAR_DSPIL_PCS3_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000359#define GPIO_PAR_DSPIL_PCS3 (0x0C)
360#define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08)
361
362#define GPIO_PAR_FEC1_7W_FEC (0x40)
363#define GPIO_PAR_FEC1_RMII_FEC (0x10)
364#define GPIO_PAR_FEC0_7W_FEC (0x04)
365#define GPIO_PAR_FEC0_RMII_FEC (0x01)
366
367/* GPIO_PAR_FECI2C */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600368#define GPIO_PAR_FECI2C_RMII0_UNMASK (0x3F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000369#define GPIO_PAR_FECI2C_MDC0 (0x80)
370#define GPIO_PAR_FECI2C_MDIO0 (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600371#define GPIO_PAR_FECI2C_RMII1_UNMASK (0xCF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000372#define GPIO_PAR_FECI2C_MDC1 (0x20)
373#define GPIO_PAR_FECI2C_MDIO1 (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600374#define GPIO_PAR_FECI2C_SDA_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000375#define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2)
376#define GPIO_PAR_FECI2C_SDA_SDA (0x0C)
377#define GPIO_PAR_FECI2C_SDA_U2TXD (0x08)
378#define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600379#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000380#define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03)
381#define GPIO_PAR_FECI2C_SCL_SCL (0x03)
382#define GPIO_PAR_FECI2C_SCL_U2RXD (0x02)
383#define GPIO_PAR_FECI2C_SCL_MDC1 (0x01)
384
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600385#define GPIO_PAR_IRQ0H_IRQ07_UNMASK (0x3F)
386#define GPIO_PAR_IRQ0H_IRQ06_UNMASK (0xCF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000387#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600388#define GPIO_PAR_IRQ0H_IRQ04_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000389#define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02)
390
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600391#define GPIO_PAR_IRQ0L_IRQ01_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000392#define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08)
393
394#define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40)
395#define GPIO_PAR_IRQ1H_IRQ16_DDATA2 (0x10)
396#define GPIO_PAR_IRQ1H_IRQ15_DDATA1 (0x04)
397#define GPIO_PAR_IRQ1H_IRQ14_DDATA0 (0x01)
398
399#define GPIO_PAR_IRQ1L_IRQ13_PST3 (0x40)
400#define GPIO_PAR_IRQ1L_IRQ12_PST2 (0x10)
401#define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04)
402#define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01)
403
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600404#define GPIO_PAR_SIMP1H_DATA1_UNMASK (0x3F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000405#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0)
406#define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80)
407#define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600408#define GPIO_PAR_SIMP1H_VEN1_UNMASK (0xCF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000409#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30)
410#define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20)
411#define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600412#define GPIO_PAR_SIMP1H_RST1_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000413#define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C)
414#define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08)
415#define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600416#define GPIO_PAR_SIMP1H_PD1_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000417#define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03)
418#define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02)
419#define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01)
420
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600421#define GPIO_PAR_SIMP1L_CLK_UNMASK (0x3F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000422#define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0)
423#define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80)
424
425#define GPIO_PAR_SIMP0_DATA0 (0x10)
426#define GPIO_PAR_SIMP0_VEN0 (0x08)
427#define GPIO_PAR_SIMP0_RST0 (0x04)
428#define GPIO_PAR_SIMP0_PD0 (0x02)
429#define GPIO_PAR_SIMP0_CLK0 (0x01)
430
431#define GPIO_PAR_TIN3(x) (((x) & 0x03) << 6)
432#define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4)
433#define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2)
434#define GPIO_PAR_TIN0(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600435#define GPIO_PAR_TIN3_UNMASK (0x3F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000436#define GPIO_PAR_TIN3_TIN3 (0xC0)
437#define GPIO_PAR_TIN3_TOUT3 (0x80)
438#define GPIO_PAR_TIN3_IRQ03 (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600439#define GPIO_PAR_TIN2_UNMASK (0xCF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000440#define GPIO_PAR_TIN2_TIN2 (0x30)
441#define GPIO_PAR_TIN2_TOUT2 (0x20)
442#define GPIO_PAR_TIN2_IRQ02 (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600443#define GPIO_PAR_TIN1_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000444#define GPIO_PAR_TIN1_TIN1 (0x0C)
445#define GPIO_PAR_TIN1_TOUT1 (0x08)
446#define GPIO_PAR_TIN1_DACK1 (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600447#define GPIO_PAR_TIN0_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000448#define GPIO_PAR_TIN0_TIN0 (0x03)
449#define GPIO_PAR_TIN0_TOUT0 (0x02)
450#define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01)
451
452#define GPIO_PAR_UART_U2TXD (0x80)
453#define GPIO_PAR_UART_U2RXD (0x40)
454#define GPIO_PAR_UART_U0TXD (0x20)
455#define GPIO_PAR_UART_U0RXD (0x10)
456#define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2)
457#define GPIO_PAR_UART_CTS0(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600458#define GPIO_PAR_UART_RTS0_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000459#define GPIO_PAR_UART_RTS0_U0RTS (0x0C)
460#define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600461#define GPIO_PAR_UART_CTS0_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000462#define GPIO_PAR_UART_CTS0_U0CTS (0x03)
463#define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02)
464#define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01)
465
466#define GPIO_PAR_DEBUG_ALLPST (0x80)
467
468#define GPIO_PAR_SDHC_DATA3 (0x20)
469#define GPIO_PAR_SDHC_DATA2 (0x10)
470#define GPIO_PAR_SDHC_DATA1 (0x08)
471#define GPIO_PAR_SDHC_DATA0 (0x04)
472#define GPIO_PAR_SDHC_CMD (0x02)
473#define GPIO_PAR_SDHC_CLK (0x01)
474
475#define GPIO_PAR_SSIH_RXD(x) (((x) & 0x03) << 6)
476#define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4)
477#define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2)
478#define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600479#define GPIO_PAR_SSIH_RXD_UNMASK (0x3F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000480#define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0)
481#define GPIO_PAR_SSIH_RXD_U1RXD (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600482#define GPIO_PAR_SSIH_TXD_UNMASK (0xCF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000483#define GPIO_PAR_SSIH_TXD_SSIRXD (0x30)
484#define GPIO_PAR_SSIH_TXD_U1TXD (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600485#define GPIO_PAR_SSIH_FS_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000486#define GPIO_PAR_SSIH_FS_SSIFS (0x0C)
487#define GPIO_PAR_SSIH_FS_U1RTS (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600488#define GPIO_PAR_SSIH_MCLK_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000489#define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03)
490#define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01)
491
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600492#define GPIO_PAR_SSIL_UNMASK (0x3F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000493#define GPIO_PAR_SSIL_BCLK (0xC0)
494#define GPIO_PAR_SSIL_U1CTS (0x40)
495
496#define GPIO_MSCR_MSCR1(x) (((x) & 0x07) << 5)
497#define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5)
498#define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5)
499#define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600500#define GPIO_MSCR_MSCRn_UNMASK (0x1F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000501#define GPIO_MSCR_MSCRn_SDR (0xE0)
502#define GPIO_MSCR_MSCRn_25VDDR (0x60)
503#define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20)
504#define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00)
505
506#define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600507#define GPIO_MSCR_MSCR5_UNMASK (0xE3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000508#define GPIO_MSCR_MSCR5_SDR (0x1C)
509#define GPIO_MSCR_MSCR5_25VDDR (0x0C)
510#define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04)
511#define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00)
512
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600513#define GPIO_SRCR_DSPI_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000514#define GPIO_SRCR_DSPI(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600515#define GPIO_SRCR_I2C_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000516#define GPIO_SRCR_I2C(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600517#define GPIO_SRCR_IRQ_IRQ0_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000518#define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600519#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000520#define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600521#define GPIO_SRCR_SIM_SIMP0_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000522#define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600523#define GPIO_SRCR_SIM_SIMP1_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000524#define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600525#define GPIO_SRCR_TIMER_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000526#define GPIO_SRCR_TIMER(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600527#define GPIO_SRCR_UART2_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000528#define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600529#define GPIO_SRCR_UART0_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000530#define GPIO_SRCR_UART0(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600531#define GPIO_SRCR_SDHC_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000532#define GPIO_SRCR_SDHC(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600533#define GPIO_SRCR_SSI_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000534#define GPIO_SRCR_SSI(x) ((x) & 0x03)
535
536#define SRCR_HIGHEST (0x03)
537#define SRCR_HIGH (0x02)
538#define SRCR_LOW (0x01)
539#define SRCR_LOWEST (0x00)
540
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600541#define GPIO_DSCR_FEC_RMIICLK_UNMASK (0xCF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000542#define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600543#define GPIO_DSCR_FEC_RMII0_UNMASK (0xF3)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000544#define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600545#define GPIO_DSCR_FEC_RMII1_UNMASK (0xFC)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000546#define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03)
547
548#define DSCR_50PF (0x03)
549#define DSCR_30PF (0x02)
550#define DSCR_20PF (0x01)
551#define DSCR_10PF (0x00)
552
553#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN (0x80)
554#define GPIO_PCRH_SIM_VEN1_PULLUP_EN (0x40)
555#define GPIO_PCRH_SIM_VEN1_PULLUP (0x20)
556#define GPIO_PCRH_SIM_DATA1_PULLUP_EN (0x10)
557#define GPIO_PCRH_SIM_DATA1_PULLUP (0x08)
558#define GPIO_PCRH_SSI_PULLUP_EN (0x02)
559#define GPIO_PCRH_SSI_PULLUP (0x01)
560
561#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN (0x80)
562#define GPIO_PCRL_SDHC_DATA3_PULLUP (0x40)
563#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN (0x20)
564#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN (0x10)
565#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN (0x08)
566#define GPIO_PCRL_SDHC_CMD_PULLUP_EN (0x04)
567
568/* *** Phase Locked Loop (PLL) *** */
569#define PLL_PCR_LOC_IRQ (0x00040000)
570#define PLL_PCR_LOC_RE (0x00020000)
571#define PLL_PCR_LOC_EN (0x00010000)
572#define PLL_PCR_LOL_IRQ (0x00004000)
573#define PLL_PCR_LOL_RE (0x00002000)
574#define PLL_PCR_LOL_EN (0x00001000)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600575#define PLL_PCR_REFDIV_UNMASK (0xFFFFF8FF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000576#define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600577#define PLL_PCR_FBDIV_UNMASK (0xFFFFFFC0)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000578#define PLL_PCR_FBDIV(x) ((x) & 0x3F)
579
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600580#define PLL_PDR_OUTDIV4_UNMASK (0x0FFF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000581#define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600582#define PLL_PDR_OUTDIV3_UNMASK (0xF0FF)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000583#define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600584#define PLL_PDR_OUTDIV2_UNMASK (0xFF0F)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000585#define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600586#define PLL_PDR_OUTDIV1_UNMASK (0xFFF0)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000587#define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F)
588#define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x)
589#define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x)
590#define PLL_PDR_FB(x) PLL_PDR_OUTDIV2(x)
591#define PLL_PDR_CPU(x) PLL_PDR_OUTDIV1(x)
592
593#define PLL_PSR_LOCF (0x00000200)
594#define PLL_PSR_LOC (0x00000100)
595#define PLL_PSR_LOLF (0x00000040)
596#define PLL_PSR_LOCKS (0x00000020)
597#define PLL_PSR_LOCK (0x00000010)
598#define PLL_PSR_MODE(x) ((x) & 0x07)
599
600/* *** Real Time Clock *** */
601#define RTC_OCEN_OSCBYP (0x00000010)
602#define RTC_OCEN_CLKEN (0x00000008)
603
TsiChung Liew8d8235f2009-03-17 11:21:43 +0000604/* SDRAM */
605#define SDRAMC_SDCR_CKE (0x40000000)
606#define SDRAMC_SDCR_REF (0x10000000)
607
TsiChung Liew536e7da2008-10-22 11:38:21 +0000608#endif /* m5301x_h */