board/ge/bx50v3/bx50v3.cfg

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 *
 * Copyright 2015 Timesys Corporation.
 * Copyright 2015 General Electric Company
 *
 * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */

IMAGE_VERSION 2
BOOT_FROM sd

#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"

/* DDR IO */
DATA 4, MX6_IOM_GRP_DDR_TYPE,	0x000c0000
DATA 4, MX6_IOM_GRP_DDRPKE,	0x00000000
DATA 4, MX6_IOM_DRAM_SDCLK_0,	0x00000030
DATA 4, MX6_IOM_DRAM_SDCLK_1,	0x00000030
DATA 4, MX6_IOM_DRAM_CAS,	0x00000030
DATA 4, MX6_IOM_DRAM_RAS,	0x00000030
DATA 4, MX6_IOM_GRP_ADDDS,	0x00000030
DATA 4, MX6_IOM_DRAM_RESET,	0x00000030
DATA 4, MX6_IOM_DRAM_SDBA2,	0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0,	0x00000030
DATA 4, MX6_IOM_DRAM_SDODT1,	0x00000030
DATA 4, MX6_IOM_GRP_CTLDS,	0x00000030
DATA 4, MX6_IOM_DDRMODE_CTL,	0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0,	0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1,	0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2,	0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3,	0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4,	0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5,	0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6,	0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7,	0x00000030
DATA 4, MX6_IOM_GRP_DDRMODE,	0x00020000
DATA 4, MX6_IOM_GRP_B0DS,	0x00000030
DATA 4, MX6_IOM_GRP_B1DS,	0x00000030
DATA 4, MX6_IOM_GRP_B2DS,	0x00000030
DATA 4, MX6_IOM_GRP_B3DS,	0x00000030
DATA 4, MX6_IOM_GRP_B4DS,	0x00000030
DATA 4, MX6_IOM_GRP_B5DS,	0x00000030
DATA 4, MX6_IOM_GRP_B6DS,	0x00000030
DATA 4, MX6_IOM_GRP_B7DS,	0x00000030
DATA 4, MX6_IOM_DRAM_DQM0,	0x00000030
DATA 4, MX6_IOM_DRAM_DQM1,	0x00000030
DATA 4, MX6_IOM_DRAM_DQM2,	0x00000030
DATA 4, MX6_IOM_DRAM_DQM3,	0x00000030
DATA 4, MX6_IOM_DRAM_DQM4,	0x00000030
DATA 4, MX6_IOM_DRAM_DQM5,	0x00000030
DATA 4, MX6_IOM_DRAM_DQM6,	0x00000030
DATA 4, MX6_IOM_DRAM_DQM7,	0x00000030

/* Calibrations */
/* ZQ */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL,  0xa1390003
/* write leveling */
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
/* Read DQS Gating calibration */
DATA 4, MX6_MMDC_P0_MPDGCTRL0,	0x45380544
DATA 4, MX6_MMDC_P0_MPDGCTRL1,	0x05280530
DATA 4, MX6_MMDC_P1_MPDGCTRL0,	0x4530053C
DATA 4, MX6_MMDC_P1_MPDGCTRL1,	0x0530050C
/* Read calibration */
DATA 4, MX6_MMDC_P0_MPRDDLCTL,	0x36303032
DATA 4, MX6_MMDC_P1_MPRDDLCTL,	0x38363042
/* Write calibration */
DATA 4, MX6_MMDC_P0_MPWRDLCTL,	0x3A3A423E
DATA 4, MX6_MMDC_P1_MPWRDLCTL,	0x4A38483E
/* read data bit delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333

/* Complete calibration by forced measurment */
DATA 4, MX6_MMDC_P0_MPMUR0,	0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0,	0x00000800

/* MMDC init */
DATA 4, MX6_MMDC_P0_MDPDC,	0x00020036
DATA 4, MX6_MMDC_P0_MDOTC,	0x09444040
DATA 4, MX6_MMDC_P0_MDCFG0,	0x8A8F79A4
DATA 4, MX6_MMDC_P0_MDCFG1,	0xDB538E64
DATA 4, MX6_MMDC_P0_MDCFG2,	0x01ff00db
DATA 4, MX6_MMDC_P0_MDMISC,	0x00001740
DATA 4, MX6_MMDC_P0_MDSCR,	0x00008000
DATA 4, MX6_MMDC_P0_MDRWD,	0x000026d2
DATA 4, MX6_MMDC_P0_MDOR,	0x008F1023
DATA 4, MX6_MMDC_P0_MDASP,	0x00000047
DATA 4, MX6_MMDC_P0_MDCTL,	0x841a0000

/* Initialize Micron MT41J128M */
DATA 4, MX6_MMDC_P0_MDSCR,	0x04088032
DATA 4, MX6_MMDC_P0_MDSCR,	0x0408803a
DATA 4, MX6_MMDC_P0_MDSCR,	0x00008033
DATA 4, MX6_MMDC_P0_MDSCR,	0x0000803b
DATA 4, MX6_MMDC_P0_MDSCR,	0x00408031
DATA 4, MX6_MMDC_P0_MDSCR,	0x00408039
DATA 4, MX6_MMDC_P0_MDSCR,	0x09408030
DATA 4, MX6_MMDC_P0_MDSCR,	0x09408038
DATA 4, MX6_MMDC_P0_MDSCR,	0x04008040
DATA 4, MX6_MMDC_P0_MDSCR,	0x04008048
DATA 4, MX6_MMDC_P0_MDREF,	0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL,	0x00011117
DATA 4, MX6_MMDC_P1_MPODTCTRL,	0x00011117
DATA 4, MX6_MMDC_P0_MDPDC,	0x00025576
DATA 4, MX6_MMDC_P0_MAPSR,	0x00011006
DATA 4, MX6_MMDC_P0_MDSCR,	0x00000000

/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0x00FFF300
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF

/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F

/*
 * Setup CCM_CCOSR register as follows:
 *
 * cko1_en  1	   --> CKO1 enabled
 * cko1_div 111  --> divide by 8
 * cko1_sel 1011 --> ahb_clk_root
 *
 * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
 */
DATA 4, CCM_CCOSR, 0x000000fb