blob: 2e077dd5161f3d0d373153eb0dfb86e2efda3d12 [file] [log] [blame]
Stefan Roeseb02f76a2018-08-16 15:27:30 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4 */
5
6#ifndef __CONFIG_LINKIT_SMART_7688_H
7#define __CONFIG_LINKIT_SMART_7688_H
8
9/* CPU */
Stefan Roesefdceb0d2019-01-31 07:24:43 +010010#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
Stefan Roeseb02f76a2018-08-16 15:27:30 +020011
12/* RAM */
13#define CONFIG_SYS_SDRAM_BASE 0x80000000
14
Stefan Roeseb02f76a2018-08-16 15:27:30 +020015#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
16
Weijie Gao757cbbe2020-04-21 09:28:48 +020017/* SPL */
Stefan Roeseb02f76a2018-08-16 15:27:30 +020018
Weijie Gao757cbbe2020-04-21 09:28:48 +020019#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
Weijie Gao757cbbe2020-04-21 09:28:48 +020020
21/* Dummy value */
22#define CONFIG_SYS_UBOOT_BASE 0
23
24/* Serial SPL */
Simon Glass2a736062021-08-08 12:20:12 -060025#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Weijie Gao757cbbe2020-04-21 09:28:48 +020026#define CONFIG_SYS_NS16550_MEM32
27#define CONFIG_SYS_NS16550_CLK 40000000
28#define CONFIG_SYS_NS16550_REG_SIZE -4
29#define CONFIG_SYS_NS16550_COM3 0xb0000e00
Weijie Gao757cbbe2020-04-21 09:28:48 +020030
31#endif
32
Stefan Roeseb02f76a2018-08-16 15:27:30 +020033/* UART */
34#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
Weijie Gao443a2062019-09-25 17:45:42 +080035 230400, 460800, 921600 }
Stefan Roeseb02f76a2018-08-16 15:27:30 +020036
37/* RAM */
Stefan Roeseb02f76a2018-08-16 15:27:30 +020038
Stefan Roeseb02f76a2018-08-16 15:27:30 +020039/* Environment settings */
Stefan Roeseb02f76a2018-08-16 15:27:30 +020040
Stefan Roeseb02f76a2018-08-16 15:27:30 +020041#endif /* __CONFIG_LINKIT_SMART_7688_H */