Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
| 8 | * |
| 9 | * (C) Copyright 2003 |
| 10 | * Texas Instruments, <www.ti.com> |
| 11 | * Kshitij Gupta <Kshitij@ti.com> |
| 12 | * |
| 13 | * (C) Copyright 2004 |
| 14 | * ARM Ltd. |
| 15 | * Philippe Robin, <philippe.robin@arm.com> |
| 16 | * |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 17 | * (C) Copyright 2011 |
| 18 | * Linaro |
| 19 | * Linus Walleij <linus.walleij@linaro.org> |
| 20 | * |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 21 | * See file CREDITS for list of people who contributed to this |
| 22 | * project. |
| 23 | * |
| 24 | * This program is free software; you can redistribute it and/or |
| 25 | * modify it under the terms of the GNU General Public License as |
| 26 | * published by the Free Software Foundation; either version 2 of |
| 27 | * the License, or (at your option) any later version. |
| 28 | * |
| 29 | * This program is distributed in the hope that it will be useful, |
| 30 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 31 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 32 | * GNU General Public License for more details. |
| 33 | * |
| 34 | * You should have received a copy of the GNU General Public License |
| 35 | * along with this program; if not, write to the Free Software |
| 36 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 37 | * MA 02111-1307 USA |
| 38 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 39 | #include <common.h> |
| 40 | #include <pci.h> |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 41 | #include <asm/io.h> |
| 42 | #include "integrator-sc.h" |
| 43 | #include "pci_v3.h" |
| 44 | |
| 45 | #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 |
| 46 | #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 |
| 47 | |
| 48 | /* |
| 49 | * These are in the physical addresses on the CPU side, i.e. |
| 50 | * where we read and write stuff - you don't want to try to |
| 51 | * move these around |
| 52 | */ |
| 53 | #define PHYS_PCI_MEM_BASE 0x40000000 |
| 54 | #define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */ |
| 55 | #define PHYS_PCI_CONFIG_BASE 0x61000000 |
| 56 | #define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */ |
| 57 | #define SZ_256M 0x10000000 |
| 58 | |
| 59 | /* |
| 60 | * These are in the PCI BUS address space |
| 61 | * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor |
| 62 | * we follow the example of the kernel, because that is the address |
| 63 | * range that devices actually use - what would they be doing at |
| 64 | * 0x40000000? |
| 65 | */ |
| 66 | #define PCI_BUS_NONMEM_START 0x00000000 |
| 67 | #define PCI_BUS_NONMEM_SIZE SZ_256M |
| 68 | |
| 69 | #define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE) |
| 70 | #define PCI_BUS_PREMEM_SIZE SZ_256M |
| 71 | |
| 72 | #if PCI_BUS_NONMEM_START & 0x000fffff |
| 73 | #error PCI_BUS_NONMEM_START must be megabyte aligned |
| 74 | #endif |
| 75 | #if PCI_BUS_PREMEM_START & 0x000fffff |
| 76 | #error PCI_BUS_PREMEM_START must be megabyte aligned |
| 77 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 78 | |
| 79 | /* |
| 80 | * Initialize PCI Devices, report devices found. |
| 81 | */ |
| 82 | |
| 83 | #ifndef CONFIG_PCI_PNP |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 84 | #define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */ |
| 85 | #define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */ |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 86 | static struct pci_config_table pci_integrator_config_table[] = { |
| 87 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, |
| 88 | pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
| 89 | PCI_ENET0_MEMADDR, |
| 90 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, |
| 91 | { } |
| 92 | }; |
| 93 | #endif /* CONFIG_PCI_PNP */ |
| 94 | |
| 95 | /* V3 access routines */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 96 | #define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) |
| 97 | #define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o))) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 98 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 99 | #define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) |
| 100 | #define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o))) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 101 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 102 | #define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) |
| 103 | #define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o))) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 104 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 105 | static unsigned long v3_open_config_window(pci_dev_t bdf, int offset) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 106 | { |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 107 | unsigned int address, mapaddress; |
| 108 | unsigned int busnr = PCI_BUS(bdf); |
| 109 | unsigned int devfn = PCI_FUNC(bdf); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 110 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 111 | /* |
| 112 | * Trap out illegal values |
| 113 | */ |
| 114 | if (offset > 255) |
| 115 | BUG(); |
| 116 | if (busnr > 255) |
| 117 | BUG(); |
| 118 | if (devfn > 255) |
| 119 | BUG(); |
| 120 | |
| 121 | if (busnr == 0) { |
| 122 | /* |
| 123 | * Linux calls the thing U-Boot calls "DEV" "SLOT" |
| 124 | * instead, but it's the same 5 bits |
| 125 | */ |
| 126 | int slot = PCI_DEV(bdf); |
| 127 | |
| 128 | /* |
| 129 | * local bus segment so need a type 0 config cycle |
| 130 | * |
| 131 | * build the PCI configuration "address" with one-hot in |
| 132 | * A31-A11 |
| 133 | * |
| 134 | * mapaddress: |
| 135 | * 3:1 = config cycle (101) |
| 136 | * 0 = PCI A1 & A0 are 0 (0) |
| 137 | */ |
| 138 | address = PCI_FUNC(bdf) << 8; |
| 139 | mapaddress = V3_LB_MAP_TYPE_CONFIG; |
| 140 | |
| 141 | if (slot > 12) |
| 142 | /* |
| 143 | * high order bits are handled by the MAP register |
| 144 | */ |
| 145 | mapaddress |= 1 << (slot - 5); |
| 146 | else |
| 147 | /* |
| 148 | * low order bits handled directly in the address |
| 149 | */ |
| 150 | address |= 1 << (slot + 11); |
| 151 | } else { |
| 152 | /* |
| 153 | * not the local bus segment so need a type 1 config cycle |
| 154 | * |
| 155 | * address: |
| 156 | * 23:16 = bus number |
| 157 | * 15:11 = slot number (7:3 of devfn) |
| 158 | * 10:8 = func number (2:0 of devfn) |
| 159 | * |
| 160 | * mapaddress: |
| 161 | * 3:1 = config cycle (101) |
| 162 | * 0 = PCI A1 & A0 from host bus (1) |
| 163 | */ |
| 164 | mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; |
| 165 | address = (busnr << 16) | (devfn << 8); |
| 166 | } |
| 167 | |
| 168 | /* |
| 169 | * Set up base0 to see all 512Mbytes of memory space (not |
| 170 | * prefetchable), this frees up base1 for re-use by |
| 171 | * configuration memory |
| 172 | */ |
| 173 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | |
| 174 | V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); |
| 175 | |
| 176 | /* |
| 177 | * Set up base1/map1 to point into configuration space. |
| 178 | */ |
| 179 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | |
| 180 | V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); |
| 181 | v3_writew(V3_LB_MAP1, mapaddress); |
| 182 | |
| 183 | return PHYS_PCI_CONFIG_BASE + address + offset; |
| 184 | } |
| 185 | |
| 186 | static void v3_close_config_window(void) |
| 187 | { |
| 188 | /* |
| 189 | * Reassign base1 for use by prefetchable PCI memory |
| 190 | */ |
| 191 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | |
| 192 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | |
| 193 | V3_LB_BASE_ENABLE); |
| 194 | v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | |
| 195 | V3_LB_MAP_TYPE_MEM_MULTIPLE); |
| 196 | |
| 197 | /* |
| 198 | * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) |
| 199 | */ |
| 200 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | |
| 201 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); |
| 202 | } |
| 203 | |
| 204 | static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf, |
| 205 | int offset, unsigned char *val) |
| 206 | { |
| 207 | unsigned long addr; |
| 208 | |
| 209 | addr = v3_open_config_window(bdf, offset); |
| 210 | *val = __raw_readb(addr); |
| 211 | v3_close_config_window(); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 212 | return 0; |
| 213 | } |
| 214 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 215 | static int pci_integrator_read__word(struct pci_controller *hose, |
| 216 | pci_dev_t bdf, int offset, |
| 217 | unsigned short *val) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 218 | { |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 219 | unsigned long addr; |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 220 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 221 | addr = v3_open_config_window(bdf, offset); |
| 222 | *val = __raw_readw(addr); |
| 223 | v3_close_config_window(); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 224 | return 0; |
| 225 | } |
| 226 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 227 | static int pci_integrator_read_dword(struct pci_controller *hose, |
| 228 | pci_dev_t bdf, int offset, |
| 229 | unsigned int *val) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 230 | { |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 231 | unsigned long addr; |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 232 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 233 | addr = v3_open_config_window(bdf, offset); |
| 234 | *val = __raw_readl(addr); |
| 235 | v3_close_config_window(); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 236 | return 0; |
| 237 | } |
| 238 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 239 | static int pci_integrator_write_byte(struct pci_controller *hose, |
| 240 | pci_dev_t bdf, int offset, |
| 241 | unsigned char val) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 242 | { |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 243 | unsigned long addr; |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 244 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 245 | addr = v3_open_config_window(bdf, offset); |
| 246 | __raw_writeb((u8)val, addr); |
| 247 | __raw_readb(addr); |
| 248 | v3_close_config_window(); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 249 | return 0; |
| 250 | } |
| 251 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 252 | static int pci_integrator_write_word(struct pci_controller *hose, |
| 253 | pci_dev_t bdf, int offset, |
| 254 | unsigned short val) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 255 | { |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 256 | unsigned long addr; |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 257 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 258 | addr = v3_open_config_window(bdf, offset); |
| 259 | __raw_writew((u8)val, addr); |
| 260 | __raw_readw(addr); |
| 261 | v3_close_config_window(); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 262 | return 0; |
| 263 | } |
| 264 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 265 | static int pci_integrator_write_dword(struct pci_controller *hose, |
| 266 | pci_dev_t bdf, int offset, |
| 267 | unsigned int val) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 268 | { |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 269 | unsigned long addr; |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 270 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 271 | addr = v3_open_config_window(bdf, offset); |
| 272 | __raw_writel((u8)val, addr); |
| 273 | __raw_readl(addr); |
| 274 | v3_close_config_window(); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 275 | return 0; |
| 276 | } |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 277 | |
| 278 | struct pci_controller integrator_hose = { |
| 279 | #ifndef CONFIG_PCI_PNP |
| 280 | config_table: pci_integrator_config_table, |
| 281 | #endif |
| 282 | }; |
| 283 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 284 | void pci_init_board(void) |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 285 | { |
| 286 | volatile int i, j; |
| 287 | struct pci_controller *hose = &integrator_hose; |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 288 | u16 val; |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 289 | |
| 290 | /* setting this register will take the V3 out of reset */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 291 | __raw_writel(SC_PCI_PCIEN, SC_PCI); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 292 | |
| 293 | /* wait a few usecs to settle the device and the PCI bus */ |
| 294 | |
| 295 | for (i = 0; i < 100; i++) |
| 296 | j = i + 1; |
| 297 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 298 | /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ |
| 299 | v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 300 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 301 | /* Wait for the mailbox to settle */ |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 302 | do { |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 303 | v3_writeb(V3_MAIL_DATA, 0xAA); |
| 304 | v3_writeb(V3_MAIL_DATA + 4, 0x55); |
| 305 | } while (v3_readb(V3_MAIL_DATA) != 0xAA || |
| 306 | v3_readb(V3_MAIL_DATA + 4) != 0x55); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 307 | |
| 308 | /* Make sure that V3 register access is not locked, if it is, unlock it */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 309 | if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) |
| 310 | v3_writew(V3_SYSTEM, 0xA05F); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 311 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 312 | /* |
| 313 | * Ensure that the slave accesses from PCI are disabled while we |
| 314 | * setup memory windows |
| 315 | */ |
| 316 | val = v3_readw(V3_PCI_CMD); |
| 317 | val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); |
| 318 | v3_writew(V3_PCI_CMD, val); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 319 | |
| 320 | /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 321 | val = v3_readw(V3_SYSTEM); |
| 322 | val &= ~V3_SYSTEM_M_RST_OUT; |
| 323 | v3_writew(V3_SYSTEM, val); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 324 | |
| 325 | /* Make all accesses from PCI space retry until we're ready for them */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 326 | val = v3_readw(V3_PCI_CFG); |
| 327 | val |= V3_PCI_CFG_M_RETRY_EN; |
| 328 | v3_writew(V3_PCI_CFG, val); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 329 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 330 | /* |
| 331 | * Set up any V3 PCI Configuration Registers that we absolutely have to. |
| 332 | * LB_CFG controls Local Bus protocol. |
| 333 | * Enable LocalBus byte strobes for READ accesses too. |
| 334 | * set bit 7 BE_IMODE and bit 6 BE_OMODE |
| 335 | */ |
| 336 | val = v3_readw(V3_LB_CFG); |
| 337 | val |= 0x0C0; |
| 338 | v3_writew(V3_LB_CFG, val); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 339 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 340 | /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */ |
| 341 | val = v3_readw(V3_PCI_CMD); |
| 342 | val |= V3_COMMAND_M_MASTER_EN; |
| 343 | v3_writew(V3_PCI_CMD, val); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 344 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 345 | /* |
| 346 | * PCI_MAP0 controls where the PCI to CPU memory window is on |
| 347 | * Local Bus |
| 348 | */ |
| 349 | v3_writel(V3_PCI_MAP0, |
| 350 | (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB | |
| 351 | V3_PCI_MAP_M_REG_EN | |
| 352 | V3_PCI_MAP_M_ENABLE)); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 353 | |
| 354 | /* PCI_BASE0 is the PCI address of the start of the window */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 355 | v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 356 | |
| 357 | /* PCI_MAP1 is LOCAL address of the start of the window */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 358 | v3_writel(V3_PCI_MAP1, |
| 359 | (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB | |
| 360 | V3_PCI_MAP_M_REG_EN | |
| 361 | V3_PCI_MAP_M_ENABLE)); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 362 | |
| 363 | /* PCI_BASE1 is the PCI address of the start of the window */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 364 | v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 365 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 366 | /* |
| 367 | * Set up memory the windows from local bus memory into PCI |
| 368 | * configuration, I/O and Memory regions. |
| 369 | * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. |
| 370 | */ |
| 371 | v3_writew(V3_LB_BASE2, |
| 372 | v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE); |
| 373 | v3_writew(V3_LB_MAP2, 0); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 374 | |
| 375 | /* PCI Configuration, use LB_BASE1/LB_MAP1. */ |
| 376 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 377 | /* |
| 378 | * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 |
| 379 | * Map first 256Mbytes as non-prefetchable via BASE0/MAP0 |
| 380 | */ |
| 381 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | |
| 382 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); |
| 383 | v3_writew(V3_LB_MAP0, |
| 384 | v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 385 | |
| 386 | /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 387 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | |
| 388 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | |
| 389 | V3_LB_BASE_ENABLE); |
| 390 | v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | |
| 391 | V3_LB_MAP_TYPE_MEM_MULTIPLE); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 392 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 393 | /* Dump PCI to local address space mappings */ |
| 394 | debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0)); |
| 395 | debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0)); |
| 396 | debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1)); |
| 397 | debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1)); |
| 398 | debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2)); |
| 399 | debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2)); |
| 400 | debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE)); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 401 | |
| 402 | /* |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 403 | * Allow accesses to PCI Configuration space and set up A1, A0 for |
| 404 | * type 1 config cycles |
| 405 | */ |
| 406 | val = v3_readw(V3_PCI_CFG); |
| 407 | val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1); |
| 408 | val |= V3_PCI_CFG_M_AD_LOW0; |
| 409 | v3_writew(V3_PCI_CFG, val); |
| 410 | |
| 411 | /* now we can allow incoming PCI MEMORY accesses */ |
| 412 | val = v3_readw(V3_PCI_CMD); |
| 413 | val |= V3_COMMAND_M_MEM_EN; |
| 414 | v3_writew(V3_PCI_CMD, val); |
| 415 | |
| 416 | /* |
| 417 | * Set RST_OUT to take the PCI bus is out of reset, PCI devices can |
| 418 | * now initialise. |
| 419 | */ |
| 420 | val = v3_readw(V3_SYSTEM); |
| 421 | val |= V3_SYSTEM_M_RST_OUT; |
| 422 | v3_writew(V3_SYSTEM, val); |
| 423 | |
| 424 | /* Lock the V3 system register so that no one else can play with it */ |
| 425 | val = v3_readw(V3_SYSTEM); |
| 426 | val |= V3_SYSTEM_M_LOCK; |
| 427 | v3_writew(V3_SYSTEM, val); |
| 428 | |
| 429 | /* |
| 430 | * Configure and register the PCI hose |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 431 | */ |
| 432 | hose->first_busno = 0; |
| 433 | hose->last_busno = 0xff; |
| 434 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 435 | /* System memory space, window 0 256 MB non-prefetchable */ |
| 436 | pci_set_region(hose->regions + 0, |
| 437 | PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE, |
| 438 | SZ_256M, |
| 439 | PCI_REGION_MEM); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 440 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 441 | /* System memory space, window 1 256 MB prefetchable */ |
| 442 | pci_set_region(hose->regions + 1, |
| 443 | PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M, |
| 444 | SZ_256M, |
| 445 | PCI_REGION_MEM | |
| 446 | PCI_REGION_PREFETCH); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 447 | |
| 448 | /* PCI I/O space */ |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 449 | pci_set_region(hose->regions + 2, |
| 450 | 0x00000000, PHYS_PCI_IO_BASE, 0x01000000, |
| 451 | PCI_REGION_IO); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 452 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 453 | /* PCI Memory - config space */ |
| 454 | pci_set_region(hose->regions + 3, |
| 455 | 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000, |
| 456 | PCI_REGION_MEM); |
| 457 | /* PCI V3 regs */ |
| 458 | pci_set_region(hose->regions + 4, |
| 459 | 0x00000000, PHYS_PCI_V3_BASE, 0x01000000, |
| 460 | PCI_REGION_MEM); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 461 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 462 | hose->region_count = 5; |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 463 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 464 | pci_set_ops(hose, |
| 465 | pci_integrator_read_byte, |
| 466 | pci_integrator_read__word, |
| 467 | pci_integrator_read_dword, |
| 468 | pci_integrator_write_byte, |
| 469 | pci_integrator_write_word, |
| 470 | pci_integrator_write_dword); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 471 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 472 | pci_register_hose(hose); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 473 | |
Linus Walleij | 2458716 | 2012-01-30 13:49:34 +0000 | [diff] [blame^] | 474 | pciauto_config_init(hose); |
| 475 | pciauto_config_device(hose, 0); |
| 476 | |
| 477 | hose->last_busno = pci_hose_scan(hose); |
Jean-Christophe PLAGNIOL-VILLARD | 86baa08 | 2009-05-17 00:58:36 +0200 | [diff] [blame] | 478 | } |