Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
David Brownell | 7a4f511 | 2009-05-15 23:47:12 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2004 Texas Instruments. |
| 4 | * Copyright (C) 2009 David Brownell |
David Brownell | 7a4f511 | 2009-05-15 23:47:12 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Tom Rini | 2f8a6db | 2021-12-14 13:36:40 -0500 | [diff] [blame] | 8 | #include <clock_legacy.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 9 | #include <init.h> |
David Brownell | 7a4f511 | 2009-05-15 23:47:12 +0200 | [diff] [blame] | 10 | #include <asm/arch/hardware.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 11 | #include <asm/global_data.h> |
Sekhar Nori | 91172ba | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 12 | #include <asm/io.h> |
David Brownell | 7a4f511 | 2009-05-15 23:47:12 +0200 | [diff] [blame] | 13 | |
Hadli, Manjunath | 8f5d468 | 2012-02-06 00:30:44 +0000 | [diff] [blame] | 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
David Brownell | 7a4f511 | 2009-05-15 23:47:12 +0200 | [diff] [blame] | 16 | /* offsets from PLL controller base */ |
| 17 | #define PLLC_PLLCTL 0x100 |
| 18 | #define PLLC_PLLM 0x110 |
| 19 | #define PLLC_PREDIV 0x114 |
| 20 | #define PLLC_PLLDIV1 0x118 |
| 21 | #define PLLC_PLLDIV2 0x11c |
| 22 | #define PLLC_PLLDIV3 0x120 |
| 23 | #define PLLC_POSTDIV 0x128 |
| 24 | #define PLLC_BPDIV 0x12c |
| 25 | #define PLLC_PLLDIV4 0x160 |
| 26 | #define PLLC_PLLDIV5 0x164 |
| 27 | #define PLLC_PLLDIV6 0x168 |
Sudhakar Rajashekhara | b7e6843 | 2011-09-03 22:18:04 -0400 | [diff] [blame] | 28 | #define PLLC_PLLDIV7 0x16c |
David Brownell | 7a4f511 | 2009-05-15 23:47:12 +0200 | [diff] [blame] | 29 | #define PLLC_PLLDIV8 0x170 |
| 30 | #define PLLC_PLLDIV9 0x174 |
| 31 | |
Sudhakar Rajashekhara | b7e6843 | 2011-09-03 22:18:04 -0400 | [diff] [blame] | 32 | unsigned int sysdiv[9] = { |
| 33 | PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5, |
| 34 | PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9 |
Sekhar Nori | 91172ba | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | int clk_get(enum davinci_clk_ids id) |
| 38 | { |
| 39 | int pre_div; |
| 40 | int pllm; |
| 41 | int post_div; |
| 42 | int pll_out; |
Sudhakar Rajashekhara | b7e6843 | 2011-09-03 22:18:04 -0400 | [diff] [blame] | 43 | unsigned int pll_base; |
Sekhar Nori | 91172ba | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 44 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 45 | pll_out = CFG_SYS_OSCIN_FREQ; |
Sekhar Nori | 91172ba | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 46 | |
| 47 | if (id == DAVINCI_AUXCLK_CLKID) |
| 48 | goto out; |
| 49 | |
Sudhakar Rajashekhara | b7e6843 | 2011-09-03 22:18:04 -0400 | [diff] [blame] | 50 | if ((id >> 16) == 1) |
| 51 | pll_base = (unsigned int)davinci_pllc1_regs; |
| 52 | else |
| 53 | pll_base = (unsigned int)davinci_pllc0_regs; |
| 54 | |
| 55 | id &= 0xFFFF; |
| 56 | |
Sekhar Nori | 91172ba | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 57 | /* |
| 58 | * Lets keep this simple. Combining operations can result in |
| 59 | * unexpected approximations |
| 60 | */ |
Sudhakar Rajashekhara | b7e6843 | 2011-09-03 22:18:04 -0400 | [diff] [blame] | 61 | pre_div = (readl(pll_base + PLLC_PREDIV) & |
| 62 | DAVINCI_PLLC_DIV_MASK) + 1; |
| 63 | pllm = readl(pll_base + PLLC_PLLM) + 1; |
Sekhar Nori | 91172ba | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 64 | |
| 65 | pll_out /= pre_div; |
| 66 | pll_out *= pllm; |
| 67 | |
| 68 | if (id == DAVINCI_PLLM_CLKID) |
| 69 | goto out; |
| 70 | |
Sudhakar Rajashekhara | b7e6843 | 2011-09-03 22:18:04 -0400 | [diff] [blame] | 71 | post_div = (readl(pll_base + PLLC_POSTDIV) & |
| 72 | DAVINCI_PLLC_DIV_MASK) + 1; |
Sekhar Nori | 91172ba | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 73 | |
| 74 | pll_out /= post_div; |
| 75 | |
| 76 | if (id == DAVINCI_PLLC_CLKID) |
| 77 | goto out; |
| 78 | |
Sudhakar Rajashekhara | b7e6843 | 2011-09-03 22:18:04 -0400 | [diff] [blame] | 79 | pll_out /= (readl(pll_base + sysdiv[id - 1]) & |
| 80 | DAVINCI_PLLC_DIV_MASK) + 1; |
Sekhar Nori | 91172ba | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 81 | |
| 82 | out: |
| 83 | return pll_out; |
| 84 | } |
Laurence Withers | be7d257 | 2012-07-30 23:30:37 +0000 | [diff] [blame] | 85 | |
| 86 | int set_cpu_clk_info(void) |
| 87 | { |
| 88 | gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; |
| 89 | /* DDR PHY uses an x2 input clock */ |
| 90 | gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : |
| 91 | (clk_get(DAVINCI_DDR_CLKID) / 1000000); |
| 92 | gd->bd->bi_dsp_freq = 0; |
| 93 | return 0; |
| 94 | } |
Tom Rini | e4c3ce7 | 2021-12-14 13:36:39 -0500 | [diff] [blame] | 95 | |
| 96 | unsigned long get_board_sys_clk(void) |
| 97 | { |
| 98 | return clk_get(DAVINCI_ARM_CLKID); |
| 99 | } |