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wdenk138ff602004-12-16 15:52:40 +00001/*
Detlev Zundel7b5611c2009-03-30 00:31:34 +02002 * (C) Copyright 2008-2009
3 * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
4 *
5 * (C) Copyright 2009
6 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
wdenk138ff602004-12-16 15:52:40 +00007 *
8 * (C) Copyright 2004
9 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
10 *
11 * (C) Copyright 2004
12 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
13 *
Detlev Zundel7b5611c2009-03-30 00:31:34 +020014 * (C) Copyright 2003-2004
15 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
16 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020017 * SPDX-License-Identifier: GPL-2.0+
wdenk138ff602004-12-16 15:52:40 +000018 */
19
Detlev Zundele979e852009-03-30 00:31:35 +020020#include <asm/io.h>
wdenk138ff602004-12-16 15:52:40 +000021#include <common.h>
22#include <mpc5xxx.h>
23#include <pci.h>
24
Marian Balakowicz5fb6d712007-11-15 13:29:55 +010025#if defined(CONFIG_DDR_MT46V16M16)
wdenk138ff602004-12-16 15:52:40 +000026#include "mt46v16m16-75.h"
Marian Balakowicz5fb6d712007-11-15 13:29:55 +010027#elif defined(CONFIG_SDR_MT48LC16M16A2)
wdenk138ff602004-12-16 15:52:40 +000028#include "mt48lc16m16a2-75.h"
Marian Balakowicz5fb6d712007-11-15 13:29:55 +010029#elif defined(CONFIG_DDR_MT46V32M16)
30#include "mt46v32m16.h"
31#elif defined(CONFIG_DDR_HYB25D512160BF)
32#include "hyb25d512160bf.h"
33#elif defined(CONFIG_DDR_K4H511638C)
34#include "k4h511638c.h"
35#else
36#error "INKA4x0 SDRAM: invalid chip type specified!"
wdenk138ff602004-12-16 15:52:40 +000037#endif
38
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#ifndef CONFIG_SYS_RAMBOOT
wdenk138ff602004-12-16 15:52:40 +000040static void sdram_start (int hi_addr)
41{
Detlev Zundel2344bb82009-03-30 00:31:36 +020042 volatile struct mpc5xxx_sdram *sdram =
43 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
wdenk138ff602004-12-16 15:52:40 +000044 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
45
46 /* unlock mode register */
Detlev Zundel2344bb82009-03-30 00:31:36 +020047 out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000048
49 /* precharge all banks */
Detlev Zundel2344bb82009-03-30 00:31:36 +020050 out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000051
52#if SDRAM_DDR
53 /* set mode register: extended mode */
Detlev Zundel2344bb82009-03-30 00:31:36 +020054 out_be32(&sdram->mode, SDRAM_EMODE);
wdenk138ff602004-12-16 15:52:40 +000055
56 /* set mode register: reset DLL */
Detlev Zundel2344bb82009-03-30 00:31:36 +020057 out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
wdenk138ff602004-12-16 15:52:40 +000058#endif
59
60 /* precharge all banks */
Detlev Zundel2344bb82009-03-30 00:31:36 +020061 out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000062
63 /* auto refresh */
Detlev Zundel2344bb82009-03-30 00:31:36 +020064 out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000065
66 /* set mode register */
Detlev Zundel2344bb82009-03-30 00:31:36 +020067 out_be32(&sdram->mode, SDRAM_MODE);
wdenk138ff602004-12-16 15:52:40 +000068
69 /* normal operation */
Detlev Zundel2344bb82009-03-30 00:31:36 +020070 out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000071}
72#endif
73
74/*
75 * ATTENTION: Although partially referenced initdram does NOT make real use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
wdenk138ff602004-12-16 15:52:40 +000077 * is something else than 0x00000000.
78 */
79
Becky Bruce9973e3c2008-06-09 16:03:40 -050080phys_size_t initdram (int board_type)
wdenk138ff602004-12-16 15:52:40 +000081{
Detlev Zundel2344bb82009-03-30 00:31:36 +020082 volatile struct mpc5xxx_mmap_ctl *mm =
83 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
84 volatile struct mpc5xxx_cdm *cdm =
85 (struct mpc5xxx_cdm *) MPC5XXX_CDM;
86 volatile struct mpc5xxx_sdram *sdram =
87 (struct mpc5xxx_sdram *) MPC5XXX_SDRAM;
wdenk138ff602004-12-16 15:52:40 +000088 ulong dramsize = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#ifndef CONFIG_SYS_RAMBOOT
Marian Balakowiczf23cb342007-11-15 13:24:43 +010090 long test1, test2;
wdenk138ff602004-12-16 15:52:40 +000091
92 /* setup SDRAM chip selects */
Detlev Zundel2344bb82009-03-30 00:31:36 +020093 out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */
94 out_be32(&mm->sdram1, 0x40000000); /* disabled */
wdenk138ff602004-12-16 15:52:40 +000095
96 /* setup config registers */
Detlev Zundel2344bb82009-03-30 00:31:36 +020097 out_be32(&sdram->config1, SDRAM_CONFIG1);
98 out_be32(&sdram->config2, SDRAM_CONFIG2);
wdenk138ff602004-12-16 15:52:40 +000099
100#if SDRAM_DDR
101 /* set tap delay */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200102 out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
wdenk138ff602004-12-16 15:52:40 +0000103#endif
104
105 /* find RAM size using SDRAM CS0 only */
106 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
wdenk138ff602004-12-16 15:52:40 +0000108 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
wdenk138ff602004-12-16 15:52:40 +0000110 if (test1 > test2) {
111 sdram_start(0);
112 dramsize = test1;
113 } else {
114 dramsize = test2;
115 }
116
117 /* memory smaller than 1MB is impossible */
118 if (dramsize < (1 << 20)) {
119 dramsize = 0;
120 }
121
122 /* set SDRAM CS0 size according to the amount of RAM found */
123 if (dramsize > 0) {
Detlev Zundel2344bb82009-03-30 00:31:36 +0200124 out_be32(&mm->sdram0, 0x13 +
125 __builtin_ffs(dramsize >> 20) - 1);
wdenk138ff602004-12-16 15:52:40 +0000126 } else {
Detlev Zundel2344bb82009-03-30 00:31:36 +0200127 out_be32(&mm->sdram0, 0); /* disabled */
wdenk138ff602004-12-16 15:52:40 +0000128 }
129
Detlev Zundel2344bb82009-03-30 00:31:36 +0200130 out_be32(&mm->sdram1, dramsize); /* disabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#else /* CONFIG_SYS_RAMBOOT */
wdenk138ff602004-12-16 15:52:40 +0000132
133 /* retrieve size of memory connected to SDRAM CS0 */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200134 dramsize = in_be32(&mm->sdram0) & 0xFF;
wdenk138ff602004-12-16 15:52:40 +0000135 if (dramsize >= 0x13) {
136 dramsize = (1 << (dramsize - 0x13)) << 20;
137 } else {
138 dramsize = 0;
139 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#endif /* CONFIG_SYS_RAMBOOT */
wdenk138ff602004-12-16 15:52:40 +0000141
wdenk138ff602004-12-16 15:52:40 +0000142 return dramsize;
143}
144
145int checkboard (void)
146{
wdenk08f27272004-12-19 21:39:27 +0000147 puts ("Board: INKA 4X0\n");
wdenk138ff602004-12-16 15:52:40 +0000148 return 0;
149}
150
151void flash_preinit(void)
152{
Detlev Zundel2344bb82009-03-30 00:31:36 +0200153 volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
154
wdenk138ff602004-12-16 15:52:40 +0000155 /*
156 * Now, when we are in RAM, enable flash write
157 * access for detection process.
Detlev Zundel2344bb82009-03-30 00:31:36 +0200158 * Note that CS_BOOT (CS0) cannot be cleared when
wdenk138ff602004-12-16 15:52:40 +0000159 * executing in flash.
160 */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200161 clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
wdenk138ff602004-12-16 15:52:40 +0000162}
wdenk436be292005-01-31 22:09:11 +0000163
wdenk151ab832005-02-24 22:44:16 +0000164int misc_init_f (void)
165{
Detlev Zundel2344bb82009-03-30 00:31:36 +0200166 volatile struct mpc5xxx_gpio *gpio =
167 (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
168 volatile struct mpc5xxx_wu_gpio *wu_gpio =
169 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
170 volatile struct mpc5xxx_gpt *gpt;
Marian Balakowiczf23cb342007-11-15 13:24:43 +0100171 char tmp[10];
wdenka0bdf492005-03-14 13:14:58 +0000172 int i, br;
173
Wolfgang Denkcdb74972010-07-24 21:55:43 +0200174 i = getenv_f("brightness", tmp, sizeof(tmp));
wdenka0bdf492005-03-14 13:14:58 +0000175 br = (i > 0)
176 ? (int) simple_strtoul (tmp, NULL, 10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 : CONFIG_SYS_BRIGHTNESS;
wdenka0bdf492005-03-14 13:14:58 +0000178 if (br > 255)
179 br = 255;
180
wdenkf4733a02005-03-06 01:21:30 +0000181 /* Initialize GPIO output pins.
182 */
wdenk342717f2005-06-27 13:30:03 +0000183 /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200184 for (i = 0; i <= 5; i++) {
185 gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
186 out_be32(&gpt->emsr, 0x34);
187 }
wdenkf4733a02005-03-06 01:21:30 +0000188
wdenka0bdf492005-03-14 13:14:58 +0000189 /* Configure GPT7 as PWM timer, 1kHz, no ints. */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200190 gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
191 out_be32(&gpt->emsr, 0); /* Disable */
192 out_be32(&gpt->cir, 0x020000fe);
193 out_be32(&gpt->pwmcr, (br << 16));
194 out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */
wdenkf4733a02005-03-06 01:21:30 +0000195
196 /* Configure PSC3_6,7 as GPIO output */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200197 setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
198 MPC5XXX_GPIO_SIMPLE_PSC3_7);
199 setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
200 MPC5XXX_GPIO_SIMPLE_PSC3_7);
wdenkf4733a02005-03-06 01:21:30 +0000201
202 /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200203 setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 |
204 MPC5XXX_GPIO_WKUP_7 |
205 MPC5XXX_GPIO_WKUP_PSC3_9);
206 setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 |
207 MPC5XXX_GPIO_WKUP_7 |
208 MPC5XXX_GPIO_WKUP_PSC3_9);
wdenkf4733a02005-03-06 01:21:30 +0000209
wdenk342717f2005-06-27 13:30:03 +0000210 /* Set LR mirror bit because it is low-active */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200211 setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7);
212
213 /* Reset Coral-P graphics controller */
214 setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9);
215
216 /* Enable display backlight */
217 clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
218 setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
219 setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8);
220 setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8);
Detlev Zundele979e852009-03-30 00:31:35 +0200221
222 /*
223 * Configure three wire serial interface to RTC (PSC1_4,
224 * PSC2_4, PSC3_4, PSC3_5)
225 */
226 setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 |
227 MPC5XXX_GPIO_WKUP_PSC2_4);
228 setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 |
229 MPC5XXX_GPIO_WKUP_PSC2_4);
230 clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
231 clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
232 MPC5XXX_GPIO_SINT_PSC3_5);
233 setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
234 MPC5XXX_GPIO_SINT_PSC3_5);
235 setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
236 clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
237
wdenkf4733a02005-03-06 01:21:30 +0000238 return 0;
wdenk151ab832005-02-24 22:44:16 +0000239}
240
wdenkf4733a02005-03-06 01:21:30 +0000241#ifdef CONFIG_PCI
wdenk436be292005-01-31 22:09:11 +0000242static struct pci_controller hose;
243
244extern void pci_mpc5xxx_init(struct pci_controller *);
245
246void pci_init_board(void)
247{
wdenkf4733a02005-03-06 01:21:30 +0000248 pci_mpc5xxx_init(&hose);
wdenk436be292005-01-31 22:09:11 +0000249}
250#endif