blob: fa2e212bb87b49a4c59222e51872124bb82a1849 [file] [log] [blame]
Louis Su30f57472008-07-09 11:01:37 +08001/*
2 * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
3 *
4 * This program is free software; you can distribute it and/or modify
5 * it under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 * This program is distributed in the hope it will be useful, but
8 * WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
14 * USA.
15 */
16
17/*
18 * ========================================================================
19 * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
20 *
21 * The AX88180 Ethernet controller is a high performance and highly
22 * integrated local CPU bus Ethernet controller with embedded 40K bytes
23 * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
24 * embedded systems.
25 * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
26 * controller that supports both MII and RGMII interfaces and is
27 * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
28 *
29 * Please visit ASIX's web site (http://www.asix.com.tw) for more
30 * details.
31 *
32 * Module Name : ax88180.c
33 * Date : 2008-07-07
34 * History
35 * 09/06/2006 : New release for AX88180 US2 chip.
36 * 07/07/2008 : Fix up the coding style and using inline functions
37 * instead of macros
38 * ========================================================================
39 */
40#include <common.h>
41#include <command.h>
42#include <net.h>
43#include <malloc.h>
Mike Frysingerf9abdfe2010-05-10 16:47:36 -040044#include <linux/mii.h>
Louis Su30f57472008-07-09 11:01:37 +080045#include "ax88180.h"
46
47/*
48 * ===========================================================================
49 * Local SubProgram Declaration
50 * ===========================================================================
51 */
52static void ax88180_rx_handler (struct eth_device *dev);
53static int ax88180_phy_initial (struct eth_device *dev);
Hoan Hoangbb7336a2010-05-10 16:09:35 -040054static void ax88180_media_config (struct eth_device *dev);
55static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev);
56static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev);
Louis Su30f57472008-07-09 11:01:37 +080057static unsigned short ax88180_mdio_read (struct eth_device *dev,
58 unsigned long regaddr);
59static void ax88180_mdio_write (struct eth_device *dev,
60 unsigned long regaddr, unsigned short regdata);
61
62/*
63 * ===========================================================================
64 * Local SubProgram Bodies
65 * ===========================================================================
66 */
67static int ax88180_mdio_check_complete (struct eth_device *dev)
68{
69 int us_cnt = 10000;
70 unsigned short tmpval;
71
72 /* MDIO read/write should not take more than 10 ms */
73 while (--us_cnt) {
74 tmpval = INW (dev, MDIOCTRL);
75 if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
76 break;
77 }
78
79 return us_cnt;
80}
81
82static unsigned short
83ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
84{
85 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
86 unsigned long tmpval = 0;
87
88 OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
89
90 if (ax88180_mdio_check_complete (dev))
91 tmpval = INW (dev, MDIODP);
92 else
93 printf ("Failed to read PHY register!\n");
94
95 return (unsigned short)(tmpval & 0xFFFF);
96}
97
98static void
99ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
100 unsigned short regdata)
101{
102 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
103
104 OUTW (dev, regdata, MDIODP);
105
106 OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
107
108 if (!ax88180_mdio_check_complete (dev))
109 printf ("Failed to write PHY register!\n");
110}
111
112static int ax88180_phy_reset (struct eth_device *dev)
113{
114 unsigned short delay_cnt = 500;
115
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400116 ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
Louis Su30f57472008-07-09 11:01:37 +0800117
118 /* Wait for the reset to complete, or time out (500 ms) */
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400119 while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
Louis Su30f57472008-07-09 11:01:37 +0800120 udelay (1000);
121 if (--delay_cnt == 0) {
122 printf ("Failed to reset PHY!\n");
123 return -1;
124 }
125 }
126
127 return 0;
128}
129
130static void ax88180_mac_reset (struct eth_device *dev)
131{
132 unsigned long tmpval;
133 unsigned char i;
134
135 struct {
136 unsigned short offset, value;
137 } program_seq[] = {
138 {
139 MISC, MISC_NORMAL}, {
140 RXINDICATOR, DEFAULT_RXINDICATOR}, {
141 TXCMD, DEFAULT_TXCMD}, {
142 TXBS, DEFAULT_TXBS}, {
143 TXDES0, DEFAULT_TXDES0}, {
144 TXDES1, DEFAULT_TXDES1}, {
145 TXDES2, DEFAULT_TXDES2}, {
146 TXDES3, DEFAULT_TXDES3}, {
147 TXCFG, DEFAULT_TXCFG}, {
148 MACCFG2, DEFAULT_MACCFG2}, {
149 MACCFG3, DEFAULT_MACCFG3}, {
150 TXLEN, DEFAULT_TXLEN}, {
151 RXBTHD0, DEFAULT_RXBTHD0}, {
152 RXBTHD1, DEFAULT_RXBTHD1}, {
153 RXFULTHD, DEFAULT_RXFULTHD}, {
154 DOGTHD0, DEFAULT_DOGTHD0}, {
155 DOGTHD1, DEFAULT_DOGTHD1},};
156
157 OUTW (dev, MISC_RESET_MAC, MISC);
158 tmpval = INW (dev, MISC);
159
160 for (i = 0; i < (sizeof (program_seq) / sizeof (program_seq[0])); i++)
161 OUTW (dev, program_seq[i].value, program_seq[i].offset);
162}
163
164static int ax88180_poll_tx_complete (struct eth_device *dev)
165{
166 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
167 unsigned long tmpval, txbs_txdp;
168 int TimeOutCnt = 10000;
169
170 txbs_txdp = 1 << priv->NextTxDesc;
171
172 while (TimeOutCnt--) {
173
174 tmpval = INW (dev, TXBS);
175
176 if ((tmpval & txbs_txdp) == 0)
177 break;
178
179 udelay (100);
180 }
181
182 if (TimeOutCnt)
183 return 0;
184 else
185 return -TimeOutCnt;
186}
187
188static void ax88180_rx_handler (struct eth_device *dev)
189{
190 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
191 unsigned long data_size;
192 unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
193 int i;
194#if defined (CONFIG_DRIVER_AX88180_16BIT)
195 unsigned short *rxdata = (unsigned short *)NetRxPackets[0];
196#else
197 unsigned long *rxdata = (unsigned long *)NetRxPackets[0];
198#endif
199 unsigned short count;
200
201 rxcurt_ptr = INW (dev, RXCURT);
202 rxbound_ptr = INW (dev, RXBOUND);
203 next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
204
205 debug ("ax88180: RX original RXBOUND=0x%04x,"
206 " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
207
208 while (next_ptr != rxcurt_ptr) {
209
210 OUTW (dev, RX_START_READ, RXINDICATOR);
211
212 data_size = READ_RXBUF (dev) & 0xFFFF;
213
214 if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
215
216 OUTW (dev, RX_STOP_READ, RXINDICATOR);
217
218 ax88180_mac_reset (dev);
219 printf ("ax88180: Invalid Rx packet length!"
220 " (len=0x%04lx)\n", data_size);
221
222 debug ("ax88180: RX RXBOUND=0x%04x,"
223 "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
224 return;
225 }
226
227 rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
228 rxbound_ptr &= RX_PAGE_NUM_MASK;
229
230 /* Comput access times */
231 count = (data_size + priv->PadSize) >> priv->BusWidth;
232
233 for (i = 0; i < count; i++) {
234 *(rxdata + i) = READ_RXBUF (dev);
235 }
236
237 OUTW (dev, RX_STOP_READ, RXINDICATOR);
238
239 /* Pass the packet up to the protocol layers. */
240 NetReceive (NetRxPackets[0], data_size);
241
242 OUTW (dev, rxbound_ptr, RXBOUND);
243
244 rxcurt_ptr = INW (dev, RXCURT);
245 rxbound_ptr = INW (dev, RXBOUND);
246 next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
247
248 debug ("ax88180: RX updated RXBOUND=0x%04x,"
249 "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
250 }
251
252 return;
253}
254
255static int ax88180_phy_initial (struct eth_device *dev)
256{
257 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
258 unsigned long tmp_regval;
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400259 unsigned short phyaddr;
Louis Su30f57472008-07-09 11:01:37 +0800260
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400261 /* Search for first avaliable PHY chipset */
262#ifdef CONFIG_PHY_ADDR
263 phyaddr = CONFIG_PHY_ADDR;
264#else
265 for (phyaddr = 0; phyaddr < 32; ++phyaddr)
266#endif
267 {
268 priv->PhyAddr = phyaddr;
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400269 priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
Louis Su30f57472008-07-09 11:01:37 +0800270
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400271 switch (priv->PhyID0) {
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400272 case MARVELL_88E1111_PHYSID0:
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400273 debug("ax88180: Found Marvell 88E1111 PHY."
274 " (PHY Addr=0x%x)\n", priv->PhyAddr);
Louis Su30f57472008-07-09 11:01:37 +0800275
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400276 tmp_regval = ax88180_mdio_read(dev, M88_EXT_SSR);
277 if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE) {
278 ax88180_mdio_write(dev, M88_EXT_SCR, DEFAULT_EXT_SCR);
279 if (ax88180_phy_reset(dev) < 0)
280 return 0;
281 ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
282 }
Louis Su30f57472008-07-09 11:01:37 +0800283
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400284 return 1;
Louis Su30f57472008-07-09 11:01:37 +0800285
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400286 case CICADA_CIS8201_PHYSID0:
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400287 debug("ax88180: Found CICADA CIS8201 PHY"
288 " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
Louis Su30f57472008-07-09 11:01:37 +0800289
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400290 ax88180_mdio_write(dev, CIS_IMR,
Louis Su30f57472008-07-09 11:01:37 +0800291 (CIS_INT_ENABLE | LINK_CHANGE_INT));
292
293 /* Set CIS_SMI_PRIORITY bit before force the media mode */
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400294 tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS);
Louis Su30f57472008-07-09 11:01:37 +0800295 tmp_regval &= ~CIS_SMI_PRIORITY;
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400296 ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval);
297
298 return 1;
299
300 case 0xffff:
301 /* No PHY at this addr */
302 break;
303
304 default:
305 printf("ax88180: Unknown PHY chipset %#x at addr %#x\n",
306 priv->PhyID0, priv->PhyAddr);
307 break;
Louis Su30f57472008-07-09 11:01:37 +0800308 }
309 }
310
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400311 printf("ax88180: Unknown PHY chipset!!\n");
312 return 0;
Louis Su30f57472008-07-09 11:01:37 +0800313}
314
Hoan Hoangbb7336a2010-05-10 16:09:35 -0400315static void ax88180_media_config (struct eth_device *dev)
Louis Su30f57472008-07-09 11:01:37 +0800316{
317 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
318 unsigned long bmcr_val, bmsr_val;
319 unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
320 unsigned long RealMediaMode;
321 int i;
322
323 /* Waiting 2 seconds for PHY link stable */
324 for (i = 0; i < 20000; i++) {
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400325 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
326 if (bmsr_val & BMSR_LSTATUS) {
Louis Su30f57472008-07-09 11:01:37 +0800327 break;
328 }
329 udelay (100);
330 }
331
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400332 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
Louis Su30f57472008-07-09 11:01:37 +0800333 debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
334
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400335 if (bmsr_val & BMSR_LSTATUS) {
336 bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
Louis Su30f57472008-07-09 11:01:37 +0800337
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400338 if (bmcr_val & BMCR_ANENABLE) {
Louis Su30f57472008-07-09 11:01:37 +0800339
340 /*
341 * Waiting for Auto-negotiation completion, this may
342 * take up to 5 seconds.
343 */
344 debug ("ax88180: Auto-negotiation is "
345 "enabled. Waiting for NWay completion..\n");
346 for (i = 0; i < 50000; i++) {
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400347 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
348 if (bmsr_val & BMSR_ANEGCOMPLETE) {
Louis Su30f57472008-07-09 11:01:37 +0800349 break;
350 }
351 udelay (100);
352 }
353 } else
354 debug ("ax88180: Auto-negotiation is disabled.\n");
355
356 debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
357 (unsigned int)bmcr_val, (unsigned int)bmsr_val);
358
359 /* Get real media mode here */
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400360 switch (priv->PhyID0) {
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400361 case MARVELL_88E1111_PHYSID0:
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400362 RealMediaMode = get_MarvellPHY_media_mode(dev);
363 break;
Mike Frysingerf9abdfe2010-05-10 16:47:36 -0400364 case CICADA_CIS8201_PHYSID0:
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400365 RealMediaMode = get_CicadaPHY_media_mode(dev);
366 break;
367 default:
Louis Su30f57472008-07-09 11:01:37 +0800368 RealMediaMode = MEDIA_1000FULL;
Mike Frysinger141ab7a2010-05-10 16:10:00 -0400369 break;
Louis Su30f57472008-07-09 11:01:37 +0800370 }
371
372 priv->LinkState = INS_LINK_UP;
373
374 switch (RealMediaMode) {
375 case MEDIA_1000FULL:
376 debug ("ax88180: 1000Mbps Full-duplex mode.\n");
377 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
378 maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
379 maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
380 FULLDUPLEX | DEFAULT_MACCFG1;
381 break;
382
383 case MEDIA_1000HALF:
384 debug ("ax88180: 1000Mbps Half-duplex mode.\n");
385 rxcfg_val = DEFAULT_RXCFG;
386 maccfg0_val = DEFAULT_MACCFG0;
387 maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
388 break;
389
390 case MEDIA_100FULL:
391 debug ("ax88180: 100Mbps Full-duplex mode.\n");
392 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
393 maccfg0_val = SPEED100 | TXFLOW_ENABLE
394 | DEFAULT_MACCFG0;
395 maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
396 break;
397
398 case MEDIA_100HALF:
399 debug ("ax88180: 100Mbps Half-duplex mode.\n");
400 rxcfg_val = DEFAULT_RXCFG;
401 maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
402 maccfg1_val = DEFAULT_MACCFG1;
403 break;
404
405 case MEDIA_10FULL:
406 debug ("ax88180: 10Mbps Full-duplex mode.\n");
407 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
408 maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
409 maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
410 break;
411
412 case MEDIA_10HALF:
413 debug ("ax88180: 10Mbps Half-duplex mode.\n");
414 rxcfg_val = DEFAULT_RXCFG;
415 maccfg0_val = DEFAULT_MACCFG0;
416 maccfg1_val = DEFAULT_MACCFG1;
417 break;
418 default:
419 debug ("ax88180: Unknow media mode.\n");
420 rxcfg_val = DEFAULT_RXCFG;
421 maccfg0_val = DEFAULT_MACCFG0;
422 maccfg1_val = DEFAULT_MACCFG1;
423
424 priv->LinkState = INS_LINK_DOWN;
425 break;
426 }
427
428 } else {
429 rxcfg_val = DEFAULT_RXCFG;
430 maccfg0_val = DEFAULT_MACCFG0;
431 maccfg1_val = DEFAULT_MACCFG1;
432
433 priv->LinkState = INS_LINK_DOWN;
434 }
435
436 OUTW (dev, rxcfg_val, RXCFG);
437 OUTW (dev, maccfg0_val, MACCFG0);
438 OUTW (dev, maccfg1_val, MACCFG1);
439
440 return;
441}
442
Hoan Hoangbb7336a2010-05-10 16:09:35 -0400443static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev)
Louis Su30f57472008-07-09 11:01:37 +0800444{
445 unsigned long m88_ssr;
446 unsigned long MediaMode;
447
448 m88_ssr = ax88180_mdio_read (dev, M88_SSR);
449 switch (m88_ssr & SSR_MEDIA_MASK) {
450 case SSR_1000FULL:
451 MediaMode = MEDIA_1000FULL;
452 break;
453 case SSR_1000HALF:
454 MediaMode = MEDIA_1000HALF;
455 break;
456 case SSR_100FULL:
457 MediaMode = MEDIA_100FULL;
458 break;
459 case SSR_100HALF:
460 MediaMode = MEDIA_100HALF;
461 break;
462 case SSR_10FULL:
463 MediaMode = MEDIA_10FULL;
464 break;
465 case SSR_10HALF:
466 MediaMode = MEDIA_10HALF;
467 break;
468 default:
469 MediaMode = MEDIA_UNKNOWN;
470 break;
471 }
472
473 return MediaMode;
474}
475
Hoan Hoangbb7336a2010-05-10 16:09:35 -0400476static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev)
Louis Su30f57472008-07-09 11:01:37 +0800477{
478 unsigned long tmp_regval;
479 unsigned long MediaMode;
480
481 tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
482 switch (tmp_regval & CIS_MEDIA_MASK) {
483 case CIS_1000FULL:
484 MediaMode = MEDIA_1000FULL;
485 break;
486 case CIS_1000HALF:
487 MediaMode = MEDIA_1000HALF;
488 break;
489 case CIS_100FULL:
490 MediaMode = MEDIA_100FULL;
491 break;
492 case CIS_100HALF:
493 MediaMode = MEDIA_100HALF;
494 break;
495 case CIS_10FULL:
496 MediaMode = MEDIA_10FULL;
497 break;
498 case CIS_10HALF:
499 MediaMode = MEDIA_10HALF;
500 break;
501 default:
502 MediaMode = MEDIA_UNKNOWN;
503 break;
504 }
505
506 return MediaMode;
507}
508
509static void ax88180_halt (struct eth_device *dev)
510{
511 /* Disable AX88180 TX/RX functions */
512 OUTW (dev, WAKEMOD, CMD);
513}
514
515static int ax88180_init (struct eth_device *dev, bd_t * bd)
516{
517 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
518 unsigned short tmp_regval;
519
520 ax88180_mac_reset (dev);
521
522 /* Disable interrupt */
523 OUTW (dev, CLEAR_IMR, IMR);
524
525 /* Disable AX88180 TX/RX functions */
526 OUTW (dev, WAKEMOD, CMD);
527
528 /* Fill the MAC address */
529 tmp_regval =
530 dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
531 OUTW (dev, tmp_regval, MACID0);
532
533 tmp_regval =
534 dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
535 OUTW (dev, tmp_regval, MACID1);
536
537 tmp_regval =
538 dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
539 OUTW (dev, tmp_regval, MACID2);
540
Hoan Hoangbb7336a2010-05-10 16:09:35 -0400541 ax88180_media_config (dev);
Louis Su30f57472008-07-09 11:01:37 +0800542
543 OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
544
545 /* Initial variables here */
546 priv->FirstTxDesc = TXDP0;
547 priv->NextTxDesc = TXDP0;
548
549 /* Check if there is any invalid interrupt status and clear it. */
550 OUTW (dev, INW (dev, ISR), ISR);
551
552 /* Start AX88180 TX/RX functions */
553 OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
554
555 return 0;
556}
557
558/* Get a data block via Ethernet */
559static int ax88180_recv (struct eth_device *dev)
560{
561 unsigned short ISR_Status;
562 unsigned short tmp_regval;
563
564 /* Read and check interrupt status here. */
565 ISR_Status = INW (dev, ISR);
566
567 while (ISR_Status) {
568 /* Clear the interrupt status */
569 OUTW (dev, ISR_Status, ISR);
570
571 debug ("\nax88180: The interrupt status = 0x%04x\n",
572 ISR_Status);
573
574 if (ISR_Status & ISR_PHY) {
575 /* Read ISR register once to clear PHY interrupt bit */
576 tmp_regval = ax88180_mdio_read (dev, M88_ISR);
Hoan Hoangbb7336a2010-05-10 16:09:35 -0400577 ax88180_media_config (dev);
Louis Su30f57472008-07-09 11:01:37 +0800578 }
579
580 if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
581 ax88180_rx_handler (dev);
582 }
583
584 /* Read and check interrupt status again */
585 ISR_Status = INW (dev, ISR);
586 }
587
588 return 0;
589}
590
591/* Send a data block via Ethernet. */
592static int
593ax88180_send (struct eth_device *dev, volatile void *packet, int length)
594{
595 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
596 unsigned short TXDES_addr;
597 unsigned short txcmd_txdp, txbs_txdp;
598 unsigned short tmp_data;
599 int i;
600#if defined (CONFIG_DRIVER_AX88180_16BIT)
601 volatile unsigned short *txdata = (volatile unsigned short *)packet;
602#else
603 volatile unsigned long *txdata = (volatile unsigned long *)packet;
604#endif
605 unsigned short count;
606
607 if (priv->LinkState != INS_LINK_UP) {
608 return 0;
609 }
610
611 priv->FirstTxDesc = priv->NextTxDesc;
612 txbs_txdp = 1 << priv->FirstTxDesc;
613
614 debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
615
616 txcmd_txdp = priv->FirstTxDesc << 13;
617 TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
618
619 OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
620
621 /* Comput access times */
622 count = (length + priv->PadSize) >> priv->BusWidth;
623
624 for (i = 0; i < count; i++) {
625 WRITE_TXBUF (dev, *(txdata + i));
626 }
627
628 OUTW (dev, txcmd_txdp | length, TXCMD);
629 OUTW (dev, txbs_txdp, TXBS);
630 OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
631
632 priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
633
634 /*
635 * Check the available transmit descriptor, if we had exhausted all
636 * transmit descriptor ,then we have to wait for at least one free
637 * descriptor
638 */
639 txbs_txdp = 1 << priv->NextTxDesc;
640 tmp_data = INW (dev, TXBS);
641
642 if (tmp_data & txbs_txdp) {
643 if (ax88180_poll_tx_complete (dev) < 0) {
644 ax88180_mac_reset (dev);
645 priv->FirstTxDesc = TXDP0;
646 priv->NextTxDesc = TXDP0;
647 printf ("ax88180: Transmit time out occurred!\n");
648 }
649 }
650
651 return 0;
652}
653
654static void ax88180_read_mac_addr (struct eth_device *dev)
655{
656 unsigned short macid0_val, macid1_val, macid2_val;
657 unsigned short tmp_regval;
658 unsigned short i;
659
660 /* Reload MAC address from EEPROM */
661 OUTW (dev, RELOAD_EEPROM, PROMCTRL);
662
663 /* Waiting for reload eeprom completion */
664 for (i = 0; i < 500; i++) {
665 tmp_regval = INW (dev, PROMCTRL);
666 if ((tmp_regval & RELOAD_EEPROM) == 0)
667 break;
668 udelay (1000);
669 }
670
671 /* Get MAC addresses */
672 macid0_val = INW (dev, MACID0);
673 macid1_val = INW (dev, MACID1);
674 macid2_val = INW (dev, MACID2);
675
676 if (((macid0_val | macid1_val | macid2_val) != 0) &&
677 ((macid0_val & 0x01) == 0)) {
678 dev->enetaddr[0] = (unsigned char)macid0_val;
679 dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
680 dev->enetaddr[2] = (unsigned char)macid1_val;
681 dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
682 dev->enetaddr[4] = (unsigned char)macid2_val;
683 dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
684 }
685}
686
687/*
688===========================================================================
689<<<<<< Exported SubProgram Bodies >>>>>>
690===========================================================================
691*/
692int ax88180_initialize (bd_t * bis)
693{
694 struct eth_device *dev;
695 struct ax88180_private *priv;
696
697 dev = (struct eth_device *)malloc (sizeof *dev);
698
699 if (NULL == dev)
700 return 0;
701
702 memset (dev, 0, sizeof *dev);
703
704 priv = (struct ax88180_private *)malloc (sizeof (*priv));
705
706 if (NULL == priv)
707 return 0;
708
709 memset (priv, 0, sizeof *priv);
710
711 sprintf (dev->name, "ax88180");
712 dev->iobase = AX88180_BASE;
713 dev->priv = priv;
714 dev->init = ax88180_init;
715 dev->halt = ax88180_halt;
716 dev->send = ax88180_send;
717 dev->recv = ax88180_recv;
718
719 priv->BusWidth = BUS_WIDTH_32;
720 priv->PadSize = 3;
721#if defined (CONFIG_DRIVER_AX88180_16BIT)
722 OUTW (dev, (START_BASE >> 8), BASE);
723 OUTW (dev, DECODE_EN, DECODE);
724
725 priv->BusWidth = BUS_WIDTH_16;
726 priv->PadSize = 1;
727#endif
728
729 ax88180_mac_reset (dev);
730
731 /* Disable interrupt */
732 OUTW (dev, CLEAR_IMR, IMR);
733
734 /* Disable AX88180 TX/RX functions */
735 OUTW (dev, WAKEMOD, CMD);
736
737 ax88180_read_mac_addr (dev);
738
739 eth_register (dev);
740
741 return ax88180_phy_initial (dev);
742
743}