blob: 5300650e1910173f6bd125ce03b2a7807919e0de [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kever Yangaa89b552016-08-12 17:58:12 +08002/*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
Kever Yangaa89b552016-08-12 17:58:12 +08004 */
5#include <asm/io.h>
Kever Yang15f09a12019-03-28 11:01:23 +08006#include <asm/arch-rockchip/hardware.h>
Kever Yang070e48b2019-03-29 09:09:03 +08007#include <asm/arch-rockchip/grf_rk3288.h>
Kever Yangaa89b552016-08-12 17:58:12 +08008
Kever Yang070e48b2019-03-29 09:09:03 +08009#define GRF_BASE 0xff770000
Kever Yangaa89b552016-08-12 17:58:12 +080010
11int arch_cpu_init(void)
12{
Kever Yangccab9e72019-07-09 21:58:43 +080013#ifdef CONFIG_SPL_BUILD
14 configure_l2ctlr();
15#else
Kever Yangaa89b552016-08-12 17:58:12 +080016 /* We do some SoC one time setting here. */
Kever Yang070e48b2019-03-29 09:09:03 +080017 struct rk3288_grf * const grf = (void *)GRF_BASE;
Kever Yangaa89b552016-08-12 17:58:12 +080018
19 /* Use rkpwm by default */
Kever Yang070e48b2019-03-29 09:09:03 +080020 rk_setreg(&grf->soc_con2, 1 << 0);
Kever Yangccab9e72019-07-09 21:58:43 +080021#endif
Kever Yangaa89b552016-08-12 17:58:12 +080022
23 return 0;
24}
Kever Yange83e8852019-03-29 09:09:04 +080025
26#ifdef CONFIG_DEBUG_UART_BOARD_INIT
27void board_debug_uart_init(void)
28{
29 /* Enable early UART on the RK3288 */
30 struct rk3288_grf * const grf = (void *)GRF_BASE;
31
32 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
33 GPIO7C6_MASK << GPIO7C6_SHIFT,
34 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
35 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
36}
37#endif