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Marian Balakowicze6f2e902005-10-11 19:09:42 +02001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * TQM8349 board configuration file
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
Marian Balakowicze6f2e902005-10-11 19:09:42 +020031/*
32 * High Level Configuration Options
33 */
34#define CONFIG_E300 1 /* E300 Family */
Peter Tyser0f898602009-05-22 17:23:24 -050035#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050036#define CONFIG_MPC834x 1 /* MPC834x specific */
Timur Tabi9ca880a2006-10-31 21:23:16 -060037#define CONFIG_MPC8349 1 /* MPC8349 specific */
Marian Balakowicze6f2e902005-10-11 19:09:42 +020038#define CONFIG_TQM834X 1 /* TQM834X board specific */
39
40/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_IMMR 0xff400000
Marian Balakowicze6f2e902005-10-11 19:09:42 +020042
43/* System clock. Primary input clock when in PCI host mode */
44#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
45
46/*
47 * Local Bus LCRR
48 * LCRR: DLL bypass, Clock divider is 8
49 *
50 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
51 *
52 * External Local Bus rate is
53 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
54 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
Marian Balakowicze6f2e902005-10-11 19:09:42 +020056
57/* board pre init: do not call, nothing to do */
58#undef CONFIG_BOARD_EARLY_INIT_F
59
60/* detect the number of flash banks */
61#define CONFIG_BOARD_EARLY_INIT_R
62
63/*
64 * DDR Setup
65 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
67#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
68#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Marian Balakowicze6f2e902005-10-11 19:09:42 +020069#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
70#undef CONFIG_DDR_ECC /* only for ECC DDR module */
71#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
74#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
75#define CONFIG_SYS_MEMTEST_END 0x00100000
Marian Balakowicze6f2e902005-10-11 19:09:42 +020076
77/*
78 * FLASH on the Local Bus
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Wolfgang Denka3455c02009-05-15 09:19:52 +020081#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#undef CONFIG_SYS_FLASH_CHECKSUM
83#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
84#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
Wolfgang Denka3455c02009-05-15 09:19:52 +020085#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
86#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Marian Balakowicze6f2e902005-10-11 19:09:42 +020087
88/*
89 * FLASH bank number detection
90 */
91
92/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
Marian Balakowicze6f2e902005-10-11 19:09:42 +020094 * banks has to be determined at runtime and stored in a gloabl variable
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
96 * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
Marian Balakowicze6f2e902005-10-11 19:09:42 +020097 * should be made sufficiently large to accomodate the number of banks that
Wolfgang Denkf013dac2005-12-04 00:40:34 +010098 * might actually be detected. Since most (all?) Flash related functions use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200100 * defined as tqm834x_num_flash_banks.
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100103#ifndef __ASSEMBLY__
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200104extern int tqm834x_num_flash_banks;
105#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200109
110/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200112 BR_MS_GPCM | BR_PS_32 | BR_V)
113
114/* FLASH timing (0x0000_0c54) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200116 OR_GPCM_SCY_5 | OR_GPCM_TRLX)
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200125
126/* disable remaining mappings */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_BR1_PRELIM 0x00000000
128#define CONFIG_SYS_OR1_PRELIM 0x00000000
129#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
130#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_BR2_PRELIM 0x00000000
133#define CONFIG_SYS_OR2_PRELIM 0x00000000
134#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
135#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BR3_PRELIM 0x00000000
138#define CONFIG_SYS_OR3_PRELIM 0x00000000
139#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
140#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200141
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200142/*
143 * Monitor config
144 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
Wolfgang Denk4681e672009-05-14 23:18:34 +0200148# define CONFIG_SYS_RAMBOOT
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200149#else
Wolfgang Denk4681e672009-05-14 23:18:34 +0200150# undef CONFIG_SYS_RAMBOOT
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200151#endif
152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_INIT_RAM_LOCK 1
154#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
155#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
158#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
159#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200160
Wolfgang Denk929b79a2009-05-14 23:18:33 +0200161#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
162#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200163
164/*
165 * Serial Port
166 */
167#define CONFIG_CONS_INDEX 1
168#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_NS16550
170#define CONFIG_SYS_NS16550_SERIAL
171#define CONFIG_SYS_NS16550_REG_SIZE 1
172#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BAUDRATE_TABLE \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200175 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
178#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200179
180/*
181 * I2C
182 */
183#define CONFIG_HARD_I2C /* I2C with hardware support */
184#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Timur Tabibe5e6182006-11-03 19:15:00 -0600185#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
187#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
188#define CONFIG_SYS_I2C_OFFSET 0x3000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200189
190/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
192#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
193#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
194#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
195#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200196
197/* I2C RTC */
198#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200200
201/* I2C SYSMON (LM75) */
202#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
203#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_DTT_MAX_TEMP 70
205#define CONFIG_SYS_DTT_LOW_TEMP -30
206#define CONFIG_SYS_DTT_HYSTERESIS 3
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200207
208/*
209 * TSEC
210 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200211#define CONFIG_TSEC_ENET /* tsec ethernet support */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200212#define CONFIG_MII
213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_TSEC1_OFFSET 0x24000
215#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
216#define CONFIG_SYS_TSEC2_OFFSET 0x25000
217#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200218
219#if defined(CONFIG_TSEC_ENET)
220
221#ifndef CONFIG_NET_MULTI
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200222#define CONFIG_NET_MULTI
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200223#endif
224
Kim Phillips255a35772007-05-16 16:52:19 -0500225#define CONFIG_TSEC1 1
226#define CONFIG_TSEC1_NAME "TSEC0"
227#define CONFIG_TSEC2 1
228#define CONFIG_TSEC2_NAME "TSEC1"
Wolfgang Denkb6f84352005-12-01 01:17:24 +0100229#define TSEC1_PHY_ADDR 2
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200230#define TSEC2_PHY_ADDR 1
231#define TSEC1_PHYIDX 0
232#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500233#define TSEC1_FLAGS TSEC_GIGABIT
234#define TSEC2_FLAGS TSEC_GIGABIT
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200235
236/* Options are: TSEC[0-1] */
237#define CONFIG_ETHPRIME "TSEC0"
238
239#endif /* CONFIG_TSEC_ENET */
240
241/*
242 * General PCI
243 * Addresses are mapped 1-1.
244 */
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200245#define CONFIG_PCI
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200246
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200247#if defined(CONFIG_PCI)
248
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200249#define CONFIG_PCI_PNP /* do pci plug-and-play */
250#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200251
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200252/* PCI1 host bridge */
Kim Phillips27c52482009-08-21 16:31:20 -0500253#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
Kim Phillips9993e192009-07-18 18:42:13 -0500255#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
256#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
257#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
258#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
260#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
261#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200262
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200263#undef CONFIG_EEPRO100
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200264#define CONFIG_EEPRO100
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200265#undef CONFIG_TULIP
266
267#if !defined(CONFIG_PCI_PNP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
269 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200270 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200271#endif
272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200274
275#endif /* CONFIG_PCI */
276
277/*
278 * Environment
279 */
Wolfgang Denk4681e672009-05-14 23:18:34 +0200280#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denk929b79a2009-05-14 23:18:33 +0200281#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
282#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
283#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
284#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
285#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
286
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200287#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Wolfgang Denk929b79a2009-05-14 23:18:33 +0200288#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200289
Jon Loeliger26946902007-07-04 22:30:50 -0500290/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500291 * BOOTP options
292 */
293#define CONFIG_BOOTP_BOOTFILESIZE
294#define CONFIG_BOOTP_BOOTPATH
295#define CONFIG_BOOTP_GATEWAY
296#define CONFIG_BOOTP_HOSTNAME
297
298
299/*
Jon Loeliger26946902007-07-04 22:30:50 -0500300 * Command line configuration.
301 */
302#include <config_cmd_default.h>
303
Wolfgang Denk4681e672009-05-14 23:18:34 +0200304#define CONFIG_CMD_ASKENV
Jon Loeliger26946902007-07-04 22:30:50 -0500305#define CONFIG_CMD_DATE
Wolfgang Denk4681e672009-05-14 23:18:34 +0200306#define CONFIG_CMD_DHCP
Jon Loeliger26946902007-07-04 22:30:50 -0500307#define CONFIG_CMD_DTT
308#define CONFIG_CMD_EEPROM
309#define CONFIG_CMD_I2C
Wolfgang Denk4681e672009-05-14 23:18:34 +0200310#define CONFIG_CMD_NFS
Jon Loeliger26946902007-07-04 22:30:50 -0500311#define CONFIG_CMD_JFFS2
312#define CONFIG_CMD_MII
313#define CONFIG_CMD_PING
Wolfgang Denk4681e672009-05-14 23:18:34 +0200314#define CONFIG_CMD_REGINFO
315#define CONFIG_CMD_SNTP
Jon Loeliger26946902007-07-04 22:30:50 -0500316
317#if defined(CONFIG_PCI)
318 #define CONFIG_CMD_PCI
319#endif
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500322 #undef CONFIG_CMD_SAVEENV
Jon Loeliger26946902007-07-04 22:30:50 -0500323 #undef CONFIG_CMD_LOADS
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200324#endif
325
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200326/*
327 * Miscellaneous configurable options
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_LONGHELP /* undef to save memory */
330#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
331#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200332
Wolfgang Denk2751a952006-10-28 02:29:14 +0200333#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
335#ifdef CONFIG_SYS_HUSH_PARSER
336#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wolfgang Denk2751a952006-10-28 02:29:14 +0200337#endif
338
Jon Loeliger26946902007-07-04 22:30:50 -0500339#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200341#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200343#endif
344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
346#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
347#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
348#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200349
350#undef CONFIG_WATCHDOG /* watchdog disabled */
351
Wolfgang Denk4681e672009-05-14 23:18:34 +0200352/* pass open firmware flat tree */
353#define CONFIG_OF_LIBFDT 1
354#define CONFIG_OF_BOARD_SETUP 1
355#define CONFIG_OF_STDOUT_VIA_ALIAS 1
356
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200357/*
358 * For booting Linux, the board info and command line data
359 * have to be in the first 8 MB of memory, since this is
360 * the maximum mapped by the Linux kernel during initialization.
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200365 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
366 HRCWL_DDR_TO_SCB_CLK_1X1 |\
367 HRCWL_CSB_TO_CLKIN_4X1 |\
368 HRCWL_VCO_1X2 |\
369 HRCWL_CORE_TO_CSB_2X1)
370
371#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200373 HRCWH_PCI_HOST |\
374 HRCWH_64_BIT_PCI |\
375 HRCWH_PCI1_ARBITER_ENABLE |\
376 HRCWH_PCI2_ARBITER_DISABLE |\
377 HRCWH_CORE_ENABLE |\
378 HRCWH_FROM_0X00000100 |\
379 HRCWH_BOOTSEQ_DISABLE |\
380 HRCWH_SW_WATCHDOG_DISABLE |\
381 HRCWH_ROM_LOC_LOCAL_16BIT |\
382 HRCWH_TSEC1M_IN_GMII |\
383 HRCWH_TSEC2M_IN_GMII )
384#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200386 HRCWH_PCI_HOST |\
387 HRCWH_32_BIT_PCI |\
388 HRCWH_PCI1_ARBITER_ENABLE |\
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200389 HRCWH_PCI2_ARBITER_DISABLE |\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200390 HRCWH_CORE_ENABLE |\
391 HRCWH_FROM_0X00000100 |\
392 HRCWH_BOOTSEQ_DISABLE |\
393 HRCWH_SW_WATCHDOG_DISABLE |\
394 HRCWH_ROM_LOC_LOCAL_16BIT |\
395 HRCWH_TSEC1M_IN_GMII |\
396 HRCWH_TSEC2M_IN_GMII )
397#endif
398
Kumar Gala9260a562006-01-11 11:12:57 -0600399/* System IO Config */
Kim Phillips3c9b1ee2009-06-05 14:11:33 -0500400#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_SICRL SICRL_LDP_A
Kumar Gala9260a562006-01-11 11:12:57 -0600402
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200403/* i-cache and d-cache disabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_HID0_INIT 0x000000000
405#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
406#define CONFIG_SYS_HID2 HID2_HBE
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200407
Becky Bruce31d82672008-05-08 19:02:12 -0500408#define CONFIG_HIGH_BATS 1 /* High BATs supported */
409
Kumar Gala2688e2f2006-02-10 15:40:06 -0600410/* DDR 0 - 512M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
412#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
413#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
414#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Kumar Gala2688e2f2006-02-10 15:40:06 -0600415
416/* stack in DCACHE @ 512M (no backing mem) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
418#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
Kumar Gala2688e2f2006-02-10 15:40:06 -0600419
420/* PCI */
Rafal Jaworowski6fe16a82006-08-18 10:39:11 +0200421#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
423#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Kim Phillips9993e192009-07-18 18:42:13 -0500424#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
425#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Kim Phillips9993e192009-07-18 18:42:13 -0500427#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
Rafal Jaworowski6fe16a82006-08-18 10:39:11 +0200428#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_IBAT3L (0)
430#define CONFIG_SYS_IBAT3U (0)
431#define CONFIG_SYS_IBAT4L (0)
432#define CONFIG_SYS_IBAT4U (0)
433#define CONFIG_SYS_IBAT5L (0)
434#define CONFIG_SYS_IBAT5U (0)
Rafal Jaworowski6fe16a82006-08-18 10:39:11 +0200435#endif
Kumar Gala2688e2f2006-02-10 15:40:06 -0600436
437/* IMMRBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
439#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
Kumar Gala2688e2f2006-02-10 15:40:06 -0600440
441/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
443#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Kumar Gala2688e2f2006-02-10 15:40:06 -0600444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
446#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
447#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
448#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
449#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
450#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
451#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
452#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
453#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
454#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
455#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
456#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
457#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
458#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
459#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
460#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kumar Gala2688e2f2006-02-10 15:40:06 -0600461
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200462/*
463 * Internal Definitions
464 *
465 * Boot Flags
466 */
467#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
468#define BOOTFLAG_WARM 0x02 /* Software reboot */
469
Jon Loeliger26946902007-07-04 22:30:50 -0500470#if defined(CONFIG_CMD_KGDB)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200471#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
472#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
473#endif
474
475/*
476 * Environment Configuration
477 */
478
Wolfgang Denkb931b3a2008-02-14 23:18:01 +0100479#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200480
481#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
482#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
483
484#define CONFIG_BAUDRATE 115200
485
486#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100487 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200488 "echo"
489
490#undef CONFIG_BOOTARGS
491
492#define CONFIG_EXTRA_ENV_SETTINGS \
493 "netdev=eth0\0" \
Wolfgang Denkb931b3a2008-02-14 23:18:01 +0100494 "hostname=tqm834x\0" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200495 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100496 "nfsroot=${serverip}:${rootpath}\0" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200497 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100498 "addip=setenv bootargs ${bootargs} " \
499 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
500 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk4681e672009-05-14 23:18:34 +0200501 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
502 "flash_nfs_old=run nfsargs addip addcons;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100503 "bootm ${kernel_addr}\0" \
Wolfgang Denk4681e672009-05-14 23:18:34 +0200504 "flash_nfs=run nfsargs addip addcons;" \
505 "bootm ${kernel_addr} - ${fdt_addr}\0" \
506 "flash_self_old=run ramargs addip addcons;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100507 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denk4681e672009-05-14 23:18:34 +0200508 "flash_self=run ramargs addip addcons;" \
509 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
510 "net_nfs_old=tftp 400000 ${bootfile};" \
511 "run nfsargs addip addcons;bootm\0" \
512 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
513 "tftp ${fdt_addr_r} ${fdt_file}; " \
514 "run nfsargs addip addcons; " \
515 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200516 "rootpath=/opt/eldk/ppc_6xx\0" \
Wolfgang Denk4681e672009-05-14 23:18:34 +0200517 "bootfile=tqm834x/uImage\0" \
518 "fdtfile=tqm834x/tqm834x.dtb\0" \
519 "kernel_addr_r=400000\0" \
520 "fdt_addr_r=600000\0" \
521 "ramdisk_addr_r=800000\0" \
522 "kernel_addr=800C0000\0" \
523 "fdt_addr=800A0000\0" \
524 "ramdisk_addr=80300000\0" \
525 "u-boot=tqm834x/u-boot.bin\0" \
526 "load=tftp 200000 ${u-boot}\0" \
527 "update=protect off 80000000 +${filesize};" \
528 "era 80000000 +${filesize};" \
529 "cp.b 200000 80000000 ${filesize}\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100530 "upd=run load update\0" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200531 ""
532
533#define CONFIG_BOOTCOMMAND "run flash_self"
534
535/*
536 * JFFS2 partitions
537 */
538/* mtdparts command line support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100539#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200540#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
541#define CONFIG_FLASH_CFI_MTD
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200542#define MTDIDS_DEFAULT "nor0=TQM834x-0"
543
544/* default mtd partition table */
Jens Gehrleina8770042008-01-29 08:45:02 +0100545#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200546 "1m(kernel),2m(initrd),"\
547 "-(user);"\
548
549#endif /* __CONFIG_H */