blob: 655f99c028ea70536d109630f2cb03652481e90e [file] [log] [blame]
Kumar Gala2a6c2d72008-08-26 21:34:55 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/fsl_ddr_sdram.h>
12
13#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
15#endif
16
17void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
18 unsigned int ctrl_num)
19{
20 unsigned int i;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020021 volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
Kumar Gala2a6c2d72008-08-26 21:34:55 -050022
23 if (ctrl_num) {
24 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
25 return;
26 }
27
28 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
29 if (i == 0) {
30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
31 out_be32(&ddr->cs0_config, regs->cs[i].config);
32
33 } else if (i == 1) {
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
35 out_be32(&ddr->cs1_config, regs->cs[i].config);
36
37 } else if (i == 2) {
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
39 out_be32(&ddr->cs2_config, regs->cs[i].config);
40
41 } else if (i == 3) {
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
43 out_be32(&ddr->cs3_config, regs->cs[i].config);
44 }
45 }
46
47 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
48 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
49 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
50 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
51 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
52 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
53 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
54 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
55 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
56 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
57 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
58 out_be32(&ddr->init_addr, regs->ddr_init_addr);
59 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
60
61 /*
62 * 200 painful micro-seconds must elapse between
63 * the DDR clock setup and the DDR config enable.
64 */
65 udelay(200);
66 asm volatile("sync;isync");
67
68 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
69
70 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
71 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
72 udelay(10000); /* throttle polling rate */
73 }
74}