blob: 146f5c6e426c17de2b149b0cce13b7bb9ccce120 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +02002/*
3 * Copyright (C) 2016 Marvell International Ltd.
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +02004 * https://spdx.org/licenses
5 */
6
7#include <common.h>
8#include <config.h>
9#include <fdtdec.h>
10#include <errno.h>
11#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +020013#include <dm/pinctrl.h>
14#include <dm/root.h>
15#include <asm/system.h>
16#include <asm/io.h>
17#include <asm/arch-armada8k/soc-info.h>
Simon Glasscd93d622020-05-10 11:40:13 -060018#include <linux/bitops.h>
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +020019#include "pinctrl-mvebu.h"
20
Konstantin Porotchkinf5db5972018-05-25 14:20:52 +080021#define AP_EMMC_PHY_CTRL_REG 0x100
22#define CP_EMMC_PHY_CTRL_REG 0x424
23#define EMMC_PHY_CTRL_SDPHY_EN BIT(0)
24
25#define AP806_EMMC_CLK_PIN_ID 0
26#define AP806_EMMC_CLK_FUNC 0x1
27#define CP110_EMMC_CLK_PIN_ID 56
28#define CP110_EMMC_CLK_FUNC 0xe
29
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +020030DECLARE_GLOBAL_DATA_PTR;
31
Konstantin Porotchkinf5db5972018-05-25 14:20:52 +080032/* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux
33 * To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux.
34 * eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC
35 * controller:
36 * - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer,
37 * - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller
38 * If pin function is set to eMMC/SD, then configure the eMMC/SD PHY
39 * muxltiplexer register to be on SDIO/eMMC controller
40 */
41void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func)
42{
43 const void *blob = gd->fdt_blob;
44 int node = dev_of_offset(dev);
45 struct mvebu_pinctrl_priv *priv = dev_get_priv(dev);
46
47 if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) {
48 if ((pin == AP806_EMMC_CLK_PIN_ID) &&
49 (func == AP806_EMMC_CLK_FUNC)) {
50 clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG,
51 EMMC_PHY_CTRL_SDPHY_EN);
52 }
53 } else if (!fdt_node_check_compatible(blob, node,
54 "marvell,armada-8k-cpm-pinctrl")) {
55 if ((pin == CP110_EMMC_CLK_PIN_ID) &&
56 (func == CP110_EMMC_CLK_FUNC)) {
57 clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG,
58 EMMC_PHY_CTRL_SDPHY_EN);
59 }
60 }
61}
62
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +020063/*
64 * mvebu_pinctrl_set_state: configure pin functions.
65 * @dev: the pinctrl device to be configured.
66 * @config: the state to be configured.
67 * @return: 0 in success
68 */
69int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
70{
71 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -070072 int node = dev_of_offset(config);
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +020073 struct mvebu_pinctrl_priv *priv;
74 u32 pin_arr[MVEBU_MAX_PINS_PER_BANK];
75 u32 function;
76 int i, pin_count;
77
78 priv = dev_get_priv(dev);
79
80 pin_count = fdtdec_get_int_array_count(blob, node,
81 "marvell,pins",
82 pin_arr,
83 MVEBU_MAX_PINS_PER_BANK);
84 if (pin_count <= 0) {
85 debug("Failed reading pins array for pinconfig %s (%d)\n",
86 config->name, pin_count);
87 return -EINVAL;
88 }
89
90 function = fdtdec_get_int(blob, node, "marvell,function", 0xff);
91
Konstantin Porotchkinf5db5972018-05-25 14:20:52 +080092 /*
93 * Check if setup of PHY mux is needed for this pins group.
94 * Only the first pin id in array is tested, all the rest use the same
95 * pin function.
96 */
97 mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function);
98
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +020099 for (i = 0; i < pin_count; i++) {
Konstantin Porotchkinf5db5972018-05-25 14:20:52 +0800100 int reg_offset;
101 int field_offset;
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +0200102 int pin = pin_arr[i];
103
104 if (function > priv->max_func) {
105 debug("Illegal function %d for pinconfig %s\n",
106 function, config->name);
107 return -EINVAL;
108 }
109
110 /* Calculate register address and bit in register */
111 reg_offset = priv->reg_direction * 4 *
112 (pin >> (PIN_REG_SHIFT));
113 field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK);
114
115 clrsetbits_le32(priv->base_reg + reg_offset,
116 PIN_FUNC_MASK << field_offset,
117 (function & PIN_FUNC_MASK) << field_offset);
118 }
119
120 return 0;
121}
122
123/*
124 * mvebu_pinctrl_set_state_all: configure the entire bank pin functions.
125 * @dev: the pinctrl device to be configured.
126 * @config: the state to be configured.
127 * @return: 0 in success
128 */
129static int mvebu_pinctrl_set_state_all(struct udevice *dev,
130 struct udevice *config)
131{
132 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700133 int node = dev_of_offset(config);
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +0200134 struct mvebu_pinctrl_priv *priv;
135 u32 func_arr[MVEBU_MAX_PINS_PER_BANK];
136 int pin, err;
137
138 priv = dev_get_priv(dev);
139
140 err = fdtdec_get_int_array(blob, node, "pin-func",
141 func_arr, priv->pin_cnt);
142 if (err) {
143 debug("Failed reading pin functions for bank %s\n",
144 priv->bank_name);
145 return -EINVAL;
146 }
147
Konstantin Porotchkinf5db5972018-05-25 14:20:52 +0800148 /* Check if setup of PHY mux is needed for this pins group. */
149 if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID)
150 mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID,
151 func_arr[AP806_EMMC_CLK_PIN_ID]);
152 else
153 mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID,
154 func_arr[CP110_EMMC_CLK_PIN_ID]);
155
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +0200156 for (pin = 0; pin < priv->pin_cnt; pin++) {
157 int reg_offset;
158 int field_offset;
159 u32 func = func_arr[pin];
160
161 /* Bypass pins with function 0xFF */
162 if (func == 0xff) {
163 debug("Warning: pin %d value is not modified ", pin);
164 debug("(kept as default)\n");
165 continue;
166 } else if (func > priv->max_func) {
167 debug("Illegal function %d for pin %d\n", func, pin);
168 return -EINVAL;
169 }
170
171 /* Calculate register address and bit in register */
172 reg_offset = priv->reg_direction * 4 *
173 (pin >> (PIN_REG_SHIFT));
174 field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK);
175
176 clrsetbits_le32(priv->base_reg + reg_offset,
177 PIN_FUNC_MASK << field_offset,
178 (func & PIN_FUNC_MASK) << field_offset);
179 }
180
181 return 0;
182}
183
184int mvebu_pinctl_probe(struct udevice *dev)
185{
186 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700187 int node = dev_of_offset(dev);
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +0200188 struct mvebu_pinctrl_priv *priv;
189
190 priv = dev_get_priv(dev);
191 if (!priv) {
192 debug("%s: Failed to get private\n", __func__);
193 return -EINVAL;
194 }
195
Masahiro Yamada702e57e2020-08-04 14:14:43 +0900196 priv->base_reg = dev_read_addr_ptr(dev);
Ovidiu Panait3fe69d32020-08-03 22:17:35 +0300197 if (!priv->base_reg) {
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +0200198 debug("%s: Failed to get base address\n", __func__);
199 return -EINVAL;
200 }
201
202 priv->pin_cnt = fdtdec_get_int(blob, node, "pin-count",
203 MVEBU_MAX_PINS_PER_BANK);
204 priv->max_func = fdtdec_get_int(blob, node, "max-func",
205 MVEBU_MAX_FUNC);
206 priv->bank_name = fdt_getprop(blob, node, "bank-name", NULL);
207
208 priv->reg_direction = 1;
209 if (fdtdec_get_bool(blob, node, "reverse-reg"))
210 priv->reg_direction = -1;
211
212 return mvebu_pinctrl_set_state_all(dev, dev);
213}
214
215static struct pinctrl_ops mvebu_pinctrl_ops = {
216 .set_state = mvebu_pinctrl_set_state
217};
218
219static const struct udevice_id mvebu_pinctrl_ids[] = {
220 { .compatible = "marvell,mvebu-pinctrl" },
Evan Wangf2466482018-05-25 14:20:51 +0800221 { .compatible = "marvell,ap806-pinctrl" },
222 { .compatible = "marvell,armada-7k-pinctrl" },
223 { .compatible = "marvell,armada-8k-cpm-pinctrl" },
224 { .compatible = "marvell,armada-8k-cps-pinctrl" },
Konstantin Porotchkin656e6cc2016-12-08 12:22:29 +0200225 { }
226};
227
228U_BOOT_DRIVER(pinctrl_mvebu) = {
229 .name = "mvebu_pinctrl",
230 .id = UCLASS_PINCTRL,
231 .of_match = mvebu_pinctrl_ids,
232 .priv_auto_alloc_size = sizeof(struct mvebu_pinctrl_priv),
233 .ops = &mvebu_pinctrl_ops,
234 .probe = mvebu_pinctl_probe
235};