| Tirumala Marri | 1b8fec1 | 2010-09-28 14:15:14 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010, Applied Micro Circuits Corporation |
| 3 | * Author: Tirumala R Marri <tmarri@apm.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; either version 2 of |
| 8 | * the License, or (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 18 | * MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | #ifndef _APM821XX_H_ |
| 22 | #define _APM821XX_H_ |
| 23 | |
| 24 | #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ |
| 25 | |
| 26 | /* Memory mapped registers */ |
| 27 | #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 |
| 28 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) |
| 29 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) |
| 30 | |
| 31 | #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) |
| 32 | |
| 33 | #define SDR0_SRST0_DMC 0x00200000 |
| 34 | #define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ |
| 35 | |
| 36 | /* AHB config. */ |
| 37 | #define AHB_TOP 0xA4 |
| 38 | #define AHB_BOT 0xA5 |
| 39 | |
| 40 | /* clk divisors */ |
| 41 | #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ |
| 42 | #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ |
| 43 | #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ |
| 44 | #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ |
| 45 | #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ |
| 46 | #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ |
| 47 | #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ |
| 48 | #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ |
| 49 | #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ |
| 50 | |
| 51 | /* |
| 52 | + * Clocking Controller |
| 53 | + */ |
| 54 | #define CPR0_CLKUPD 0x0020 |
| 55 | #define CPR0_PLLC 0x0040 |
| 56 | #define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) |
| 57 | #define CPR0_PLLD 0x0060 |
| 58 | #define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) |
| 59 | #define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) |
| 60 | #define CPR0_CPUD 0x0080 |
| 61 | #define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) |
| 62 | #define CPR0_PLB2D 0x00a0 |
| 63 | #define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) |
| 64 | #define CPR0_OPBD 0x00c0 |
| 65 | #define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) |
| 66 | #define CPR0_PERD 0x00e0 |
| 67 | #define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) |
| 68 | #define CPR0_DDR2D 0x0100 |
| 69 | #define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) |
| 70 | #define CLK_ICFG 0x0140 |
| 71 | |
| 72 | #endif /* _APM821XX_H_ */ |