blob: 099a7ca81b25134d32e5f22a3882e5cea366e0f2 [file] [log] [blame]
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +02001/*
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#include <asm/arch/mx31-regs.h>
21
22.macro REG reg, val
23 ldr r2, =\reg
24 ldr r3, =\val
25 str r3, [r2]
26.endm
27
28.macro REG8 reg, val
29 ldr r2, =\reg
30 ldr r3, =\val
31 strb r3, [r2]
32.endm
33
34.macro DELAY loops
35 ldr r2, =\loops
361:
37 subs r2, r2, #1
38 nop
39 bcs 1b
40.endm
41
42/* RedBoot: AIPS setup - Only setup MPROTx registers.
43 * The PACR default values are good.*/
44.macro init_aips
45 /*
46 * Set all MPROTx to be non-bufferable, trusted for R/W,
47 * not forced to user-mode.
48 */
49 ldr r0, =0x43F00000
50 ldr r1, =0x77777777
51 str r1, [r0, #0x00]
52 str r1, [r0, #0x04]
53 ldr r0, =0x53F00000
54 str r1, [r0, #0x00]
55 str r1, [r0, #0x04]
56
57 /*
58 * Clear the on and off peripheral modules Supervisor Protect bit
59 * for SDMA to access them. Did not change the AIPS control registers
60 * (offset 0x20) access type
61 */
62 ldr r0, =0x43F00000
63 ldr r1, =0x0
64 str r1, [r0, #0x40]
65 str r1, [r0, #0x44]
66 str r1, [r0, #0x48]
67 str r1, [r0, #0x4C]
68 ldr r1, [r0, #0x50]
69 and r1, r1, #0x00FFFFFF
70 str r1, [r0, #0x50]
71
72 ldr r0, =0x53F00000
73 ldr r1, =0x0
74 str r1, [r0, #0x40]
75 str r1, [r0, #0x44]
76 str r1, [r0, #0x48]
77 str r1, [r0, #0x4C]
78 ldr r1, [r0, #0x50]
79 and r1, r1, #0x00FFFFFF
80 str r1, [r0, #0x50]
81.endm /* init_aips */
82
83/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
84.macro init_max
85 ldr r0, =0x43F04000
86 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
87 ldr r1, =0x00302154
88 str r1, [r0, #0x000] /* for S0 */
89 str r1, [r0, #0x100] /* for S1 */
90 str r1, [r0, #0x200] /* for S2 */
91 str r1, [r0, #0x300] /* for S3 */
92 str r1, [r0, #0x400] /* for S4 */
93 /* SGPCR - always park on last master */
94 ldr r1, =0x10
95 str r1, [r0, #0x010] /* for S0 */
96 str r1, [r0, #0x110] /* for S1 */
97 str r1, [r0, #0x210] /* for S2 */
98 str r1, [r0, #0x310] /* for S3 */
99 str r1, [r0, #0x410] /* for S4 */
100 /* MGPCR - restore default values */
101 ldr r1, =0x0
102 str r1, [r0, #0x800] /* for M0 */
103 str r1, [r0, #0x900] /* for M1 */
104 str r1, [r0, #0xA00] /* for M2 */
105 str r1, [r0, #0xB00] /* for M3 */
106 str r1, [r0, #0xC00] /* for M4 */
107 str r1, [r0, #0xD00] /* for M5 */
108.endm /* init_max */
109
110/* RedBoot: M3IF setup */
111.macro init_m3if
112 /* Configure M3IF registers */
113 ldr r1, =0xB8003000
114 /*
115 * M3IF Control Register (M3IFCTL)
116 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
117 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
118 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
119 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
120 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
121 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
122 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
123 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
124 * ------------
125 * 0x00000040
126 */
127 ldr r0, =0x00000040
128 str r0, [r1] /* M3IF control reg */
129.endm /* init_m3if */
130
131/* RedBoot: To support 133MHz DDR */
132.macro init_drive_strength
133 /*
134 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
135 * in SW_PAD_CTL registers
136 */
137
138 /* SDCLK */
139 ldr r1, =0x43FAC200
140 ldr r0, [r1, #0x6C]
141 bic r0, r0, #(1 << 12)
142 str r0, [r1, #0x6C]
143
144 /* CAS */
145 ldr r0, [r1, #0x70]
146 bic r0, r0, #(1 << 22)
147 str r0, [r1, #0x70]
148
149 /* RAS */
150 ldr r0, [r1, #0x74]
151 bic r0, r0, #(1 << 2)
152 str r0, [r1, #0x74]
153
154 /* CS2 (CSD0) */
155 ldr r0, [r1, #0x7C]
156 bic r0, r0, #(1 << 22)
157 str r0, [r1, #0x7C]
158
159 /* DQM3 */
160 ldr r0, [r1, #0x84]
161 bic r0, r0, #(1 << 22)
162 str r0, [r1, #0x84]
163
164 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
165 ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
166pad_loop:
167 ldr r0, [r1, #0x88]
168 bic r0, r0, #(1 << 22)
169 bic r0, r0, #(1 << 12)
170 bic r0, r0, #(1 << 2)
171 str r0, [r1, #0x88]
172 add r1, r1, #4
173 subs r2, r2, #0x1
174 bne pad_loop
175.endm /* init_drive_strength */
176
177/* CPLD on CS4 setup */
178.macro init_cs4
179 ldr r0, =WEIM_BASE
180 ldr r1, =0x0000D843
181 str r1, [r0, #0x40]
182 ldr r1, =0x22252521
183 str r1, [r0, #0x44]
184 ldr r1, =0x22220A00
185 str r1, [r0, #0x48]
186.endm /* init_cs4 */
187
188.globl lowlevel_init
189lowlevel_init:
190
191 /* Redboot initializes very early AIPS, what for?
192 * Then it also initializes Multi-Layer AHB Crossbar Switch,
193 * M3IF */
194 /* Also setup the Peripheral Port Remap register inside the core */
195 ldr r0, =0x40000015 /* start from AIPS 2GB region */
196 mcr p15, 0, r0, c15, c2, 4
197
198 init_aips
199
200 init_max
201
202 init_m3if
203
204 init_drive_strength
205
206 init_cs4
207
208 /* Image Processing Unit: */
209 /* Too early to switch display on? */
210 REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
211 /* Clock Control Module: */
212 REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
213
214 DELAY 0x40000
215
216 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
217 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
218
219 /* PBC CPLD on CS4 */
220 mov r1, #CS4_BASE
221 ldrh r1, [r1, #0x2]
222 /* Is 27MHz switch set? */
223 ands r1, r1, #0x16
224
225 /* 532-133-66.5 */
226 ldr r0, =CCM_BASE
227 ldr r1, =0xFF871D58
228 /* PDR0 */
229 str r1, [r0, #0x4]
230 ldreq r1, MPCTL_PARAM_532
231 ldrne r1, MPCTL_PARAM_532_27
232 /* MPCTL */
233 str r1, [r0, #0x10]
234
235 /* Set UPLL=240MHz, USB=60MHz */
236 ldr r1, =0x49FCFE7F
237 /* PDR1 */
238 str r1, [r0, #0x8]
239 ldreq r1, UPCTL_PARAM_240
240 ldrne r1, UPCTL_PARAM_240_27
241 /* UPCTL */
242 str r1, [r0, #0x14]
243 /* default CLKO to 1/8 of the ARM core */
244 mov r1, #0x000002C0
245 add r1, r1, #0x00000006
246 /* COSR */
247 str r1, [r0, #0x1c]
248
249 /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
250/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
251
252 /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
253/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
254 /* Default: 1, 4, 12, 1 */
255 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
256
257 /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
258 REG 0xB8001010, 0x00000004
259 REG 0xB8001004, 0x006ac73a
260 REG 0xB8001000, 0x92100000
261 REG 0x80000f00, 0x12344321
262 REG 0xB8001000, 0xa2100000
263 REG 0x80000000, 0x12344321
264 REG 0x80000000, 0x12344321
265 REG 0xB8001000, 0xb2100000
266 REG8 0x80000033, 0xda
267 REG8 0x81000000, 0xff
268 REG 0xB8001000, 0x82226080
269 REG 0x80000000, 0xDEADBEEF
270 REG 0xB8001010, 0x0000000c
271
272 mov pc, lr
273
274MPCTL_PARAM_532:
275 .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
276MPCTL_PARAM_532_27:
277 .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
278UPCTL_PARAM_240:
279 .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
280UPCTL_PARAM_240_27:
281 .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))