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wdenk03f5c552004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8555cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
wdenk03f5c552004-10-10 21:21:55 +000029#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050036#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000037#define CONFIG_MPC8555 1 /* MPC8555 specific */
38#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
39
40#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050041#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020042#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk03f5c552004-10-10 21:21:55 +000043#define CONFIG_ENV_OVERWRITE
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060044#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk03f5c552004-10-10 21:21:55 +000045
Jon Loeliger25eedb22008-03-19 15:02:07 -050046#define CONFIG_FSL_VIA
Timur Tabie8d18542008-07-18 16:52:23 +020047
Jon Loeliger25eedb22008-03-19 15:02:07 -050048
wdenk03f5c552004-10-10 21:21:55 +000049#ifndef __ASSEMBLY__
50extern unsigned long get_clock_freq(void);
51#endif
52#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
53
54/*
55 * These can be toggled for performance analysis, otherwise use default.
56 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020057#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000058#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
61#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000062
wdenk03f5c552004-10-10 21:21:55 +000063/*
64 * Base addresses -- Note these are effective addresses where the
65 * actual resources get mapped (not physical addresses)
66 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
68#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
69#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
70#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk03f5c552004-10-10 21:21:55 +000071
Jon Loeliger2b40edb2008-03-18 11:12:42 -050072/* DDR Setup */
73#define CONFIG_FSL_DDR1
74#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
75#define CONFIG_DDR_SPD
76#undef CONFIG_FSL_DDR_INTERACTIVE
77
78#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
79
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
81#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000082
Jon Loeliger2b40edb2008-03-18 11:12:42 -050083#define CONFIG_NUM_DDR_CONTROLLERS 1
84#define CONFIG_DIMM_SLOTS_PER_CTLR 1
85#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk03f5c552004-10-10 21:21:55 +000086
Jon Loeliger2b40edb2008-03-18 11:12:42 -050087/* I2C addresses of SPD EEPROMs */
88#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
89
90/* Make sure required options are set */
wdenk03f5c552004-10-10 21:21:55 +000091#ifndef CONFIG_SPD_EEPROM
92#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
93#endif
94
Jon Loeliger7202d432005-07-25 11:13:26 -050095#undef CONFIG_CLOCKS_IN_MHZ
96
wdenk03f5c552004-10-10 21:21:55 +000097/*
Jon Loeliger7202d432005-07-25 11:13:26 -050098 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +000099 */
Jon Loeliger7202d432005-07-25 11:13:26 -0500100
101/*
102 * FLASH on the Local Bus
103 * Two banks, 8M each, using the CFI driver.
104 * Boot from BR0/OR0 bank at 0xff00_0000
105 * Alternate BR1/OR1 bank at 0xff80_0000
106 *
107 * BR0, BR1:
108 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
109 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
110 * Port Size = 16 bits = BRx[19:20] = 10
111 * Use GPCM = BRx[24:26] = 000
112 * Valid = BRx[31] = 1
113 *
114 * 0 4 8 12 16 20 24 28
115 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
116 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
117 *
118 * OR0, OR1:
119 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
120 * Reserved ORx[17:18] = 11, confusion here?
121 * CSNT = ORx[20] = 1
122 * ACS = half cycle delay = ORx[21:22] = 11
123 * SCY = 6 = ORx[24:27] = 0110
124 * TRLX = use relaxed timing = ORx[29] = 1
125 * EAD = use external address latch delay = OR[31] = 1
126 *
127 * 0 4 8 12 16 20 24 28
128 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
129 */
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_BR0_PRELIM 0xff801001
134#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_OR0_PRELIM 0xff806e65
137#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
140#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
141#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
142#undef CONFIG_SYS_FLASH_CHECKSUM
143#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
144#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000145
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200146#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000147
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200148#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_CFI
150#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000151
wdenk03f5c552004-10-10 21:21:55 +0000152
153/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500154 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
157#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000158
159/*
160 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000162 *
163 * For BR2, need:
164 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
165 * port-size = 32-bits = BR2[19:20] = 11
166 * no parity checking = BR2[21:22] = 00
167 * SDRAM for MSEL = BR2[24:26] = 011
168 * Valid = BR[31] = 1
169 *
170 * 0 4 8 12 16 20 24 28
171 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
172 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000174 * FIXME: the top 17 bits of BR2.
175 */
176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000178
179/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000181 *
182 * For OR2, need:
183 * 64MB mask for AM, OR2[0:7] = 1111 1100
184 * XAM, OR2[17:18] = 11
185 * 9 columns OR2[19-21] = 010
186 * 13 rows OR2[23-25] = 100
187 * EAD set for extra time OR[31] = 1
188 *
189 * 0 4 8 12 16 20 24 28
190 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
191 */
192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
196#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
197#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
198#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000199
200/*
wdenk03f5c552004-10-10 21:21:55 +0000201 * Common settings for all Local Bus SDRAM commands.
202 * At run time, either BSMA1516 (for CPU 1.1)
203 * or BSMA1617 (for CPU 1.0) (old)
204 * is OR'ed in too.
205 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500206#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
207 | LSDMR_PRETOACT7 \
208 | LSDMR_ACTTORW7 \
209 | LSDMR_BL8 \
210 | LSDMR_WRC4 \
211 | LSDMR_CL3 \
212 | LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000213 )
214
215/*
216 * The CADMUS registers are connected to CS3 on CDS.
217 * The new memory map places CADMUS at 0xf8000000.
218 *
219 * For BR3, need:
220 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
221 * port-size = 8-bits = BR[19:20] = 01
222 * no parity checking = BR[21:22] = 00
223 * GPMC for MSEL = BR[24:26] = 000
224 * Valid = BR[31] = 1
225 *
226 * 0 4 8 12 16 20 24 28
227 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
228 *
229 * For OR3, need:
230 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
231 * disable buffer ctrl OR[19] = 0
232 * CSNT OR[20] = 1
233 * ACS OR[21:22] = 11
234 * XACS OR[23] = 1
235 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
236 * SETA OR[28] = 0
237 * TRLX OR[29] = 1
238 * EHTR OR[30] = 1
239 * EAD extra time OR[31] = 1
240 *
241 * 0 4 8 12 16 20 24 28
242 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
243 */
244
Jon Loeliger25eedb22008-03-19 15:02:07 -0500245#define CONFIG_FSL_CADMUS
246
wdenk03f5c552004-10-10 21:21:55 +0000247#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_BR3_PRELIM 0xf8000801
249#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_INIT_RAM_LOCK 1
252#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
253#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
256#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
257#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
260#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000261
262/* Serial Port */
263#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_NS16550
265#define CONFIG_SYS_NS16550_SERIAL
266#define CONFIG_SYS_NS16550_REG_SIZE 1
267#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000270 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
273#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000274
275/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_HUSH_PARSER
277#ifdef CONFIG_SYS_HUSH_PARSER
278#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk03f5c552004-10-10 21:21:55 +0000279#endif
280
Matthew McClintock0e163872006-06-28 10:43:36 -0500281/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600282#define CONFIG_OF_LIBFDT 1
283#define CONFIG_OF_BOARD_SETUP 1
284#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500285
Jon Loeliger20476722006-10-20 15:50:15 -0500286/*
287 * I2C
288 */
289#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
290#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk03f5c552004-10-10 21:21:55 +0000291#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
293#define CONFIG_SYS_I2C_SLAVE 0x7F
294#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
295#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk03f5c552004-10-10 21:21:55 +0000296
Timur Tabie8d18542008-07-18 16:52:23 +0200297/* EEPROM */
298#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_I2C_EEPROM_CCID
300#define CONFIG_SYS_ID_EEPROM
301#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
302#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200303
wdenk03f5c552004-10-10 21:21:55 +0000304/*
305 * General PCI
306 * Addresses are mapped 1-1.
307 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600308#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600309#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600310#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600312#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600313#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
315#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000316
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600317#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600318#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600319#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600321#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600322#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
324#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000325
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700326#ifdef CONFIG_LEGACY
327#define BRIDGE_ID 17
328#define VIA_ID 2
329#else
330#define BRIDGE_ID 28
331#define VIA_ID 4
332#endif
wdenk03f5c552004-10-10 21:21:55 +0000333
334#if defined(CONFIG_PCI)
335
336#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200337#define CONFIG_PCI_PNP /* do pci plug-and-play */
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500338#define CONFIG_MPC85XX_PCI2
wdenk03f5c552004-10-10 21:21:55 +0000339
340#undef CONFIG_EEPRO100
341#undef CONFIG_TULIP
342
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500343#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000345
346#endif /* CONFIG_PCI */
347
348
349#if defined(CONFIG_TSEC_ENET)
350
351#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200352#define CONFIG_NET_MULTI 1
wdenk03f5c552004-10-10 21:21:55 +0000353#endif
354
355#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500356#define CONFIG_TSEC1 1
357#define CONFIG_TSEC1_NAME "TSEC0"
358#define CONFIG_TSEC2 1
359#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000360#define TSEC1_PHY_ADDR 0
361#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000362#define TSEC1_PHYIDX 0
363#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500364#define TSEC1_FLAGS TSEC_GIGABIT
365#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500366
367/* Options are: TSEC[0-1] */
368#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000369
370#endif /* CONFIG_TSEC_ENET */
371
wdenk03f5c552004-10-10 21:21:55 +0000372/*
373 * Environment
374 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200375#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200377#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
378#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000379
380#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000382
Jon Loeliger2835e512007-06-13 13:22:08 -0500383/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500384 * BOOTP options
385 */
386#define CONFIG_BOOTP_BOOTFILESIZE
387#define CONFIG_BOOTP_BOOTPATH
388#define CONFIG_BOOTP_GATEWAY
389#define CONFIG_BOOTP_HOSTNAME
390
391
392/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500393 * Command line configuration.
394 */
395#include <config_cmd_default.h>
396
397#define CONFIG_CMD_PING
398#define CONFIG_CMD_I2C
399#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600400#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500401#define CONFIG_CMD_IRQ
402#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500403#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500404
wdenk03f5c552004-10-10 21:21:55 +0000405#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500406 #define CONFIG_CMD_PCI
wdenk03f5c552004-10-10 21:21:55 +0000407#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500408
wdenk03f5c552004-10-10 21:21:55 +0000409
410#undef CONFIG_WATCHDOG /* watchdog disabled */
411
412/*
413 * Miscellaneous configurable options
414 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500416#define CONFIG_CMDLINE_EDITING /* Command-line editing */
417#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
419#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500420#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000422#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000424#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
426#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
427#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
428#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk03f5c552004-10-10 21:21:55 +0000429
430/*
431 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500432 * have to be in the first 16 MB of memory, since this is
wdenk03f5c552004-10-10 21:21:55 +0000433 * the maximum mapped by the Linux kernel during initialization.
434 */
Kumar Gala89188a62009-07-15 08:54:50 -0500435#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
wdenk03f5c552004-10-10 21:21:55 +0000436
wdenk03f5c552004-10-10 21:21:55 +0000437/*
438 * Internal Definitions
439 *
440 * Boot Flags
441 */
442#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
443#define BOOTFLAG_WARM 0x02 /* Software reboot */
444
Jon Loeliger2835e512007-06-13 13:22:08 -0500445#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000446#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
447#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
448#endif
449
wdenk03f5c552004-10-10 21:21:55 +0000450/*
451 * Environment Configuration
452 */
453
454/* The mac addresses for all ethernet interface */
455#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500456#define CONFIG_HAS_ETH0
wdenk03f5c552004-10-10 21:21:55 +0000457#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000458#define CONFIG_HAS_ETH1
wdenk03f5c552004-10-10 21:21:55 +0000459#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000460#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000461#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
462#endif
463
464#define CONFIG_IPADDR 192.168.1.253
465
466#define CONFIG_HOSTNAME unknown
467#define CONFIG_ROOTPATH /nfsroot
468#define CONFIG_BOOTFILE your.uImage
469
470#define CONFIG_SERVERIP 192.168.1.1
471#define CONFIG_GATEWAYIP 192.168.1.1
472#define CONFIG_NETMASK 255.255.255.0
473
474#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
475
476#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
477#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
478
479#define CONFIG_BAUDRATE 115200
480
481#define CONFIG_EXTRA_ENV_SETTINGS \
482 "netdev=eth0\0" \
483 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500484 "ramdiskaddr=600000\0" \
485 "ramdiskfile=your.ramdisk.u-boot\0" \
486 "fdtaddr=400000\0" \
487 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000488
489#define CONFIG_NFSBOOTCOMMAND \
490 "setenv bootargs root=/dev/nfs rw " \
491 "nfsroot=$serverip:$rootpath " \
492 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
493 "console=$consoledev,$baudrate $othbootargs;" \
494 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500495 "tftp $fdtaddr $fdtfile;" \
496 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000497
498#define CONFIG_RAMBOOTCOMMAND \
499 "setenv bootargs root=/dev/ram rw " \
500 "console=$consoledev,$baudrate $othbootargs;" \
501 "tftp $ramdiskaddr $ramdiskfile;" \
502 "tftp $loadaddr $bootfile;" \
503 "bootm $loadaddr $ramdiskaddr"
504
505#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
506
wdenk03f5c552004-10-10 21:21:55 +0000507#endif /* __CONFIG_H */