blob: c92902a92edc2b327304d92f2e67ef0f33239ba4 [file] [log] [blame]
Shengzhou Liuae6b03f2011-11-22 16:51:13 +08001/*
2 * Copyright 2011 Freescale Semiconductor
3 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or (at your option)
8 * any later version.
9 *
10 * This file provides support for the QIXIS of some Freescale reference boards.
11 *
12 */
13
14#include <common.h>
15#include <command.h>
16#include <asm/io.h>
17#include "qixis.h"
18
19u8 qixis_read(unsigned int reg)
20{
21 void *p = (void *)QIXIS_BASE;
22
23 return in_8(p + reg);
24}
25
26void qixis_write(unsigned int reg, u8 value)
27{
28 void *p = (void *)QIXIS_BASE;
29
30 out_8(p + reg, value);
31}
32
33void qixis_reset(void)
34{
Prabhakar Kushwaha9f26fd72012-09-17 17:30:31 +000035 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +080036}
37
38void qixis_bank_reset(void)
39{
Prabhakar Kushwaha9f26fd72012-09-17 17:30:31 +000040 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
41 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +080042}
43
Prabhakar Kushwaha9f26fd72012-09-17 17:30:31 +000044/* Set the boot bank to the power-on default bank */
Shengzhou Liuae6b03f2011-11-22 16:51:13 +080045void clear_altbank(void)
46{
47 u8 reg;
48
49 reg = QIXIS_READ(brdcfg[0]);
Prabhakar Kushwaha9f26fd72012-09-17 17:30:31 +000050 reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
Shengzhou Liuae6b03f2011-11-22 16:51:13 +080051 QIXIS_WRITE(brdcfg[0], reg);
52}
53
54/* Set the boot bank to the alternate bank */
55void set_altbank(void)
56{
57 u8 reg;
58
59 reg = QIXIS_READ(brdcfg[0]);
60 reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
61 QIXIS_WRITE(brdcfg[0], reg);
62}
63
64#ifdef DEBUG
65static void qixis_dump_regs(void)
66{
67 int i;
68
69 printf("id = %02x\n", QIXIS_READ(id));
70 printf("arch = %02x\n", QIXIS_READ(arch));
71 printf("scver = %02x\n", QIXIS_READ(scver));
72 printf("model = %02x\n", QIXIS_READ(model));
73 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
74 printf("aux = %02x\n", QIXIS_READ(aux));
75 for (i = 0; i < 16; i++)
76 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
77 for (i = 0; i < 16; i++)
78 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
79 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
80 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
81 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
82 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
83 printf("aux = %02x\n", QIXIS_READ(aux));
84 printf("watch = %02x\n", QIXIS_READ(watch));
85 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
86 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
87 printf("present = %02x\n", QIXIS_READ(present));
Shengzhou Liue4de13e2012-10-07 20:21:02 +000088 printf("present2 = %02x\n", QIXIS_READ(present2));
Shengzhou Liuae6b03f2011-11-22 16:51:13 +080089 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
90 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
91 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
92 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
Shengzhou Liuae6b03f2011-11-22 16:51:13 +080093}
94#endif
95
96int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
97{
98 int i;
99
100 if (argc <= 1) {
101 clear_altbank();
102 qixis_reset();
103 } else if (strcmp(argv[1], "altbank") == 0) {
104 set_altbank();
105 qixis_bank_reset();
106 } else if (strcmp(argv[1], "watchdog") == 0) {
107 static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
108 "1min", "2min", "4min", "8min"};
109 u8 rcfg = QIXIS_READ(rcfg_ctl);
110
111 if (argv[2] == NULL) {
112 printf("qixis watchdog <watchdog_period>\n");
113 return 0;
114 }
115 for (i = 0; i < ARRAY_SIZE(period); i++) {
116 if (strcmp(argv[2], period[i]) == 0) {
117 /* disable watchdog */
Prabhakar Kushwaha9f26fd72012-09-17 17:30:31 +0000118 QIXIS_WRITE(rcfg_ctl,
119 rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800120 QIXIS_WRITE(watch, ((i<<2) - 1));
121 QIXIS_WRITE(rcfg_ctl, rcfg);
122 return 0;
123 }
124 }
125 }
126
127#ifdef DEBUG
128 else if (strcmp(argv[1], "dump") == 0) {
129 qixis_dump_regs();
130 return 0;
131 }
132#endif
133
134 else {
135 printf("Invalid option: %s\n", argv[1]);
136 return 1;
137 }
138
139 return 0;
140}
141
142U_BOOT_CMD(
143 qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
144 "Reset the board using the FPGA sequencer",
145 "- hard reset to default bank\n"
146 "qixis_reset altbank - reset to alternate bank\n"
147 "qixis watchdog <watchdog_period> - set the watchdog period\n"
148 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
149#ifdef DEBUG
150 "qixis_reset dump - display the QIXIS registers\n"
151#endif
152 );