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wdenkfe8c2802002-11-03 00:38:21 +00001/*------------------------------------------------------------------------
2 . smc91111.c
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
4 .
5 . (C) Copyright 2002
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
8 .
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
wdenk42dfe7a2004-03-14 22:25:36 +000010 . Developed by Simple Network Magic Corporation (SNMC)
wdenkfe8c2802002-11-03 00:38:21 +000011 . Copyright (C) 1996 by Erik Stahlman (ES)
12 .
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
17 .
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk42dfe7a2004-03-14 22:25:36 +000020 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkfe8c2802002-11-03 00:38:21 +000021 . GNU General Public License for more details.
22 .
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
wdenk42dfe7a2004-03-14 22:25:36 +000025 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
wdenkfe8c2802002-11-03 00:38:21 +000026 .
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
30 .
31 .
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
37 .
38 . Arguments:
wdenk42dfe7a2004-03-14 22:25:36 +000039 . io = for the base address
wdenkfe8c2802002-11-03 00:38:21 +000040 . irq = for the IRQ
41 .
42 . author:
wdenk42dfe7a2004-03-14 22:25:36 +000043 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
wdenkfe8c2802002-11-03 00:38:21 +000045 .
46 .
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
48 .
49 . Sources:
wdenk42dfe7a2004-03-14 22:25:36 +000050 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
wdenkfe8c2802002-11-03 00:38:21 +000053 .
54 . History:
wdenk42dfe7a2004-03-14 22:25:36 +000055 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
wdenkfe8c2802002-11-03 00:38:21 +000056 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
wdenk42dfe7a2004-03-14 22:25:36 +000057 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
wdenkfe8c2802002-11-03 00:38:21 +000060 ----------------------------------------------------------------------------*/
61
62#include <common.h>
63#include <command.h>
wdenkf39748a2004-06-09 13:37:52 +000064#include <config.h>
wdenkfe8c2802002-11-03 00:38:21 +000065#include "smc91111.h"
66#include <net.h>
67
68#ifdef CONFIG_DRIVER_SMC91111
69
70/* Use power-down feature of the chip */
71#define POWER_DOWN 0
72
73#define NO_AUTOPROBE
74
Wolfgang Denk0be248f2006-03-07 00:22:36 +010075#define SMC_DEBUG 0
wdenk8bf3b002003-12-06 23:20:41 +000076
77#if SMC_DEBUG > 1
wdenkfe8c2802002-11-03 00:38:21 +000078static const char version[] =
79 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
wdenk8bf3b002003-12-06 23:20:41 +000080#endif
wdenkfe8c2802002-11-03 00:38:21 +000081
wdenkf39748a2004-06-09 13:37:52 +000082/* Autonegotiation timeout in seconds */
83#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
84#define CONFIG_SMC_AUTONEG_TIMEOUT 10
85#endif
86
wdenkfe8c2802002-11-03 00:38:21 +000087/*------------------------------------------------------------------------
88 .
89 . Configuration options, for the experienced user to change.
90 .
91 -------------------------------------------------------------------------*/
92
93/*
94 . Wait time for memory to be free. This probably shouldn't be
95 . tuned that much, as waiting for this means nothing else happens
96 . in the system
97*/
98#define MEMORY_WAIT_TIME 16
99
100
101#if (SMC_DEBUG > 2 )
102#define PRINTK3(args...) printf(args)
103#else
104#define PRINTK3(args...)
105#endif
106
107#if SMC_DEBUG > 1
108#define PRINTK2(args...) printf(args)
109#else
110#define PRINTK2(args...)
111#endif
112
113#ifdef SMC_DEBUG
114#define PRINTK(args...) printf(args)
115#else
116#define PRINTK(args...)
117#endif
118
119
120/*------------------------------------------------------------------------
121 .
wdenk42dfe7a2004-03-14 22:25:36 +0000122 . The internal workings of the driver. If you are changing anything
wdenkfe8c2802002-11-03 00:38:21 +0000123 . here with the SMC stuff, you should have the datasheet and know
124 . what you are doing.
125 .
126 -------------------------------------------------------------------------*/
127#define CARDNAME "LAN91C111"
128
129/* Memory sizing constant */
130#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
131
132#ifndef CONFIG_SMC91111_BASE
133#define CONFIG_SMC91111_BASE 0x20000300
134#endif
135
136#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
137
138#define SMC_DEV_NAME "SMC91111"
139#define SMC_PHY_ADDR 0x0000
140#define SMC_ALLOC_MAX_TRY 5
141#define SMC_TX_TIMEOUT 30
142
143#define SMC_PHY_CLOCK_DELAY 1000
144
145#define ETH_ZLEN 60
146
wdenk42dfe7a2004-03-14 22:25:36 +0000147#ifdef CONFIG_SMC_USE_32_BIT
wdenkfe8c2802002-11-03 00:38:21 +0000148#define USE_32_BIT 1
149#else
150#undef USE_32_BIT
151#endif
152/*-----------------------------------------------------------------
153 .
154 . The driver can be entered at any of the following entry points.
155 .
156 .------------------------------------------------------------------ */
157
158extern int eth_init(bd_t *bd);
159extern void eth_halt(void);
160extern int eth_rx(void);
161extern int eth_send(volatile void *packet, int length);
162
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100163#ifdef SHARED_RESOURCES
164 extern void swap_to(int device_id);
165#endif
wdenkfe8c2802002-11-03 00:38:21 +0000166
wdenkfe8c2802002-11-03 00:38:21 +0000167/*
168 . This is called by register_netdev(). It is responsible for
169 . checking the portlist for the SMC9000 series chipset. If it finds
170 . one, then it will initialize the device, find the hardware information,
171 . and sets up the appropriate device parameters.
172 . NOTE: Interrupts are *OFF* when this procedure is called.
173 .
174 . NB:This shouldn't be static since it is referred to externally.
175*/
176int smc_init(void);
177
178/*
179 . This is called by unregister_netdev(). It is responsible for
180 . cleaning up before the driver is finally unregistered and discarded.
181*/
182void smc_destructor(void);
183
184/*
185 . The kernel calls this function when someone wants to use the device,
186 . typically 'ifconfig ethX up'.
187*/
wdenk0b97ab12003-06-19 23:58:30 +0000188static int smc_open(bd_t *bd);
wdenkfe8c2802002-11-03 00:38:21 +0000189
190
191/*
192 . This is called by the kernel in response to 'ifconfig ethX down'. It
193 . is responsible for cleaning up everything that the open routine
194 . does, and maybe putting the card into a powerdown state.
195*/
196static int smc_close(void);
197
198/*
199 . Configures the PHY through the MII Management interface
200*/
201#ifndef CONFIG_SMC91111_EXT_PHY
202static void smc_phy_configure(void);
203#endif /* !CONFIG_SMC91111_EXT_PHY */
204
205/*
206 . This is a separate procedure to handle the receipt of a packet, to
207 . leave the interrupt code looking slightly cleaner
208*/
209static int smc_rcv(void);
210
wdenk0b97ab12003-06-19 23:58:30 +0000211/* See if a MAC address is defined in the current environment. If so use it. If not
wdenk8bde7f72003-06-27 21:31:46 +0000212 . print a warning and set the environment and other globals with the default.
wdenk0b97ab12003-06-19 23:58:30 +0000213 . If an EEPROM is present it really should be consulted.
214*/
215int smc_get_ethaddr(bd_t *bd);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100216int get_rom_mac(uchar *v_rom_mac);
wdenkfe8c2802002-11-03 00:38:21 +0000217
218/*
219 ------------------------------------------------------------
220 .
221 . Internal routines
222 .
223 ------------------------------------------------------------
224*/
225
wdenkc3c7f862004-06-09 14:47:54 +0000226#ifdef CONFIG_SMC_USE_IOFUNCS
227/*
228 * input and output functions
229 *
230 * Implemented due to inx,outx macros accessing the device improperly
231 * and putting the device into an unkown state.
232 *
233 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
234 * could not be free'd (hence the alloc failures), duplicate packets,
235 * packets being corrupt (shifted) on the wire, etc. Switching to the
236 * inx,outx functions fixed this problem.
237 */
238static inline word SMC_inw(dword offset);
239static inline void SMC_outw(word value, dword offset);
240static inline byte SMC_inb(dword offset);
241static inline void SMC_outb(byte value, dword offset);
242static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
243static inline void SMC_outsw(dword offset, uchar* buf, dword len);
244
245#define barrier() __asm__ __volatile__("": : :"memory")
246
247static inline word SMC_inw(dword offset)
248{
249 word v;
250 v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
251 barrier(); *(volatile u32*)(0xc0000000);
252 return v;
253}
254
255static inline void SMC_outw(word value, dword offset)
256{
257 *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
258 barrier(); *(volatile u32*)(0xc0000000);
259}
260
261static inline byte SMC_inb(dword offset)
262{
263 word _w;
264
265 _w = SMC_inw(offset & ~((dword)1));
266 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
267}
268
269static inline void SMC_outb(byte value, dword offset)
270{
271 word _w;
272
273 _w = SMC_inw(offset & ~((dword)1));
274 if (offset & 1)
275 *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
276 else
277 *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
278}
279
280static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
281{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100282 volatile word *p = (volatile word *)buf;
283
wdenkc3c7f862004-06-09 14:47:54 +0000284 while (len-- > 0) {
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100285 *p++ = SMC_inw(offset);
286 barrier();
287 *((volatile u32*)(0xc0000000));
wdenkc3c7f862004-06-09 14:47:54 +0000288 }
289}
290
291static inline void SMC_outsw(dword offset, uchar* buf, dword len)
292{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100293 volatile word *p = (volatile word *)buf;
294
wdenkc3c7f862004-06-09 14:47:54 +0000295 while (len-- > 0) {
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100296 SMC_outw(*p++, offset);
297 barrier();
298 *(volatile u32*)(0xc0000000);
wdenkc3c7f862004-06-09 14:47:54 +0000299 }
300}
301#endif /* CONFIG_SMC_USE_IOFUNCS */
302
wdenk8bf3b002003-12-06 23:20:41 +0000303static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
wdenkfe8c2802002-11-03 00:38:21 +0000304
305/*
306 * This function must be called before smc_open() if you want to override
307 * the default mac address.
308 */
309
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100310void smc_set_mac_addr(const unsigned char *addr) {
wdenkfe8c2802002-11-03 00:38:21 +0000311 int i;
312
313 for (i=0; i < sizeof(smc_mac_addr); i++){
314 smc_mac_addr[i] = addr[i];
315 }
316}
317
318/*
319 * smc_get_macaddr is no longer used. If you want to override the default
wdenk0b97ab12003-06-19 23:58:30 +0000320 * mac address, call smc_get_mac_addr as a part of the board initialization.
wdenkfe8c2802002-11-03 00:38:21 +0000321 */
322
323#if 0
324void smc_get_macaddr( byte *addr ) {
325 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
wdenk8bde7f72003-06-27 21:31:46 +0000326 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
wdenkfe8c2802002-11-03 00:38:21 +0000327 int i;
328
329
wdenk8bde7f72003-06-27 21:31:46 +0000330 for (i=0; i<6; i++) {
331 addr[0] = *(dnp1110_mac+0);
332 addr[1] = *(dnp1110_mac+1);
333 addr[2] = *(dnp1110_mac+2);
334 addr[3] = *(dnp1110_mac+3);
335 addr[4] = *(dnp1110_mac+4);
336 addr[5] = *(dnp1110_mac+5);
337 }
wdenkfe8c2802002-11-03 00:38:21 +0000338}
339#endif /* 0 */
340
341/***********************************************
wdenk42dfe7a2004-03-14 22:25:36 +0000342 * Show available memory *
wdenkfe8c2802002-11-03 00:38:21 +0000343 ***********************************************/
344void dump_memory_info(void)
345{
wdenk8bde7f72003-06-27 21:31:46 +0000346 word mem_info;
347 word old_bank;
wdenkfe8c2802002-11-03 00:38:21 +0000348
wdenk8bde7f72003-06-27 21:31:46 +0000349 old_bank = SMC_inw(BANK_SELECT)&0xF;
wdenkfe8c2802002-11-03 00:38:21 +0000350
wdenk8bde7f72003-06-27 21:31:46 +0000351 SMC_SELECT_BANK(0);
352 mem_info = SMC_inw( MIR_REG );
353 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
wdenkfe8c2802002-11-03 00:38:21 +0000354
wdenk8bde7f72003-06-27 21:31:46 +0000355 SMC_SELECT_BANK(old_bank);
wdenkfe8c2802002-11-03 00:38:21 +0000356}
357/*
358 . A rather simple routine to print out a packet for debugging purposes.
359*/
360#if SMC_DEBUG > 2
361static void print_packet( byte *, int );
362#endif
363
364#define tx_done(dev) 1
365
366
wdenkfe8c2802002-11-03 00:38:21 +0000367/* this does a soft reset on the device */
368static void smc_reset( void );
369
370/* Enable Interrupts, Receive, and Transmit */
371static void smc_enable( void );
372
373/* this puts the device in an inactive state */
374static void smc_shutdown( void );
375
376/* Routines to Read and Write the PHY Registers across the
377 MII Management Interface
378*/
379
380#ifndef CONFIG_SMC91111_EXT_PHY
381static word smc_read_phy_register(byte phyreg);
382static void smc_write_phy_register(byte phyreg, word phydata);
383#endif /* !CONFIG_SMC91111_EXT_PHY */
384
385
wdenkb56ddc62003-09-15 21:14:37 +0000386static int poll4int (byte mask, int timeout)
387{
388 int tmo = get_timer (0) + timeout * CFG_HZ;
389 int is_timeout = 0;
390 word old_bank = SMC_inw (BSR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000391
wdenkb56ddc62003-09-15 21:14:37 +0000392 PRINTK2 ("Polling...\n");
393 SMC_SELECT_BANK (2);
394 while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
395 if (get_timer (0) >= tmo) {
396 is_timeout = 1;
397 break;
398 }
wdenkfe8c2802002-11-03 00:38:21 +0000399 }
wdenkfe8c2802002-11-03 00:38:21 +0000400
wdenkb56ddc62003-09-15 21:14:37 +0000401 /* restore old bank selection */
402 SMC_SELECT_BANK (old_bank);
wdenkfe8c2802002-11-03 00:38:21 +0000403
wdenkb56ddc62003-09-15 21:14:37 +0000404 if (is_timeout)
405 return 1;
406 else
407 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000408}
409
wdenk487778b2003-06-06 11:20:01 +0000410/* Only one release command at a time, please */
wdenkb56ddc62003-09-15 21:14:37 +0000411static inline void smc_wait_mmu_release_complete (void)
wdenk487778b2003-06-06 11:20:01 +0000412{
413 int count = 0;
wdenkb56ddc62003-09-15 21:14:37 +0000414
wdenk487778b2003-06-06 11:20:01 +0000415 /* assume bank 2 selected */
wdenkb56ddc62003-09-15 21:14:37 +0000416 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
417 udelay (1); /* Wait until not busy */
418 if (++count > 200)
419 break;
wdenk487778b2003-06-06 11:20:01 +0000420 }
421}
422
wdenkfe8c2802002-11-03 00:38:21 +0000423/*
424 . Function: smc_reset( void )
425 . Purpose:
wdenk42dfe7a2004-03-14 22:25:36 +0000426 . This sets the SMC91111 chip to its normal state, hopefully from whatever
427 . mess that any other DOS driver has put it in.
wdenkfe8c2802002-11-03 00:38:21 +0000428 .
429 . Maybe I should reset more registers to defaults in here? SOFTRST should
430 . do that for me.
431 .
432 . Method:
433 . 1. send a SOFT RESET
434 . 2. wait for it to finish
435 . 3. enable autorelease mode
436 . 4. reset the memory management unit
437 . 5. clear all interrupts
438 .
439*/
wdenkb56ddc62003-09-15 21:14:37 +0000440static void smc_reset (void)
wdenkfe8c2802002-11-03 00:38:21 +0000441{
wdenkf39748a2004-06-09 13:37:52 +0000442 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000443
444 /* This resets the registers mostly to defaults, but doesn't
445 affect EEPROM. That seems unnecessary */
wdenkb56ddc62003-09-15 21:14:37 +0000446 SMC_SELECT_BANK (0);
447 SMC_outw (RCR_SOFTRST, RCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000448
449 /* Setup the Configuration Register */
450 /* This is necessary because the CONFIG_REG is not affected */
451 /* by a soft reset */
452
wdenkb56ddc62003-09-15 21:14:37 +0000453 SMC_SELECT_BANK (1);
wdenkfe8c2802002-11-03 00:38:21 +0000454#if defined(CONFIG_SMC91111_EXT_PHY)
wdenkb56ddc62003-09-15 21:14:37 +0000455 SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000456#else
wdenkb56ddc62003-09-15 21:14:37 +0000457 SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000458#endif
459
460
461 /* Release from possible power-down state */
462 /* Configuration register is not affected by Soft Reset */
wdenkb56ddc62003-09-15 21:14:37 +0000463 SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000464
wdenkb56ddc62003-09-15 21:14:37 +0000465 SMC_SELECT_BANK (0);
wdenkfe8c2802002-11-03 00:38:21 +0000466
467 /* this should pause enough for the chip to be happy */
wdenkb56ddc62003-09-15 21:14:37 +0000468 udelay (10);
wdenkfe8c2802002-11-03 00:38:21 +0000469
470 /* Disable transmit and receive functionality */
wdenkb56ddc62003-09-15 21:14:37 +0000471 SMC_outw (RCR_CLEAR, RCR_REG);
472 SMC_outw (TCR_CLEAR, TCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000473
474 /* set the control register */
wdenkb56ddc62003-09-15 21:14:37 +0000475 SMC_SELECT_BANK (1);
476 SMC_outw (CTL_DEFAULT, CTL_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000477
478 /* Reset the MMU */
wdenkb56ddc62003-09-15 21:14:37 +0000479 SMC_SELECT_BANK (2);
480 smc_wait_mmu_release_complete ();
481 SMC_outw (MC_RESET, MMU_CMD_REG);
482 while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
483 udelay (1); /* Wait until not busy */
wdenkfe8c2802002-11-03 00:38:21 +0000484
485 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
486 but this is a place where future chipsets _COULD_ break. Be wary
wdenk8bde7f72003-06-27 21:31:46 +0000487 of issuing another MMU command right after this */
wdenkfe8c2802002-11-03 00:38:21 +0000488
489 /* Disable all interrupts */
wdenkb56ddc62003-09-15 21:14:37 +0000490 SMC_outb (0, IM_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000491}
492
493/*
494 . Function: smc_enable
495 . Purpose: let the chip talk to the outside work
496 . Method:
497 . 1. Enable the transmitter
498 . 2. Enable the receiver
499 . 3. Enable interrupts
500*/
501static void smc_enable()
502{
wdenkf39748a2004-06-09 13:37:52 +0000503 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000504 SMC_SELECT_BANK( 0 );
505 /* see the header file for options in TCR/RCR DEFAULT*/
506 SMC_outw( TCR_DEFAULT, TCR_REG );
507 SMC_outw( RCR_DEFAULT, RCR_REG );
508
509 /* clear MII_DIS */
510/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
511}
512
513/*
514 . Function: smc_shutdown
515 . Purpose: closes down the SMC91xxx chip.
516 . Method:
517 . 1. zero the interrupt mask
518 . 2. clear the enable receive flag
519 . 3. clear the enable xmit flags
520 .
521 . TODO:
522 . (1) maybe utilize power down mode.
523 . Why not yet? Because while the chip will go into power down mode,
524 . the manual says that it will wake up in response to any I/O requests
wdenk42dfe7a2004-03-14 22:25:36 +0000525 . in the register space. Empirical results do not show this working.
wdenkfe8c2802002-11-03 00:38:21 +0000526*/
527static void smc_shutdown()
528{
wdenkf39748a2004-06-09 13:37:52 +0000529 PRINTK2(CARDNAME ": smc_shutdown\n");
wdenkfe8c2802002-11-03 00:38:21 +0000530
531 /* no more interrupts for me */
532 SMC_SELECT_BANK( 2 );
533 SMC_outb( 0, IM_REG );
534
535 /* and tell the card to stay away from that nasty outside world */
536 SMC_SELECT_BANK( 0 );
537 SMC_outb( RCR_CLEAR, RCR_REG );
538 SMC_outb( TCR_CLEAR, TCR_REG );
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100539#ifdef SHARED_RESOURCES
540 swap_to(FLASH);
541#endif
wdenkfe8c2802002-11-03 00:38:21 +0000542}
543
544
545/*
546 . Function: smc_hardware_send_packet(struct net_device * )
547 . Purpose:
548 . This sends the actual packet to the SMC9xxx chip.
549 .
550 . Algorithm:
wdenk42dfe7a2004-03-14 22:25:36 +0000551 . First, see if a saved_skb is available.
wdenkfe8c2802002-11-03 00:38:21 +0000552 . ( this should NOT be called if there is no 'saved_skb'
553 . Now, find the packet number that the chip allocated
554 . Point the data pointers at it in memory
555 . Set the length word in the chip's memory
556 . Dump the packet to chip memory
557 . Check if a last byte is needed ( odd length packet )
558 . if so, set the control flag right
wdenk42dfe7a2004-03-14 22:25:36 +0000559 . Tell the card to send it
wdenkfe8c2802002-11-03 00:38:21 +0000560 . Enable the transmit interrupt, so I know if it failed
wdenk42dfe7a2004-03-14 22:25:36 +0000561 . Free the kernel data if I actually sent it.
wdenkfe8c2802002-11-03 00:38:21 +0000562*/
wdenkb56ddc62003-09-15 21:14:37 +0000563static int smc_send_packet (volatile void *packet, int packet_length)
wdenkfe8c2802002-11-03 00:38:21 +0000564{
wdenkb56ddc62003-09-15 21:14:37 +0000565 byte packet_no;
566 unsigned long ioaddr;
567 byte *buf;
568 int length;
569 int numPages;
570 int try = 0;
571 int time_out;
572 byte status;
wdenk518e2e12004-03-25 14:59:05 +0000573 byte saved_pnr;
574 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000575
wdenk518e2e12004-03-25 14:59:05 +0000576 /* save PTR and PNR registers before manipulation */
wdenkb79a11c2004-03-25 15:14:43 +0000577 SMC_SELECT_BANK (2);
wdenk518e2e12004-03-25 14:59:05 +0000578 saved_pnr = SMC_inb( PN_REG );
579 saved_ptr = SMC_inw( PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000580
wdenkf39748a2004-06-09 13:37:52 +0000581 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000582
583 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
584
585 /* allocate memory
wdenkb56ddc62003-09-15 21:14:37 +0000586 ** The MMU wants the number of pages to be the number of 256 bytes
587 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
588 **
589 ** The 91C111 ignores the size bits, but the code is left intact
590 ** for backwards and future compatibility.
591 **
592 ** Pkt size for allocating is data length +6 (for additional status
593 ** words, length and ctl!)
594 **
595 ** If odd size then last byte is included in this header.
596 */
597 numPages = ((length & 0xfffe) + 6);
598 numPages >>= 8; /* Divide by 256 */
wdenkfe8c2802002-11-03 00:38:21 +0000599
wdenkb56ddc62003-09-15 21:14:37 +0000600 if (numPages > 7) {
601 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000602 return 0;
603 }
604
605 /* now, try to allocate the memory */
wdenkb56ddc62003-09-15 21:14:37 +0000606 SMC_SELECT_BANK (2);
607 SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000608
wdenkdc7c9a12003-03-26 06:55:25 +0000609 /* FIXME: the ALLOC_INT bit never gets set *
wdenk42dfe7a2004-03-14 22:25:36 +0000610 * so the following will always give a *
611 * memory allocation error. *
612 * same code works in armboot though *
wdenkdc7c9a12003-03-26 06:55:25 +0000613 * -ro
614 */
615
wdenkfe8c2802002-11-03 00:38:21 +0000616again:
617 try++;
618 time_out = MEMORY_WAIT_TIME;
619 do {
wdenkb56ddc62003-09-15 21:14:37 +0000620 status = SMC_inb (SMC91111_INT_REG);
621 if (status & IM_ALLOC_INT) {
wdenkfe8c2802002-11-03 00:38:21 +0000622 /* acknowledge the interrupt */
wdenkb56ddc62003-09-15 21:14:37 +0000623 SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
wdenk8bde7f72003-06-27 21:31:46 +0000624 break;
wdenkfe8c2802002-11-03 00:38:21 +0000625 }
wdenkb56ddc62003-09-15 21:14:37 +0000626 } while (--time_out);
wdenkfe8c2802002-11-03 00:38:21 +0000627
wdenkb56ddc62003-09-15 21:14:37 +0000628 if (!time_out) {
629 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
630 SMC_DEV_NAME, try);
631 if (try < SMC_ALLOC_MAX_TRY)
632 goto again;
633 else
634 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000635 }
636
wdenkb56ddc62003-09-15 21:14:37 +0000637 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
638 SMC_DEV_NAME, try);
wdenkfe8c2802002-11-03 00:38:21 +0000639
640 /* I can send the packet now.. */
641
642 ioaddr = SMC_BASE_ADDRESS;
643
wdenkb56ddc62003-09-15 21:14:37 +0000644 buf = (byte *) packet;
wdenkfe8c2802002-11-03 00:38:21 +0000645
646 /* If I get here, I _know_ there is a packet slot waiting for me */
wdenkb56ddc62003-09-15 21:14:37 +0000647 packet_no = SMC_inb (AR_REG);
648 if (packet_no & AR_FAILED) {
wdenkfe8c2802002-11-03 00:38:21 +0000649 /* or isn't there? BAD CHIP! */
wdenkb56ddc62003-09-15 21:14:37 +0000650 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000651 return 0;
652 }
653
654 /* we have a packet address, so tell the card to use it */
wdenk1f6d4252004-11-02 13:00:33 +0000655#ifndef CONFIG_XAENIAX
wdenkb56ddc62003-09-15 21:14:37 +0000656 SMC_outb (packet_no, PN_REG);
wdenk1f6d4252004-11-02 13:00:33 +0000657#else
658 /* On Xaeniax board, we can't use SMC_outb here because that way
659 * the Allocate MMU command will end up written to the command register
660 * as well, which will lead to a problem.
661 */
662 SMC_outl (packet_no << 16, 0);
663#endif
wdenkb79a11c2004-03-25 15:14:43 +0000664 /* do not write new ptr value if Write data fifo not empty */
665 while ( saved_ptr & PTR_NOTEMPTY )
wdenk518e2e12004-03-25 14:59:05 +0000666 printf ("Write data fifo not empty!\n");
667
wdenkfe8c2802002-11-03 00:38:21 +0000668 /* point to the beginning of the packet */
wdenkb56ddc62003-09-15 21:14:37 +0000669 SMC_outw (PTR_AUTOINC, PTR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000670
wdenkb56ddc62003-09-15 21:14:37 +0000671 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
672 SMC_DEV_NAME, length);
wdenkfe8c2802002-11-03 00:38:21 +0000673
674#if SMC_DEBUG > 2
wdenkb56ddc62003-09-15 21:14:37 +0000675 printf ("Transmitting Packet\n");
676 print_packet (buf, length);
wdenkfe8c2802002-11-03 00:38:21 +0000677#endif
678
679 /* send the packet length ( +6 for status, length and ctl byte )
wdenk8bde7f72003-06-27 21:31:46 +0000680 and the status word ( set to zeros ) */
wdenkfe8c2802002-11-03 00:38:21 +0000681#ifdef USE_32_BIT
wdenkb56ddc62003-09-15 21:14:37 +0000682 SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000683#else
wdenkb56ddc62003-09-15 21:14:37 +0000684 SMC_outw (0, SMC91111_DATA_REG);
685 /* send the packet length ( +6 for status words, length, and ctl */
686 SMC_outw ((length + 6), SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000687#endif
688
689 /* send the actual data
wdenkb56ddc62003-09-15 21:14:37 +0000690 . I _think_ it's faster to send the longs first, and then
691 . mop up by sending the last word. It depends heavily
wdenk42dfe7a2004-03-14 22:25:36 +0000692 . on alignment, at least on the 486. Maybe it would be
wdenkb56ddc62003-09-15 21:14:37 +0000693 . a good idea to check which is optimal? But that could take
694 . almost as much time as is saved?
695 */
wdenkfe8c2802002-11-03 00:38:21 +0000696#ifdef USE_32_BIT
wdenkb56ddc62003-09-15 21:14:37 +0000697 SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
wdenkbb310d42004-11-22 22:20:07 +0000698#ifndef CONFIG_XAENIAX
wdenkb56ddc62003-09-15 21:14:37 +0000699 if (length & 0x2)
700 SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
701 SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000702#else
wdenkbb310d42004-11-22 22:20:07 +0000703 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
704 * unaligned tail part specially. The standard code doesn't work.
705 */
706 if ((length & 3) == 3) {
707 u16 * ptr = (u16*) &buf[length-3];
708 SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16),
709 SMC91111_DATA_REG);
710 } else if ((length & 2) == 2) {
711 u16 * ptr = (u16*) &buf[length-2];
712 SMC_outl(*ptr, SMC91111_DATA_REG);
713 } else if (length & 1) {
714 SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG);
715 } else {
716 SMC_outl(0, SMC91111_DATA_REG);
717 }
718#endif
719#else
wdenkb56ddc62003-09-15 21:14:37 +0000720 SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000721#endif /* USE_32_BIT */
722
wdenkbb310d42004-11-22 22:20:07 +0000723#ifndef CONFIG_XAENIAX
wdenk42dfe7a2004-03-14 22:25:36 +0000724 /* Send the last byte, if there is one. */
wdenkb56ddc62003-09-15 21:14:37 +0000725 if ((length & 1) == 0) {
726 SMC_outw (0, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000727 } else {
wdenkb56ddc62003-09-15 21:14:37 +0000728 SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000729 }
wdenkbb310d42004-11-22 22:20:07 +0000730#endif
wdenkfe8c2802002-11-03 00:38:21 +0000731
732 /* and let the chipset deal with it */
wdenkb56ddc62003-09-15 21:14:37 +0000733 SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000734
735 /* poll for TX INT */
wdenk518e2e12004-03-25 14:59:05 +0000736 /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
737 /* poll for TX_EMPTY INT - autorelease enabled */
738 if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
wdenkfe8c2802002-11-03 00:38:21 +0000739 /* sending failed */
wdenkb56ddc62003-09-15 21:14:37 +0000740 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000741
742 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000743 /* no need to release, MMU does that now */
wdenk1f6d4252004-11-02 13:00:33 +0000744#ifdef CONFIG_XAENIAX
745 SMC_outw (MC_FREEPKT, MMU_CMD_REG);
746#endif
wdenkfe8c2802002-11-03 00:38:21 +0000747
wdenk8bde7f72003-06-27 21:31:46 +0000748 /* wait for MMU getting ready (low) */
wdenkb56ddc62003-09-15 21:14:37 +0000749 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
750 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000751 }
wdenkfe8c2802002-11-03 00:38:21 +0000752
wdenkb56ddc62003-09-15 21:14:37 +0000753 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000754
755
756 return 0;
757 } else {
758 /* ack. int */
wdenk518e2e12004-03-25 14:59:05 +0000759 SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
760 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
wdenkb56ddc62003-09-15 21:14:37 +0000761 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
762 length);
wdenkfe8c2802002-11-03 00:38:21 +0000763
764 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000765 /* no need to release, MMU does that now */
wdenk1f6d4252004-11-02 13:00:33 +0000766#ifdef CONFIG_XAENIAX
767 SMC_outw (MC_FREEPKT, MMU_CMD_REG);
768#endif
wdenkfe8c2802002-11-03 00:38:21 +0000769
wdenk8bde7f72003-06-27 21:31:46 +0000770 /* wait for MMU getting ready (low) */
wdenkb56ddc62003-09-15 21:14:37 +0000771 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
772 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000773 }
wdenkfe8c2802002-11-03 00:38:21 +0000774
wdenkb56ddc62003-09-15 21:14:37 +0000775 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000776
777
778 }
779
wdenk518e2e12004-03-25 14:59:05 +0000780 /* restore previously saved registers */
wdenk1f6d4252004-11-02 13:00:33 +0000781#ifndef CONFIG_XAENIAX
wdenk518e2e12004-03-25 14:59:05 +0000782 SMC_outb( saved_pnr, PN_REG );
wdenk1f6d4252004-11-02 13:00:33 +0000783#else
784 /* On Xaeniax board, we can't use SMC_outb here because that way
785 * the Allocate MMU command will end up written to the command register
786 * as well, which will lead to a problem.
787 */
788 SMC_outl(saved_pnr << 16, 0);
789#endif
wdenk518e2e12004-03-25 14:59:05 +0000790 SMC_outw( saved_ptr, PTR_REG );
791
wdenkfe8c2802002-11-03 00:38:21 +0000792 return length;
793}
794
795/*-------------------------------------------------------------------------
796 |
797 | smc_destructor( struct net_device * dev )
798 | Input parameters:
799 | dev, pointer to the device structure
800 |
801 | Output:
802 | None.
803 |
804 ---------------------------------------------------------------------------
805*/
806void smc_destructor()
807{
wdenkf39748a2004-06-09 13:37:52 +0000808 PRINTK2(CARDNAME ": smc_destructor\n");
wdenkfe8c2802002-11-03 00:38:21 +0000809}
810
811
812/*
813 * Open and Initialize the board
814 *
815 * Set up everything, reset the card, etc ..
816 *
817 */
wdenkb56ddc62003-09-15 21:14:37 +0000818static int smc_open (bd_t * bd)
wdenkfe8c2802002-11-03 00:38:21 +0000819{
wdenkb56ddc62003-09-15 21:14:37 +0000820 int i, err;
wdenkfe8c2802002-11-03 00:38:21 +0000821
wdenkf39748a2004-06-09 13:37:52 +0000822 PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000823
824 /* reset the hardware */
wdenkb56ddc62003-09-15 21:14:37 +0000825 smc_reset ();
826 smc_enable ();
wdenkfe8c2802002-11-03 00:38:21 +0000827
828 /* Configure the PHY */
829#ifndef CONFIG_SMC91111_EXT_PHY
wdenkb56ddc62003-09-15 21:14:37 +0000830 smc_phy_configure ();
wdenkfe8c2802002-11-03 00:38:21 +0000831#endif
832
wdenkfe8c2802002-11-03 00:38:21 +0000833 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
834/* SMC_SELECT_BANK(0); */
835/* SMC_outw(0, RPC_REG); */
wdenkb56ddc62003-09-15 21:14:37 +0000836 SMC_SELECT_BANK (1);
wdenk8bde7f72003-06-27 21:31:46 +0000837
wdenkb56ddc62003-09-15 21:14:37 +0000838 err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
839 if (err < 0) {
wdenk42dfe7a2004-03-14 22:25:36 +0000840 memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */
wdenkb56ddc62003-09-15 21:14:37 +0000841 return (-1); /* upper code ignores this, but NOT bi_enetaddr */
842 }
wdenkfe8c2802002-11-03 00:38:21 +0000843#ifdef USE_32_BIT
wdenkb56ddc62003-09-15 21:14:37 +0000844 for (i = 0; i < 6; i += 2) {
wdenkfe8c2802002-11-03 00:38:21 +0000845 word address;
846
wdenkb56ddc62003-09-15 21:14:37 +0000847 address = smc_mac_addr[i + 1] << 8;
848 address |= smc_mac_addr[i];
wdenk39539882004-07-01 16:30:44 +0000849 SMC_outw (address, (ADDR0_REG + i));
wdenkfe8c2802002-11-03 00:38:21 +0000850 }
851#else
wdenkb56ddc62003-09-15 21:14:37 +0000852 for (i = 0; i < 6; i++)
wdenk39539882004-07-01 16:30:44 +0000853 SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
wdenkfe8c2802002-11-03 00:38:21 +0000854#endif
855
856 return 0;
857}
858
wdenkfe8c2802002-11-03 00:38:21 +0000859/*-------------------------------------------------------------
860 .
861 . smc_rcv - receive a packet from the card
862 .
863 . There is ( at least ) a packet waiting to be read from
864 . chip-memory.
865 .
866 . o Read the status
867 . o If an error, record it
868 . o otherwise, read in the packet
869 --------------------------------------------------------------
870*/
871static int smc_rcv()
872{
wdenk42dfe7a2004-03-14 22:25:36 +0000873 int packet_number;
wdenkfe8c2802002-11-03 00:38:21 +0000874 word status;
875 word packet_length;
wdenk42dfe7a2004-03-14 22:25:36 +0000876 int is_error = 0;
wdenkfe8c2802002-11-03 00:38:21 +0000877#ifdef USE_32_BIT
878 dword stat_len;
879#endif
wdenk518e2e12004-03-25 14:59:05 +0000880 byte saved_pnr;
881 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000882
wdenkfe8c2802002-11-03 00:38:21 +0000883 SMC_SELECT_BANK(2);
wdenk518e2e12004-03-25 14:59:05 +0000884 /* save PTR and PTR registers */
885 saved_pnr = SMC_inb( PN_REG );
886 saved_ptr = SMC_inw( PTR_REG );
887
wdenkfe8c2802002-11-03 00:38:21 +0000888 packet_number = SMC_inw( RXFIFO_REG );
889
890 if ( packet_number & RXFIFO_REMPTY ) {
891
892 return 0;
893 }
894
wdenkf39748a2004-06-09 13:37:52 +0000895 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000896 /* start reading from the start of the packet */
897 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
898
899 /* First two words are status and packet_length */
900#ifdef USE_32_BIT
901 stat_len = SMC_inl(SMC91111_DATA_REG);
902 status = stat_len & 0xffff;
903 packet_length = stat_len >> 16;
904#else
wdenk42dfe7a2004-03-14 22:25:36 +0000905 status = SMC_inw( SMC91111_DATA_REG );
906 packet_length = SMC_inw( SMC91111_DATA_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000907#endif
908
909 packet_length &= 0x07ff; /* mask off top bits */
910
911 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
912
913 if ( !(status & RS_ERRORS ) ){
914 /* Adjust for having already read the first two words */
915 packet_length -= 4; /*4; */
916
917
wdenkfe8c2802002-11-03 00:38:21 +0000918 /* set odd length for bug in LAN91C111, */
919 /* which never sets RS_ODDFRAME */
920 /* TODO ? */
921
922
923#ifdef USE_32_BIT
924 PRINTK3(" Reading %d dwords (and %d bytes) \n",
925 packet_length >> 2, packet_length & 3 );
926 /* QUESTION: Like in the TX routine, do I want
927 to send the DWORDs or the bytes first, or some
928 mixture. A mixture might improve already slow PIO
wdenk42dfe7a2004-03-14 22:25:36 +0000929 performance */
wdenkfe8c2802002-11-03 00:38:21 +0000930 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
931 /* read the left over bytes */
932 if (packet_length & 3) {
933 int i;
934
wdenk699b13a2002-11-03 18:03:52 +0000935 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
wdenkfe8c2802002-11-03 00:38:21 +0000936 dword leftover = SMC_inl(SMC91111_DATA_REG);
937 for (i=0; i<(packet_length & 3); i++)
938 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
939 }
940#else
941 PRINTK3(" Reading %d words and %d byte(s) \n",
942 (packet_length >> 1 ), packet_length & 1 );
943 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
944
945#endif /* USE_32_BIT */
946
947#if SMC_DEBUG > 2
948 printf("Receiving Packet\n");
949 print_packet( NetRxPackets[0], packet_length );
950#endif
951 } else {
952 /* error ... */
953 /* TODO ? */
954 is_error = 1;
955 }
956
957 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
958 udelay(1); /* Wait until not busy */
959
960 /* error or good, tell the card to get rid of this packet */
961 SMC_outw( MC_RELEASE, MMU_CMD_REG );
962
963 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
964 udelay(1); /* Wait until not busy */
965
wdenk518e2e12004-03-25 14:59:05 +0000966 /* restore saved registers */
wdenk1f6d4252004-11-02 13:00:33 +0000967#ifndef CONFIG_XAENIAX
wdenk518e2e12004-03-25 14:59:05 +0000968 SMC_outb( saved_pnr, PN_REG );
wdenk1f6d4252004-11-02 13:00:33 +0000969#else
970 /* On Xaeniax board, we can't use SMC_outb here because that way
971 * the Allocate MMU command will end up written to the command register
972 * as well, which will lead to a problem.
973 */
974 SMC_outl( saved_pnr << 16, 0);
975#endif
wdenk518e2e12004-03-25 14:59:05 +0000976 SMC_outw( saved_ptr, PTR_REG );
977
wdenkfe8c2802002-11-03 00:38:21 +0000978 if (!is_error) {
979 /* Pass the packet up to the protocol layers. */
980 NetReceive(NetRxPackets[0], packet_length);
981 return packet_length;
982 } else {
983 return 0;
984 }
985
986}
987
988
wdenkfe8c2802002-11-03 00:38:21 +0000989/*----------------------------------------------------
990 . smc_close
991 .
992 . this makes the board clean up everything that it can
wdenk42dfe7a2004-03-14 22:25:36 +0000993 . and not talk to the outside world. Caused by
wdenkfe8c2802002-11-03 00:38:21 +0000994 . an 'ifconfig ethX down'
995 .
996 -----------------------------------------------------*/
997static int smc_close()
998{
wdenkf39748a2004-06-09 13:37:52 +0000999 PRINTK2("%s: smc_close\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001000
1001 /* clear everything */
1002 smc_shutdown();
1003
1004 return 0;
1005}
1006
1007
1008#if 0
1009/*------------------------------------------------------------
1010 . Modify a bit in the LAN91C111 register set
1011 .-------------------------------------------------------------*/
1012static word smc_modify_regbit(int bank, int ioaddr, int reg,
1013 unsigned int bit, int val)
1014{
1015 word regval;
1016
1017 SMC_SELECT_BANK( bank );
1018
1019 regval = SMC_inw( reg );
1020 if (val)
1021 regval |= bit;
1022 else
1023 regval &= ~bit;
1024
1025 SMC_outw( regval, 0 );
1026 return(regval);
1027}
1028
1029
1030/*------------------------------------------------------------
1031 . Retrieve a bit in the LAN91C111 register set
1032 .-------------------------------------------------------------*/
1033static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
1034{
1035 SMC_SELECT_BANK( bank );
1036 if ( SMC_inw( reg ) & bit)
1037 return(1);
1038 else
1039 return(0);
1040}
1041
1042
1043/*------------------------------------------------------------
1044 . Modify a LAN91C111 register (word access only)
1045 .-------------------------------------------------------------*/
1046static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
1047{
1048 SMC_SELECT_BANK( bank );
1049 SMC_outw( val, reg );
1050}
1051
1052
1053/*------------------------------------------------------------
1054 . Retrieve a LAN91C111 register (word access only)
1055 .-------------------------------------------------------------*/
1056static int smc_get_reg(int bank, int ioaddr, int reg)
1057{
1058 SMC_SELECT_BANK( bank );
1059 return(SMC_inw( reg ));
1060}
1061
1062#endif /* 0 */
1063
1064/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
1065
1066#if (SMC_DEBUG > 2 )
1067
1068/*------------------------------------------------------------
1069 . Debugging function for viewing MII Management serial bitstream
1070 .-------------------------------------------------------------*/
wdenkb56ddc62003-09-15 21:14:37 +00001071static void smc_dump_mii_stream (byte * bits, int size)
wdenkfe8c2802002-11-03 00:38:21 +00001072{
1073 int i;
1074
wdenkb56ddc62003-09-15 21:14:37 +00001075 printf ("BIT#:");
1076 for (i = 0; i < size; ++i) {
1077 printf ("%d", i % 10);
1078 }
wdenkfe8c2802002-11-03 00:38:21 +00001079
wdenkb56ddc62003-09-15 21:14:37 +00001080 printf ("\nMDOE:");
1081 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001082 if (bits[i] & MII_MDOE)
wdenkb56ddc62003-09-15 21:14:37 +00001083 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +00001084 else
wdenkb56ddc62003-09-15 21:14:37 +00001085 printf ("0");
1086 }
wdenkfe8c2802002-11-03 00:38:21 +00001087
wdenkb56ddc62003-09-15 21:14:37 +00001088 printf ("\nMDO :");
1089 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001090 if (bits[i] & MII_MDO)
wdenkb56ddc62003-09-15 21:14:37 +00001091 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +00001092 else
wdenkb56ddc62003-09-15 21:14:37 +00001093 printf ("0");
1094 }
wdenkfe8c2802002-11-03 00:38:21 +00001095
wdenkb56ddc62003-09-15 21:14:37 +00001096 printf ("\nMDI :");
1097 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001098 if (bits[i] & MII_MDI)
wdenkb56ddc62003-09-15 21:14:37 +00001099 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +00001100 else
wdenkb56ddc62003-09-15 21:14:37 +00001101 printf ("0");
1102 }
wdenkfe8c2802002-11-03 00:38:21 +00001103
wdenkb56ddc62003-09-15 21:14:37 +00001104 printf ("\n");
wdenkfe8c2802002-11-03 00:38:21 +00001105}
1106#endif
1107
1108/*------------------------------------------------------------
1109 . Reads a register from the MII Management serial interface
1110 .-------------------------------------------------------------*/
1111#ifndef CONFIG_SMC91111_EXT_PHY
wdenkb56ddc62003-09-15 21:14:37 +00001112static word smc_read_phy_register (byte phyreg)
wdenkfe8c2802002-11-03 00:38:21 +00001113{
1114 int oldBank;
1115 int i;
1116 byte mask;
1117 word mii_reg;
1118 byte bits[64];
1119 int clk_idx = 0;
1120 int input_idx;
1121 word phydata;
1122 byte phyaddr = SMC_PHY_ADDR;
1123
1124 /* 32 consecutive ones on MDO to establish sync */
1125 for (i = 0; i < 32; ++i)
1126 bits[clk_idx++] = MII_MDOE | MII_MDO;
1127
1128 /* Start code <01> */
1129 bits[clk_idx++] = MII_MDOE;
1130 bits[clk_idx++] = MII_MDOE | MII_MDO;
1131
1132 /* Read command <10> */
1133 bits[clk_idx++] = MII_MDOE | MII_MDO;
1134 bits[clk_idx++] = MII_MDOE;
1135
1136 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001137 mask = (byte) 0x10;
1138 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001139 if (phyaddr & mask)
1140 bits[clk_idx++] = MII_MDOE | MII_MDO;
1141 else
1142 bits[clk_idx++] = MII_MDOE;
1143
1144 /* Shift to next lowest bit */
1145 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001146 }
wdenkfe8c2802002-11-03 00:38:21 +00001147
1148 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001149 mask = (byte) 0x10;
1150 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001151 if (phyreg & mask)
1152 bits[clk_idx++] = MII_MDOE | MII_MDO;
1153 else
1154 bits[clk_idx++] = MII_MDOE;
1155
1156 /* Shift to next lowest bit */
1157 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001158 }
wdenkfe8c2802002-11-03 00:38:21 +00001159
1160 /* Tristate and turnaround (2 bit times) */
1161 bits[clk_idx++] = 0;
1162 /*bits[clk_idx++] = 0; */
1163
1164 /* Input starts at this bit time */
1165 input_idx = clk_idx;
1166
1167 /* Will input 16 bits */
1168 for (i = 0; i < 16; ++i)
1169 bits[clk_idx++] = 0;
1170
1171 /* Final clock bit */
1172 bits[clk_idx++] = 0;
1173
1174 /* Save the current bank */
wdenkb56ddc62003-09-15 21:14:37 +00001175 oldBank = SMC_inw (BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001176
1177 /* Select bank 3 */
wdenkb56ddc62003-09-15 21:14:37 +00001178 SMC_SELECT_BANK (3);
wdenkfe8c2802002-11-03 00:38:21 +00001179
1180 /* Get the current MII register value */
wdenkb56ddc62003-09-15 21:14:37 +00001181 mii_reg = SMC_inw (MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001182
1183 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001184 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001185
1186 /* Clock all 64 cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001187 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001188 /* Clock Low - output data */
wdenkb56ddc62003-09-15 21:14:37 +00001189 SMC_outw (mii_reg | bits[i], MII_REG);
1190 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001191
1192
1193 /* Clock Hi - input data */
wdenkb56ddc62003-09-15 21:14:37 +00001194 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1195 udelay (SMC_PHY_CLOCK_DELAY);
1196 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1197 }
wdenkfe8c2802002-11-03 00:38:21 +00001198
1199 /* Return to idle state */
1200 /* Set clock to low, data to low, and output tristated */
wdenkb56ddc62003-09-15 21:14:37 +00001201 SMC_outw (mii_reg, MII_REG);
1202 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001203
1204 /* Restore original bank select */
wdenkb56ddc62003-09-15 21:14:37 +00001205 SMC_SELECT_BANK (oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001206
1207 /* Recover input data */
1208 phydata = 0;
wdenkb56ddc62003-09-15 21:14:37 +00001209 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001210 phydata <<= 1;
1211
1212 if (bits[input_idx++] & MII_MDI)
1213 phydata |= 0x0001;
wdenkb56ddc62003-09-15 21:14:37 +00001214 }
wdenkfe8c2802002-11-03 00:38:21 +00001215
1216#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001217 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001218 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001219 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001220#endif
1221
wdenkb56ddc62003-09-15 21:14:37 +00001222 return (phydata);
wdenkfe8c2802002-11-03 00:38:21 +00001223}
1224
1225
1226/*------------------------------------------------------------
1227 . Writes a register to the MII Management serial interface
1228 .-------------------------------------------------------------*/
wdenkb56ddc62003-09-15 21:14:37 +00001229static void smc_write_phy_register (byte phyreg, word phydata)
wdenkfe8c2802002-11-03 00:38:21 +00001230{
1231 int oldBank;
1232 int i;
1233 word mask;
1234 word mii_reg;
1235 byte bits[65];
1236 int clk_idx = 0;
1237 byte phyaddr = SMC_PHY_ADDR;
1238
1239 /* 32 consecutive ones on MDO to establish sync */
1240 for (i = 0; i < 32; ++i)
1241 bits[clk_idx++] = MII_MDOE | MII_MDO;
1242
1243 /* Start code <01> */
1244 bits[clk_idx++] = MII_MDOE;
1245 bits[clk_idx++] = MII_MDOE | MII_MDO;
1246
1247 /* Write command <01> */
1248 bits[clk_idx++] = MII_MDOE;
1249 bits[clk_idx++] = MII_MDOE | MII_MDO;
1250
1251 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001252 mask = (byte) 0x10;
1253 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001254 if (phyaddr & mask)
1255 bits[clk_idx++] = MII_MDOE | MII_MDO;
1256 else
1257 bits[clk_idx++] = MII_MDOE;
1258
1259 /* Shift to next lowest bit */
1260 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001261 }
wdenkfe8c2802002-11-03 00:38:21 +00001262
1263 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001264 mask = (byte) 0x10;
1265 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001266 if (phyreg & mask)
1267 bits[clk_idx++] = MII_MDOE | MII_MDO;
1268 else
1269 bits[clk_idx++] = MII_MDOE;
1270
1271 /* Shift to next lowest bit */
1272 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001273 }
wdenkfe8c2802002-11-03 00:38:21 +00001274
1275 /* Tristate and turnaround (2 bit times) */
1276 bits[clk_idx++] = 0;
1277 bits[clk_idx++] = 0;
1278
1279 /* Write out 16 bits of data, msb first */
1280 mask = 0x8000;
wdenkb56ddc62003-09-15 21:14:37 +00001281 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001282 if (phydata & mask)
1283 bits[clk_idx++] = MII_MDOE | MII_MDO;
1284 else
1285 bits[clk_idx++] = MII_MDOE;
1286
1287 /* Shift to next lowest bit */
1288 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001289 }
wdenkfe8c2802002-11-03 00:38:21 +00001290
1291 /* Final clock bit (tristate) */
1292 bits[clk_idx++] = 0;
1293
1294 /* Save the current bank */
wdenkb56ddc62003-09-15 21:14:37 +00001295 oldBank = SMC_inw (BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001296
1297 /* Select bank 3 */
wdenkb56ddc62003-09-15 21:14:37 +00001298 SMC_SELECT_BANK (3);
wdenkfe8c2802002-11-03 00:38:21 +00001299
1300 /* Get the current MII register value */
wdenkb56ddc62003-09-15 21:14:37 +00001301 mii_reg = SMC_inw (MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001302
1303 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001304 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001305
1306 /* Clock all cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001307 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001308 /* Clock Low - output data */
wdenkb56ddc62003-09-15 21:14:37 +00001309 SMC_outw (mii_reg | bits[i], MII_REG);
1310 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001311
1312
1313 /* Clock Hi - input data */
wdenkb56ddc62003-09-15 21:14:37 +00001314 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1315 udelay (SMC_PHY_CLOCK_DELAY);
1316 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1317 }
wdenkfe8c2802002-11-03 00:38:21 +00001318
1319 /* Return to idle state */
1320 /* Set clock to low, data to low, and output tristated */
wdenkb56ddc62003-09-15 21:14:37 +00001321 SMC_outw (mii_reg, MII_REG);
1322 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001323
1324 /* Restore original bank select */
wdenkb56ddc62003-09-15 21:14:37 +00001325 SMC_SELECT_BANK (oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001326
1327#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001328 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001329 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001330 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001331#endif
1332}
1333#endif /* !CONFIG_SMC91111_EXT_PHY */
1334
1335
wdenkfe8c2802002-11-03 00:38:21 +00001336/*------------------------------------------------------------
1337 . Waits the specified number of milliseconds - kernel friendly
1338 .-------------------------------------------------------------*/
1339#ifndef CONFIG_SMC91111_EXT_PHY
1340static void smc_wait_ms(unsigned int ms)
1341{
1342 udelay(ms*1000);
1343}
1344#endif /* !CONFIG_SMC91111_EXT_PHY */
1345
1346
wdenkfe8c2802002-11-03 00:38:21 +00001347/*------------------------------------------------------------
1348 . Configures the specified PHY using Autonegotiation. Calls
1349 . smc_phy_fixed() if the user has requested a certain config.
1350 .-------------------------------------------------------------*/
1351#ifndef CONFIG_SMC91111_EXT_PHY
wdenkb56ddc62003-09-15 21:14:37 +00001352static void smc_phy_configure ()
wdenkfe8c2802002-11-03 00:38:21 +00001353{
1354 int timeout;
1355 byte phyaddr;
wdenkb56ddc62003-09-15 21:14:37 +00001356 word my_phy_caps; /* My PHY capabilities */
1357 word my_ad_caps; /* My Advertised capabilities */
1358 word status = 0; /*;my status = 0 */
wdenkfe8c2802002-11-03 00:38:21 +00001359 int failed = 0;
1360
wdenkf39748a2004-06-09 13:37:52 +00001361 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001362
1363
wdenkfe8c2802002-11-03 00:38:21 +00001364 /* Get the detected phy address */
1365 phyaddr = SMC_PHY_ADDR;
1366
1367 /* Reset the PHY, setting all other bits to zero */
wdenkb56ddc62003-09-15 21:14:37 +00001368 smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001369
1370 /* Wait for the reset to complete, or time out */
wdenkb56ddc62003-09-15 21:14:37 +00001371 timeout = 6; /* Wait up to 3 seconds */
1372 while (timeout--) {
1373 if (!(smc_read_phy_register (PHY_CNTL_REG)
1374 & PHY_CNTL_RST)) {
wdenkfe8c2802002-11-03 00:38:21 +00001375 /* reset complete */
1376 break;
wdenkfe8c2802002-11-03 00:38:21 +00001377 }
1378
wdenkb56ddc62003-09-15 21:14:37 +00001379 smc_wait_ms (500); /* wait 500 millisecs */
1380 }
1381
1382 if (timeout < 1) {
1383 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001384 goto smc_phy_configure_exit;
wdenkb56ddc62003-09-15 21:14:37 +00001385 }
wdenkfe8c2802002-11-03 00:38:21 +00001386
1387 /* Read PHY Register 18, Status Output */
1388 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1389
1390 /* Enable PHY Interrupts (for register 18) */
1391 /* Interrupts listed here are disabled */
wdenk8bf3b002003-12-06 23:20:41 +00001392 smc_write_phy_register (PHY_MASK_REG, 0xffff);
wdenkfe8c2802002-11-03 00:38:21 +00001393
1394 /* Configure the Receive/Phy Control register */
wdenkb56ddc62003-09-15 21:14:37 +00001395 SMC_SELECT_BANK (0);
1396 SMC_outw (RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001397
1398 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
wdenkb56ddc62003-09-15 21:14:37 +00001399 my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
1400 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
wdenkfe8c2802002-11-03 00:38:21 +00001401
1402 if (my_phy_caps & PHY_STAT_CAP_T4)
1403 my_ad_caps |= PHY_AD_T4;
1404
1405 if (my_phy_caps & PHY_STAT_CAP_TXF)
1406 my_ad_caps |= PHY_AD_TX_FDX;
1407
1408 if (my_phy_caps & PHY_STAT_CAP_TXH)
1409 my_ad_caps |= PHY_AD_TX_HDX;
1410
1411 if (my_phy_caps & PHY_STAT_CAP_TF)
1412 my_ad_caps |= PHY_AD_10_FDX;
1413
1414 if (my_phy_caps & PHY_STAT_CAP_TH)
1415 my_ad_caps |= PHY_AD_10_HDX;
1416
1417 /* Update our Auto-Neg Advertisement Register */
wdenkb56ddc62003-09-15 21:14:37 +00001418 smc_write_phy_register (PHY_AD_REG, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001419
wdenk518e2e12004-03-25 14:59:05 +00001420 /* Read the register back. Without this, it appears that when */
1421 /* auto-negotiation is restarted, sometimes it isn't ready and */
1422 /* the link does not come up. */
1423 smc_read_phy_register(PHY_AD_REG);
1424
wdenkf39748a2004-06-09 13:37:52 +00001425 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1426 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001427
1428 /* Restart auto-negotiation process in order to advertise my caps */
wdenkb56ddc62003-09-15 21:14:37 +00001429 smc_write_phy_register (PHY_CNTL_REG,
1430 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001431
1432 /* Wait for the auto-negotiation to complete. This may take from */
1433 /* 2 to 3 seconds. */
1434 /* Wait for the reset to complete, or time out */
wdenkf39748a2004-06-09 13:37:52 +00001435 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
wdenkb56ddc62003-09-15 21:14:37 +00001436 while (timeout--) {
wdenkf39748a2004-06-09 13:37:52 +00001437
wdenkb56ddc62003-09-15 21:14:37 +00001438 status = smc_read_phy_register (PHY_STAT_REG);
1439 if (status & PHY_STAT_ANEG_ACK) {
wdenkfe8c2802002-11-03 00:38:21 +00001440 /* auto-negotiate complete */
1441 break;
wdenkb56ddc62003-09-15 21:14:37 +00001442 }
wdenkfe8c2802002-11-03 00:38:21 +00001443
wdenkb56ddc62003-09-15 21:14:37 +00001444 smc_wait_ms (500); /* wait 500 millisecs */
wdenkfe8c2802002-11-03 00:38:21 +00001445
1446 /* Restart auto-negotiation if remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001447 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001448 printf ("%s: PHY remote fault detected\n",
wdenkb56ddc62003-09-15 21:14:37 +00001449 SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001450
1451 /* Restart auto-negotiation */
wdenkf39748a2004-06-09 13:37:52 +00001452 printf ("%s: PHY restarting auto-negotiation\n",
wdenkfe8c2802002-11-03 00:38:21 +00001453 SMC_DEV_NAME);
wdenkb56ddc62003-09-15 21:14:37 +00001454 smc_write_phy_register (PHY_CNTL_REG,
1455 PHY_CNTL_ANEG_EN |
1456 PHY_CNTL_ANEG_RST |
1457 PHY_CNTL_SPEED |
1458 PHY_CNTL_DPLX);
wdenkfe8c2802002-11-03 00:38:21 +00001459 }
wdenkb56ddc62003-09-15 21:14:37 +00001460 }
wdenkfe8c2802002-11-03 00:38:21 +00001461
wdenkb56ddc62003-09-15 21:14:37 +00001462 if (timeout < 1) {
wdenkf39748a2004-06-09 13:37:52 +00001463 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001464 failed = 1;
wdenkb56ddc62003-09-15 21:14:37 +00001465 }
wdenkfe8c2802002-11-03 00:38:21 +00001466
1467 /* Fail if we detected an auto-negotiate remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001468 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001469 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001470 failed = 1;
wdenkb56ddc62003-09-15 21:14:37 +00001471 }
wdenkfe8c2802002-11-03 00:38:21 +00001472
1473 /* Re-Configure the Receive/Phy Control register */
wdenkb56ddc62003-09-15 21:14:37 +00001474 SMC_outw (RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001475
wdenk26238132004-07-09 22:51:01 +00001476smc_phy_configure_exit: ;
wdenkfe8c2802002-11-03 00:38:21 +00001477
1478}
1479#endif /* !CONFIG_SMC91111_EXT_PHY */
1480
1481
1482#if SMC_DEBUG > 2
1483static void print_packet( byte * buf, int length )
1484{
wdenk8bde7f72003-06-27 21:31:46 +00001485 int i;
1486 int remainder;
1487 int lines;
wdenkfe8c2802002-11-03 00:38:21 +00001488
wdenk8bde7f72003-06-27 21:31:46 +00001489 printf("Packet of length %d \n", length );
wdenkfe8c2802002-11-03 00:38:21 +00001490
1491#if SMC_DEBUG > 3
wdenk8bde7f72003-06-27 21:31:46 +00001492 lines = length / 16;
1493 remainder = length % 16;
wdenkfe8c2802002-11-03 00:38:21 +00001494
wdenk8bde7f72003-06-27 21:31:46 +00001495 for ( i = 0; i < lines ; i ++ ) {
1496 int cur;
wdenkfe8c2802002-11-03 00:38:21 +00001497
wdenk8bde7f72003-06-27 21:31:46 +00001498 for ( cur = 0; cur < 8; cur ++ ) {
1499 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001500
wdenk8bde7f72003-06-27 21:31:46 +00001501 a = *(buf ++ );
1502 b = *(buf ++ );
1503 printf("%02x%02x ", a, b );
1504 }
1505 printf("\n");
1506 }
1507 for ( i = 0; i < remainder/2 ; i++ ) {
1508 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001509
wdenk8bde7f72003-06-27 21:31:46 +00001510 a = *(buf ++ );
1511 b = *(buf ++ );
1512 printf("%02x%02x ", a, b );
1513 }
1514 printf("\n");
wdenkfe8c2802002-11-03 00:38:21 +00001515#endif
wdenkfe8c2802002-11-03 00:38:21 +00001516}
1517#endif
1518
1519int eth_init(bd_t *bd) {
Wolfgang Denk0afe5192006-03-12 02:10:00 +01001520#ifdef SHARED_RESOURCES
1521 swap_to(ETHERNET);
1522#endif
wdenk0b97ab12003-06-19 23:58:30 +00001523 return (smc_open(bd));
wdenkfe8c2802002-11-03 00:38:21 +00001524}
1525
1526void eth_halt() {
1527 smc_close();
1528}
1529
1530int eth_rx() {
1531 return smc_rcv();
1532}
1533
1534int eth_send(volatile void *packet, int length) {
1535 return smc_send_packet(packet, length);
1536}
1537
wdenkb56ddc62003-09-15 21:14:37 +00001538int smc_get_ethaddr (bd_t * bd)
wdenk0b97ab12003-06-19 23:58:30 +00001539{
wdenkb56ddc62003-09-15 21:14:37 +00001540 int env_size, rom_valid, env_present = 0, reg;
1541 char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +01001542 char s_env_mac[64];
1543 uchar v_env_mac[6], v_rom_mac[6];
wdenk0b97ab12003-06-19 23:58:30 +00001544
wdenkb56ddc62003-09-15 21:14:37 +00001545 env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
1546 if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */
1547 printf ("\n*** ERROR: ethaddr is not set properly!!\n");
1548 return (-1);
wdenk8bde7f72003-06-27 21:31:46 +00001549 }
wdenk8bde7f72003-06-27 21:31:46 +00001550
wdenkb56ddc62003-09-15 21:14:37 +00001551 if (env_size > 0) {
1552 env_present = 1;
1553 s = s_env_mac;
wdenk8bde7f72003-06-27 21:31:46 +00001554 }
wdenkb56ddc62003-09-15 21:14:37 +00001555
wdenk42dfe7a2004-03-14 22:25:36 +00001556 for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
wdenkb56ddc62003-09-15 21:14:37 +00001557 v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
1558 if (s)
1559 s = (*e) ? e + 1 : e;
1560 }
1561
1562 rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */
1563
1564 if (!env_present) { /* if NO env */
1565 if (rom_valid) { /* but ROM is valid */
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +01001566 v_mac = (char *)v_rom_mac;
wdenkb56ddc62003-09-15 21:14:37 +00001567 sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
1568 v_mac[0], v_mac[1], v_mac[2], v_mac[3],
1569 v_mac[4], v_mac[5]);
1570 setenv ("ethaddr", s_env_mac);
1571 } else { /* no env, bad ROM */
1572 printf ("\n*** ERROR: ethaddr is NOT set !!\n");
1573 return (-1);
1574 }
1575 } else { /* good env, don't care ROM */
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +01001576 v_mac = (char *)v_env_mac; /* always use a good env over a ROM */
wdenkb56ddc62003-09-15 21:14:37 +00001577 }
1578
wdenk42dfe7a2004-03-14 22:25:36 +00001579 if (env_present && rom_valid) { /* if both env and ROM are good */
wdenkb56ddc62003-09-15 21:14:37 +00001580 if (memcmp (v_env_mac, v_rom_mac, 6) != 0) {
wdenkb56ddc62003-09-15 21:14:37 +00001581 printf ("\nWarning: MAC addresses don't match:\n");
1582 printf ("\tHW MAC address: "
1583 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1584 v_rom_mac[0], v_rom_mac[1],
1585 v_rom_mac[2], v_rom_mac[3],
1586 v_rom_mac[4], v_rom_mac[5] );
1587 printf ("\t\"ethaddr\" value: "
1588 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1589 v_env_mac[0], v_env_mac[1],
1590 v_env_mac[2], v_env_mac[3],
1591 v_env_mac[4], v_env_mac[5]) ;
1592 debug ("### Set MAC addr from environment\n");
wdenkb56ddc62003-09-15 21:14:37 +00001593 }
1594 }
1595 memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +01001596 smc_set_mac_addr ((uchar *)v_mac); /* use old function to update smc default */
wdenk3d3befa2004-03-14 15:06:13 +00001597 PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
wdenk42dfe7a2004-03-14 22:25:36 +00001598 v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
wdenkb56ddc62003-09-15 21:14:37 +00001599 return (0);
wdenk0b97ab12003-06-19 23:58:30 +00001600}
1601
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +01001602int get_rom_mac (uchar *v_rom_mac)
wdenk0b97ab12003-06-19 23:58:30 +00001603{
wdenkb56ddc62003-09-15 21:14:37 +00001604#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
1605 char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
1606
1607 memcpy (v_rom_mac, hw_mac_addr, 6);
1608 return (1);
wdenk0b97ab12003-06-19 23:58:30 +00001609#else
wdenk3d3befa2004-03-14 15:06:13 +00001610 int i;
wdenkf39748a2004-06-09 13:37:52 +00001611 int valid_mac = 0;
1612
wdenk3d3befa2004-03-14 15:06:13 +00001613 SMC_SELECT_BANK (1);
1614 for (i=0; i<6; i++)
1615 {
wdenk39539882004-07-01 16:30:44 +00001616 v_rom_mac[i] = SMC_inb ((ADDR0_REG + i));
wdenkf39748a2004-06-09 13:37:52 +00001617 valid_mac |= v_rom_mac[i];
wdenkb56ddc62003-09-15 21:14:37 +00001618 }
wdenkf39748a2004-06-09 13:37:52 +00001619
1620 return (valid_mac ? 1 : 0);
wdenk0b97ab12003-06-19 23:58:30 +00001621#endif
1622}
wdenkfe8c2802002-11-03 00:38:21 +00001623#endif /* CONFIG_DRIVER_SMC91111 */