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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk024a26b2002-08-21 21:35:08 +00002/*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk024a26b2002-08-21 21:35:08 +00005 */
6
Wolfgang Denk53677ef2008-05-20 16:00:29 +02007#include <linux/types.h> /* for ulong typedef */
wdenk024a26b2002-08-21 21:35:08 +00008
9#ifndef _FPGA_H_
10#define _FPGA_H_
11
12#ifndef CONFIG_MAX_FPGA_DEVICES
13#define CONFIG_MAX_FPGA_DEVICES 5
14#endif
15
wdenk024a26b2002-08-21 21:35:08 +000016/* fpga_xxxx function return value definitions */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020017#define FPGA_SUCCESS 0
Alexander Dahl5a4675a2019-06-28 14:41:24 +020018#define FPGA_FAIL 1
wdenk024a26b2002-08-21 21:35:08 +000019
20/* device numbers must be non-negative */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020021#define FPGA_INVALID_DEVICE -1
wdenk024a26b2002-08-21 21:35:08 +000022
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053023#define FPGA_ENC_USR_KEY 1
24#define FPGA_NO_ENC_OR_NO_AUTH 2
25
wdenk024a26b2002-08-21 21:35:08 +000026/* root data type defintions */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020027typedef enum { /* typedef fpga_type */
28 fpga_min_type, /* range check value */
29 fpga_xilinx, /* Xilinx Family) */
30 fpga_altera, /* unimplemented */
Stefano Babic3b8ac462010-06-29 11:47:48 +020031 fpga_lattice, /* Lattice family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020032 fpga_undefined /* invalid range check value */
33} fpga_type; /* end, typedef fpga_type */
wdenk024a26b2002-08-21 21:35:08 +000034
Wolfgang Denk53677ef2008-05-20 16:00:29 +020035typedef struct { /* typedef fpga_desc */
36 fpga_type devtype; /* switch value to select sub-functions */
37 void *devdesc; /* real device descriptor */
38} fpga_desc; /* end, typedef fpga_desc */
wdenk024a26b2002-08-21 21:35:08 +000039
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053040typedef struct { /* typedef fpga_desc */
41 unsigned int blocksize;
42 char *interface;
43 char *dev_part;
Tien Fong Chee3003c442019-02-15 15:57:07 +080044 const char *filename;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053045 int fstype;
46} fpga_fs_info;
wdenk024a26b2002-08-21 21:35:08 +000047
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053048struct fpga_secure_info {
49 u8 *userkey_addr;
50 u8 authflag;
51 u8 encflag;
52};
53
Michal Simek7a78bd22014-05-02 14:09:30 +020054typedef enum {
55 BIT_FULL = 0,
Michal Simek67193862014-05-02 13:43:39 +020056 BIT_PARTIAL,
Siva Durga Prasad Paladuguddbcf8f2015-12-09 18:46:42 +053057 BIT_NONE = 0xFF,
Michal Simek7a78bd22014-05-02 14:09:30 +020058} bitstream_type;
59
wdenk024a26b2002-08-21 21:35:08 +000060/* root function definitions */
Michal Simek65835052015-01-14 09:59:00 +010061void fpga_init(void);
62int fpga_add(fpga_type devtype, void *desc);
63int fpga_count(void);
Michal Simekebd322d2015-01-13 16:09:53 +010064const fpga_desc *const fpga_get_desc(int devnum);
Goldschmidt Simon8b93a922017-11-10 14:17:41 +000065int fpga_is_partial_data(int devnum, size_t img_len);
Michal Simek65835052015-01-14 09:59:00 +010066int fpga_load(int devnum, const void *buf, size_t bsize,
Oleksandr Suvorov282eed52022-07-22 17:16:07 +030067 bitstream_type bstype, int flags);
Michal Simek65835052015-01-14 09:59:00 +010068int fpga_fsload(int devnum, const void *buf, size_t size,
69 fpga_fs_info *fpga_fsinfo);
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053070int fpga_loads(int devnum, const void *buf, size_t size,
71 struct fpga_secure_info *fpga_sec_info);
Michal Simek65835052015-01-14 09:59:00 +010072int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
73 bitstream_type bstype);
74int fpga_dump(int devnum, const void *buf, size_t bsize);
75int fpga_info(int devnum);
76const fpga_desc *const fpga_validate(int devnum, const void *buf,
77 size_t bsize, char *fn);
wdenk024a26b2002-08-21 21:35:08 +000078
79#endif /* _FPGA_H_ */