blob: c0c8c16fd9c274aaacd2bd2ac69c615660e799c1 [file] [log] [blame]
Sam Protsenko3457bba2016-04-13 14:20:25 +03001config USB_DWC3
2 bool "DesignWare USB3 DRD Core Support"
Tom Rinibe5c0602021-07-09 10:11:56 -04003 depends on USB_XHCI_HCD || USB_GADGET
Sam Protsenko3457bba2016-04-13 14:20:25 +03004 help
5 Say Y here if your system has a Dual Role SuperSpeed
6 USB controller based on the DesignWare USB3 IP Core.
Sam Protsenko65403f32016-04-13 14:20:27 +03007
8if USB_DWC3
9
Sam Protsenko65403f32016-04-13 14:20:27 +030010config USB_DWC3_GADGET
Jean-Jacques Hiblot3e6ab732019-09-11 11:33:53 +020011 bool "USB Gadget support for DWC3"
12 default y
Sam Protsenko65403f32016-04-13 14:20:27 +030013 depends on USB_GADGET
Masahiro Yamada6ea247d2017-08-25 01:30:20 +090014 select USB_GADGET_DUALSPEED
Sam Protsenko65403f32016-04-13 14:20:27 +030015
Sam Protsenkoc16bf622016-04-13 14:20:28 +030016comment "Platform Glue Driver Support"
17
18config USB_DWC3_OMAP
19 bool "Texas Instruments OMAP5 and similar Platforms"
20 help
21 Some platforms from Texas Instruments like OMAP5, DRA7xxx and
22 AM437x use this IP for USB2/3 functionality.
23
24 Say 'Y' here if you have one such device
25
Michal Simek49d67452018-05-18 13:15:06 +020026config USB_DWC3_GENERIC
Jean-Jacques Hiblot446e3a22018-11-29 10:52:48 +010027 bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue)"
28 depends on DM_USB && USB_DWC3 && MISC
Michal Simek49d67452018-05-18 13:15:06 +020029 help
Jean-Jacques Hiblot446e3a22018-11-29 10:52:48 +010030 Select this for Xilinx ZynqMP and similar Platforms.
31 This wrapper supports Host and Peripheral operation modes.
Michal Simek49d67452018-05-18 13:15:06 +020032
Angus Ainslie582ce232022-07-14 08:11:11 -070033config SPL_USB_DWC3_GENERIC
34 bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue) for the SPL"
35 depends on SPL_DM_USB && USB_DWC3 && SPL_MISC
36 help
37 Select this for Xilinx ZynqMP and similar Platforms.
38 This wrapper supports Host and Peripheral operation modes.
39
Neil Armstrongadb049a2019-02-19 13:42:01 +010040config USB_DWC3_MESON_G12A
41 bool "Amlogic Meson G12A USB wrapper"
42 depends on DM_USB && USB_DWC3 && ARCH_MESON
Marek Vasute61eaee2023-02-23 17:32:43 +010043 select PHY
Neil Armstrongadb049a2019-02-19 13:42:01 +010044 help
45 Select this for Amlogic Meson G12A Platforms.
46 This wrapper supports Host and Peripheral operation modes.
47
Neil Armstrong46eddbc2020-09-10 10:48:13 +020048config USB_DWC3_MESON_GXL
49 bool "Amlogic Meson GXL USB wrapper"
50 depends on DM_USB && USB_DWC3 && ARCH_MESON
Marek Vasute61eaee2023-02-23 17:32:43 +010051 select PHY
Neil Armstrong46eddbc2020-09-10 10:48:13 +020052 help
53 Select this for Amlogic Meson GXL and GXM Platforms.
54 This wrapper supports Host and Peripheral operation modes.
55
Masahiro Yamadadc04b352017-09-28 22:01:00 +090056config USB_DWC3_UNIPHIER
57 bool "DesignWare USB3 Host Support on UniPhier Platforms"
Kunihiko Hayashiec01e0b2023-02-20 14:50:33 +090058 depends on ARCH_UNIPHIER && USB_DWC3
59 select USB_DWC3_GENERIC
Marek Vasutb684ec82023-02-23 17:29:24 +010060 select PHY
Kunihiko Hayashiec01e0b2023-02-20 14:50:33 +090061 select PHY_UNIPHIER_USB3
Masahiro Yamadadc04b352017-09-28 22:01:00 +090062 help
63 Support of USB2/3 functionality in Socionext UniPhier platforms.
64 Say 'Y' here if you have one such device.
65
Michael Walle2b0b51d2021-10-15 15:15:23 +020066config USB_DWC3_LAYERSCAPE
67 bool "Freescale Layerscape platform support"
68 depends on DM_USB && USB_DWC3
69 depends on !USB_XHCI_FSL
70 help
71 Select this for Freescale Layerscape Platforms.
72
73 Host and Peripheral operation modes are supported. OTG is not
74 supported.
75
Sam Protsenkob1427292016-04-13 14:20:29 +030076menu "PHY Subsystem"
77
78config USB_DWC3_PHY_OMAP
79 bool "TI OMAP SoC series USB DRD PHY driver"
80 help
81 Enable single driver for both USB2 PHY programming and USB3 PHY
82 programming for TI SoCs.
83
84config USB_DWC3_PHY_SAMSUNG
85 bool "Exynos5 SoC series USB DRD PHY driver"
86 help
87 Enable USB DRD PHY support for Exynos 5 SoC series.
88 This driver provides PHY interface for USB 3.0 DRD controller
89 present on Exynos5 SoC series.
90
91endmenu
92
Sam Protsenko65403f32016-04-13 14:20:27 +030093endif