blob: f28f350fcc86923545139a94501dfcbcde7e6246 [file] [log] [blame]
Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
Paul Gortmaker2738bc82009-09-20 20:36:06 -04002 * Copyright 2007,2009 Wind River Systems <www.windriver.com>
Joe Hamman9e3ed392007-12-13 06:45:14 -06003 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Joe Hamman9e3ed392007-12-13 06:45:14 -06007 */
8
9/*
10 * sbc8548 board configuration file
Paul Gortmaker2738bc82009-09-20 20:36:06 -040011 * Please refer to doc/README.sbc8548 for more info.
Joe Hamman9e3ed392007-12-13 06:45:14 -060012 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Paul Gortmaker2738bc82009-09-20 20:36:06 -040016/*
17 * Top level Makefile configuration choices
18 */
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020019#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000020#define CONFIG_PCI_INDIRECT_BRIDGE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040021#define CONFIG_PCI1
22#endif
23
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020024#ifdef CONFIG_66
Paul Gortmaker2738bc82009-09-20 20:36:06 -040025#define CONFIG_SYS_CLK_DIV 1
26#endif
27
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020028#ifdef CONFIG_33
Paul Gortmaker2738bc82009-09-20 20:36:06 -040029#define CONFIG_SYS_CLK_DIV 2
30#endif
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_PCIE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040033#define CONFIG_PCIE1
34#endif
35
36/*
37 * High Level Configuration Options
38 */
Joe Hamman9e3ed392007-12-13 06:45:14 -060039#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
Joe Hamman9e3ed392007-12-13 06:45:14 -060041#define CONFIG_MPC8548 1 /* MPC8548 specific */
42#define CONFIG_SBC8548 1 /* SBC8548 board specific */
43
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050044/*
45 * If you want to boot from the SODIMM flash, instead of the soldered
46 * on flash, set this, and change JP12, SW2:8 accordingly.
47 */
48#undef CONFIG_SYS_ALT_BOOT
49
Wolfgang Denk2ae18242010-10-06 09:05:45 +020050#ifndef CONFIG_SYS_TEXT_BASE
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050051#ifdef CONFIG_SYS_ALT_BOOT
52#define CONFIG_SYS_TEXT_BASE 0xfff00000
53#else
Wolfgang Denk2ae18242010-10-06 09:05:45 +020054#define CONFIG_SYS_TEXT_BASE 0xfffa0000
55#endif
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050056#endif
Wolfgang Denk2ae18242010-10-06 09:05:45 +020057
Joe Hamman9e3ed392007-12-13 06:45:14 -060058#undef CONFIG_RIO
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040059
60#ifdef CONFIG_PCI
61#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
62#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
63#endif
64#ifdef CONFIG_PCIE1
65#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
66#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -060067
68#define CONFIG_TSEC_ENET /* tsec ethernet support */
69#define CONFIG_ENV_OVERWRITE
Joe Hamman9e3ed392007-12-13 06:45:14 -060070
Joe Hamman9e3ed392007-12-13 06:45:14 -060071#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
72
Kumar Galae2b159d2008-01-16 09:05:27 -060073#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060074
Paul Gortmaker2738bc82009-09-20 20:36:06 -040075/*
76 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
77 */
78#ifndef CONFIG_SYS_CLK_DIV
79#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
80#endif
81#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -060082
83/*
84 * These can be toggled for performance analysis, otherwise use default.
85 */
86#define CONFIG_L2_CACHE /* toggle L2 cache */
87#define CONFIG_BTB /* toggle branch predition */
Joe Hamman9e3ed392007-12-13 06:45:14 -060088
89/*
90 * Only possible on E500 Version 2 or newer cores.
91 */
92#define CONFIG_ENABLE_36BIT_PHYS 1
93
94#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
95
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
97#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
98#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hamman9e3ed392007-12-13 06:45:14 -060099
Timur Tabie46fedf2011-08-04 18:03:41 -0500100#define CONFIG_SYS_CCSRBAR 0xe0000000
101#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Joe Hamman9e3ed392007-12-13 06:45:14 -0600102
Kumar Gala33b90792008-08-26 23:15:28 -0500103/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700104#define CONFIG_SYS_FSL_DDR2
Kumar Gala33b90792008-08-26 23:15:28 -0500105#undef CONFIG_FSL_DDR_INTERACTIVE
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500106#undef CONFIG_DDR_ECC /* only for ECC DDR module */
107/*
108 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
109 * to collide, meaning you couldn't reliably read either. So
110 * physically remove the LBC PC100 SDRAM module from the board
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500111 * before enabling the two SPD options below, or check that you
112 * have the hardware fix on your board via "i2c probe" and looking
113 * for a device at 0x53.
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500114 */
Kumar Gala33b90792008-08-26 23:15:28 -0500115#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
116#undef CONFIG_DDR_SPD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600117
Kumar Gala33b90792008-08-26 23:15:28 -0500118#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
119#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
122#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala33b90792008-08-26 23:15:28 -0500123#define CONFIG_VERY_BIG_RAM
124
125#define CONFIG_NUM_DDR_CONTROLLERS 1
126#define CONFIG_DIMM_SLOTS_PER_CTLR 1
127#define CONFIG_CHIP_SELECTS_PER_CTRL 2
128
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500129/*
130 * The hardware fix for the I2C address collision puts the DDR
131 * SPD at 0x53, but if we are running on an older board w/o the
132 * fix, it will still be at 0x51. We check 0x53 1st.
133 */
Kumar Gala33b90792008-08-26 23:15:28 -0500134#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500135#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600136
137/*
138 * Make sure required options are set
139 */
140#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Paul Gortmaker2a6b3b72011-12-30 23:53:11 -0500142 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600143#endif
144
145#undef CONFIG_CLOCKS_IN_MHZ
146
147/*
148 * FLASH on the Local Bus
149 * Two banks, one 8MB the other 64MB, using the CFI driver.
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500150 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
151 * CS0 the 8MB boot flash, and CS6 the 64MB flash.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600152 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500153 * Default:
154 * ec00_0000 efff_ffff 64MB SODIMM
155 * ff80_0000 ffff_ffff 8MB soldered flash
156 *
157 * Alternate:
158 * ef80_0000 efff_ffff 8MB soldered flash
159 * fc00_0000 ffff_ffff 64MB SODIMM
160 *
161 * BR0_8M:
Joe Hamman9e3ed392007-12-13 06:45:14 -0600162 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
163 * Port Size = 8 bits = BRx[19:20] = 01
164 * Use GPCM = BRx[24:26] = 000
165 * Valid = BRx[31] = 1
166 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500167 * BR0_64M:
168 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600169 * Port Size = 32 bits = BRx[19:20] = 11
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500170 *
171 * 0 4 8 12 16 20 24 28
172 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
173 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
174 */
175#define CONFIG_SYS_BR0_8M 0xff800801
176#define CONFIG_SYS_BR0_64M 0xfc001801
177
178/*
179 * BR6_8M:
180 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
181 * Port Size = 8 bits = BRx[19:20] = 01
Joe Hamman9e3ed392007-12-13 06:45:14 -0600182 * Use GPCM = BRx[24:26] = 000
183 * Valid = BRx[31] = 1
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500184
185 * BR6_64M:
186 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
187 * Port Size = 32 bits = BRx[19:20] = 11
Joe Hamman9e3ed392007-12-13 06:45:14 -0600188 *
189 * 0 4 8 12 16 20 24 28
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500190 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
191 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
192 */
193#define CONFIG_SYS_BR6_8M 0xef800801
194#define CONFIG_SYS_BR6_64M 0xec001801
195
196/*
197 * OR0_8M:
Joe Hamman9e3ed392007-12-13 06:45:14 -0600198 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
199 * XAM = OR0[17:18] = 11
200 * CSNT = OR0[20] = 1
201 * ACS = half cycle delay = OR0[21:22] = 11
202 * SCY = 6 = OR0[24:27] = 0110
203 * TRLX = use relaxed timing = OR0[29] = 1
204 * EAD = use external address latch delay = OR0[31] = 1
205 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500206 * OR0_64M:
207 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600208 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500209 *
210 * 0 4 8 12 16 20 24 28
211 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
212 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
213 */
214#define CONFIG_SYS_OR0_8M 0xff806e65
215#define CONFIG_SYS_OR0_64M 0xfc006e65
216
217/*
218 * OR6_8M:
219 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600220 * XAM = OR6[17:18] = 11
221 * CSNT = OR6[20] = 1
222 * ACS = half cycle delay = OR6[21:22] = 11
223 * SCY = 6 = OR6[24:27] = 0110
224 * TRLX = use relaxed timing = OR6[29] = 1
225 * EAD = use external address latch delay = OR6[31] = 1
226 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500227 * OR6_64M:
228 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
229 *
Joe Hamman9e3ed392007-12-13 06:45:14 -0600230 * 0 4 8 12 16 20 24 28
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500231 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
232 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
Joe Hamman9e3ed392007-12-13 06:45:14 -0600233 */
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500234#define CONFIG_SYS_OR6_8M 0xff806e65
235#define CONFIG_SYS_OR6_64M 0xfc006e65
Joe Hamman9e3ed392007-12-13 06:45:14 -0600236
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500237#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
Paul Gortmaker3fd673c2011-12-30 23:53:07 -0500239#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600240
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500241#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
242#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
Joe Hamman9e3ed392007-12-13 06:45:14 -0600243
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500244#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
245#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
246#else /* JP12 in alternate position */
247#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
248#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600249
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500250#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
251#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
252
253#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
254#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
255#endif
256
257#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400258#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
259 CONFIG_SYS_ALT_FLASH}
260#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
261#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#undef CONFIG_SYS_FLASH_CHECKSUM
263#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
264#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600265
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200266#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600267
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200268#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_FLASH_CFI
270#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600271
272/* CS5 = Local bus peripherals controlled by the EPLD */
273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_BR5_PRELIM 0xf8000801
275#define CONFIG_SYS_OR5_PRELIM 0xff006e65
276#define CONFIG_SYS_EPLD_BASE 0xf8000000
277#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
278#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
279#define CONFIG_SYS_BD_REV 0xf8300000
280#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600281
282/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400283 * SDRAM on the Local Bus (CS3 and CS4)
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500284 * Note that most boards have a hardware errata where both the
285 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
286 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500287 * A hardware workaround is also available, see README.sbc8548 file.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400290#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600291
292/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400293 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600295 *
296 * For BR3, need:
297 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
298 * port-size = 32-bits = BR2[19:20] = 11
299 * no parity checking = BR2[21:22] = 00
300 * SDRAM for MSEL = BR2[24:26] = 011
301 * Valid = BR[31] = 1
302 *
303 * 0 4 8 12 16 20 24 28
304 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
305 *
306 */
307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_BR3_PRELIM 0xf0001861
Joe Hamman9e3ed392007-12-13 06:45:14 -0600309
310/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400311 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600312 *
313 * For OR3, need:
314 * 64MB mask for AM, OR3[0:7] = 1111 1100
315 * XAM, OR3[17:18] = 11
316 * 10 columns OR3[19-21] = 011
317 * 12 rows OR3[23-25] = 011
318 * EAD set for extra time OR[31] = 0
319 *
320 * 0 4 8 12 16 20 24 28
321 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
322 */
323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600325
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400326/*
327 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
328 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
329 *
330 * For BR4, need:
331 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
332 * port-size = 32-bits = BR2[19:20] = 11
333 * no parity checking = BR2[21:22] = 00
334 * SDRAM for MSEL = BR2[24:26] = 011
335 * Valid = BR[31] = 1
336 *
337 * 0 4 8 12 16 20 24 28
338 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
339 *
340 */
341
342#define CONFIG_SYS_BR4_PRELIM 0xf4001861
343
344/*
345 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
346 *
347 * For OR4, need:
348 * 64MB mask for AM, OR3[0:7] = 1111 1100
349 * XAM, OR3[17:18] = 11
350 * 10 columns OR3[19-21] = 011
351 * 12 rows OR3[23-25] = 011
352 * EAD set for extra time OR[31] = 0
353 *
354 * 0 4 8 12 16 20 24 28
355 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
356 */
357
358#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
361#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
362#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
363#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600364
365/*
Joe Hamman9e3ed392007-12-13 06:45:14 -0600366 * Common settings for all Local Bus SDRAM commands.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600367 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500368#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500369 | LSDMR_BSMA1516 \
370 | LSDMR_PRETOACT3 \
371 | LSDMR_ACTTORW3 \
372 | LSDMR_BUFCMD \
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500373 | LSDMR_BL8 \
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500374 | LSDMR_WRC2 \
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500375 | LSDMR_CL3 \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600376 )
377
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500378#define CONFIG_SYS_LBC_LSDMR_PCHALL \
379 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
380#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
381 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
382#define CONFIG_SYS_LBC_LSDMR_MRW \
383 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
384#define CONFIG_SYS_LBC_LSDMR_RFEN \
385 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_INIT_RAM_LOCK 1
388#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200389#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600392
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200393#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hamman9e3ed392007-12-13 06:45:14 -0600395
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400396/*
397 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200398 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400399 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200400 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400401 * thing for MONITOR_LEN in both cases.
402 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200403#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500404#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600405
406/* Serial Port */
407#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_NS16550
409#define CONFIG_SYS_NS16550_SERIAL
410#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Gortmaker2738bc82009-09-20 20:36:06 -0400411#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600414 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
417#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600418
419/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_HUSH_PARSER
Joe Hamman9e3ed392007-12-13 06:45:14 -0600421
422/* pass open firmware flat tree */
423#define CONFIG_OF_LIBFDT 1
424#define CONFIG_OF_BOARD_SETUP 1
425#define CONFIG_OF_STDOUT_VIA_ALIAS 1
426
427/*
428 * I2C
429 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200430#define CONFIG_SYS_I2C
431#define CONFIG_SYS_I2C_FSL
432#define CONFIG_SYS_FSL_I2C_SPEED 400000
433#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
434#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
Joe Hamman9e3ed392007-12-13 06:45:14 -0600436
437/*
438 * General PCI
439 * Memory space is mapped 1-1, but I/O space must start from 0.
440 */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400441#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600443
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400444#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
445#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
446#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400448#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
449#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
450#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
451#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600452
453#ifdef CONFIG_PCIE1
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400454#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
455#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
456#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400458#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
459#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
460#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
461#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600462#endif
463
464#ifdef CONFIG_RIO
465/*
466 * RapidIO MMU
467 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
469#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600470#endif
471
Joe Hamman9e3ed392007-12-13 06:45:14 -0600472#if defined(CONFIG_PCI)
473
Joe Hamman9e3ed392007-12-13 06:45:14 -0600474#define CONFIG_PCI_PNP /* do pci plug-and-play */
475
476#undef CONFIG_EEPRO100
477#undef CONFIG_TULIP
478
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400479#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600480
Joe Hamman9e3ed392007-12-13 06:45:14 -0600481#endif /* CONFIG_PCI */
482
483
484#if defined(CONFIG_TSEC_ENET)
485
Joe Hamman9e3ed392007-12-13 06:45:14 -0600486#define CONFIG_MII 1 /* MII PHY management */
487#define CONFIG_TSEC1 1
488#define CONFIG_TSEC1_NAME "eTSEC0"
489#define CONFIG_TSEC2 1
490#define CONFIG_TSEC2_NAME "eTSEC1"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600491#undef CONFIG_MPC85XX_FEC
492
Paul Gortmaker58da8892008-12-11 15:47:50 -0500493#define TSEC1_PHY_ADDR 0x19
494#define TSEC2_PHY_ADDR 0x1a
Joe Hamman9e3ed392007-12-13 06:45:14 -0600495
496#define TSEC1_PHYIDX 0
497#define TSEC2_PHYIDX 0
Paul Gortmakerbd931052008-12-11 15:47:49 -0500498
Joe Hamman9e3ed392007-12-13 06:45:14 -0600499#define TSEC1_FLAGS TSEC_GIGABIT
500#define TSEC2_FLAGS TSEC_GIGABIT
Joe Hamman9e3ed392007-12-13 06:45:14 -0600501
502/* Options are: eTSEC[0-3] */
503#define CONFIG_ETHPRIME "eTSEC0"
504#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
505#endif /* CONFIG_TSEC_ENET */
506
507/*
508 * Environment
509 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200510#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200511#define CONFIG_ENV_SIZE 0x2000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200512#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400513#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
514#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200515#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400516#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
517#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
518#else
519#warning undefined environment size/location.
520#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -0600521
522#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600524
525/*
526 * BOOTP options
527 */
528#define CONFIG_BOOTP_BOOTFILESIZE
529#define CONFIG_BOOTP_BOOTPATH
530#define CONFIG_BOOTP_GATEWAY
531#define CONFIG_BOOTP_HOSTNAME
532
533
534/*
535 * Command line configuration.
536 */
537#include <config_cmd_default.h>
538
539#define CONFIG_CMD_PING
540#define CONFIG_CMD_I2C
541#define CONFIG_CMD_MII
542#define CONFIG_CMD_ELF
Becky Bruce199e2622010-06-17 11:37:25 -0500543#define CONFIG_CMD_REGINFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600544
545#if defined(CONFIG_PCI)
546 #define CONFIG_CMD_PCI
547#endif
548
549
550#undef CONFIG_WATCHDOG /* watchdog disabled */
551
552/*
553 * Miscellaneous configurable options
554 */
Paul Gortmakerad22f922008-12-11 15:47:51 -0500555#define CONFIG_CMDLINE_EDITING /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500556#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_LONGHELP /* undef to save memory */
558#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600559#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600561#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600563#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
565#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
566#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600567
568/*
569 * For booting Linux, the board info and command line data
570 * have to be in the first 8 MB of memory, since this is
571 * the maximum mapped by the Linux kernel during initialization.
572 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600574
Joe Hamman9e3ed392007-12-13 06:45:14 -0600575#if defined(CONFIG_CMD_KGDB)
576#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600577#endif
578
579/*
580 * Environment Configuration
581 */
582
583/* The mac addresses for all ethernet interface */
584#if defined(CONFIG_TSEC_ENET)
585#define CONFIG_HAS_ETH0
586#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
587#define CONFIG_HAS_ETH1
588#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600589#endif
590
591#define CONFIG_IPADDR 192.168.0.55
592
593#define CONFIG_HOSTNAME sbc8548
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000594#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000595#define CONFIG_BOOTFILE "/uImage"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600596#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
597
598#define CONFIG_SERVERIP 192.168.0.2
599#define CONFIG_GATEWAYIP 192.168.0.1
600#define CONFIG_NETMASK 255.255.255.0
601
602#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
603
604#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
605#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
606
607#define CONFIG_BAUDRATE 115200
608
609#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200610"netdev=eth0\0" \
611"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
612"tftpflash=tftpboot $loadaddr $uboot; " \
613 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
614 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
615 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
616 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
617 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
618"consoledev=ttyS0\0" \
619"ramdiskaddr=2000000\0" \
620"ramdiskfile=uRamdisk\0" \
621"fdtaddr=c00000\0" \
622"fdtfile=sbc8548.dtb\0"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600623
624#define CONFIG_NFSBOOTCOMMAND \
625 "setenv bootargs root=/dev/nfs rw " \
626 "nfsroot=$serverip:$rootpath " \
627 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
628 "console=$consoledev,$baudrate $othbootargs;" \
629 "tftp $loadaddr $bootfile;" \
630 "tftp $fdtaddr $fdtfile;" \
631 "bootm $loadaddr - $fdtaddr"
632
633
634#define CONFIG_RAMBOOTCOMMAND \
635 "setenv bootargs root=/dev/ram rw " \
636 "console=$consoledev,$baudrate $othbootargs;" \
637 "tftp $ramdiskaddr $ramdiskfile;" \
638 "tftp $loadaddr $bootfile;" \
639 "tftp $fdtaddr $fdtfile;" \
640 "bootm $loadaddr $ramdiskaddr $fdtaddr"
641
642#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
643
644#endif /* __CONFIG_H */