blob: 63ea24edea06c70123fed5953c7bb1088005700b [file] [log] [blame]
wdenkcd0a9de2004-02-23 20:48:38 +00001/*
2 * (C) Copyright 2004
3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
wdenk4d13cba2004-03-14 14:09:05 +000039#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
wdenkcd0a9de2004-02-23 20:48:38 +000040#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
41#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
42
43/*
44 * OS Bootstrap configuration
45 *
46 */
47
48#if 0
49#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
50#else
51#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
52#endif
53
54#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
55
56#if 1
57#undef CONFIG_BOOTARGS
58#define CONFIG_BOOTCOMMAND \
59 "setenv bootargs console=ttyS0,38400 debug " \
60 "root=/dev/ram rw ramdisk_size=4096 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkcd0a9de2004-02-23 20:48:38 +000062 "bootm fe000000 fe100000"
63#endif
64
65#if 0
66#undef CONFIG_BOOTARGS
67#define CONFIG_BOOTCOMMAND \
68 "bootp; " \
69 "setenv bootargs console=ttyS0,38400 debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010070 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkcd0a9de2004-02-23 20:48:38 +000072 "bootm"
73#endif
74
75/*
76 * BOOTP/DHCP protocol configuration
77 *
78 */
79#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
80 CONFIG_BOOTP_DNS2 | \
81 CONFIG_BOOTP_BOOTFILESIZE )
wdenkcd0a9de2004-02-23 20:48:38 +000082
Jon Loeliger37e4f242007-07-04 22:31:56 -050083
84/*
85 * Command line configuration.
86 */
87#include <config_cmd_default.h>
88
89#define CONFIG_CMD_ASKENV
90#define CONFIG_CMD_BEDBUG
91#define CONFIG_CMD_ELF
92#define CONFIG_CMD_IRQ
93#define CONFIG_CMD_I2C
94#define CONFIG_CMD_PCI
95#define CONFIG_CMD_DATE
96#define CONFIG_CMD_MII
97#define CONFIG_CMD_PING
98#define CONFIG_CMD_DHCP
99
wdenkcd0a9de2004-02-23 20:48:38 +0000100
101/*
102 * Serial download configuration
103 *
104 */
105#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
106#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
107
108/*
109 * KGDB Configuration
110 *
111 */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500112#if defined(CONFIG_CMD_KGDB)
wdenkcd0a9de2004-02-23 20:48:38 +0000113#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
114#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
115#endif
116
117/*
118 * Miscellaneous configurable options
119 *
120 */
121#undef CFG_HUSH_PARSER /* use "hush" command parser */
122#ifdef CFG_HUSH_PARSER
123#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
124#endif
125
126#define CFG_LONGHELP /* undef to save memory */
127#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500128#if defined(CONFIG_CMD_KGDB)
wdenkcd0a9de2004-02-23 20:48:38 +0000129#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
130#else
131#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
132#endif
133#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
134#define CFG_MAXARGS 16 /* max number of command args */
135#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
136
137#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
138#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
139
140#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
141#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
142#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
143#define CFG_LOAD_ADDR 0x100000 /* default load address */
144
145/*
146 * For booting Linux, the board info and command line data
147 * have to be in the first 8 MB of memory, since this is
148 * the maximum mapped by the Linux kernel during initialization.
149 */
150#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
151
152/*
153 * watchdog configuration
154 *
155 */
156#undef CONFIG_WATCHDOG /* watchdog disabled */
157
158/*
159 * UART configuration
160 *
161 */
162#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
163#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
164#undef CFG_BASE_BAUD
165#define CONFIG_BAUDRATE 38400 /* Default baud rate */
166#define CFG_BAUDRATE_TABLE \
167 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
168
169/*
170 * I2C configuration
171 *
172 */
173#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
174#define CFG_I2C_SPEED 100000 /* I2C speed */
175#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
176
177/*
178 * MII PHY configuration
179 *
180 */
181#define CONFIG_MII 1 /* MII PHY management */
182#define CONFIG_PHY_ADDR 0 /* PHY address */
183#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
184 /* 32usec min. for LXT971A */
185#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
186
187/*
188 * RTC configuration
189 *
190 * Note that DS1307 RTC is limited to 100Khz I2C bus.
191 *
192 */
193#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
194
195/*
196 * PCI stuff
197 *
198 */
199#define CONFIG_PCI /* include pci support */
200#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
201#define PCI_HOST_FORCE 1 /* configure as pci host */
202#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
203
204#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
205#define CONFIG_PCI_PNP /* do pci plug-and-play */
206 /* resource configuration */
207#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
208#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
209
210#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
211#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
212#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
213#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
214#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
215#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
216#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
217#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
218
219/*
220 * IDE stuff
221 *
222 */
223#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
224#undef CONFIG_IDE_LED /* no led for ide supported */
225#undef CONFIG_IDE_RESET /* no reset for ide supported */
226
227/*
228 * Environment configuration
229 *
230 */
231#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
232#undef CFG_ENV_IS_IN_NVRAM
233#undef CFG_ENV_IS_IN_EEPROM
234
235/*
236 * General Memory organization
237 *
238 * Start addresses for the final memory configuration
239 * (Set up by the startup code)
240 * Please note that CFG_SDRAM_BASE _must_ start at 0
241 */
242#define CFG_SDRAM_BASE 0x00000000
243#define CFG_FLASH_BASE 0xFE000000
244#define CFG_FLASH_SIZE 0x02000000
245#define CFG_MONITOR_BASE TEXT_BASE
246#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
247#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
248
249#if CFG_MONITOR_BASE < CFG_FLASH_BASE
250#define CFG_RAMSTART
251#endif
252
253#if defined(CFG_ENV_IS_IN_FLASH)
254#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
255#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
256#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */
257#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
258#endif
259
260/*
261 * FLASH Device configuration
262 *
263 */
264#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
265#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
266#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
267#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
268#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
269#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
270#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
271#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
272
273/*
274 * On Chip Memory location/size
275 *
276 */
277#define CFG_OCM_DATA_ADDR 0xF8000000
278#define CFG_OCM_DATA_SIZE 0x1000
279
280/*
281 * Global info and initial stack
282 *
283 */
284#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
285#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
286#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
287#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
288#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
289
290/*
291 * Cache configuration
292 *
293 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200294#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenkcd0a9de2004-02-23 20:48:38 +0000295 /* have only 8kB, 16kB is save here */
296#define CFG_CACHELINE_SIZE 32
297
298/*
299 * Miscellaneous board specific definitions
300 *
301 */
302#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
wdenkeeb1b772004-03-23 22:53:55 +0000303#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
wdenkcd0a9de2004-02-23 20:48:38 +0000304
305/*
306 * Internal Definitions
307 *
308 * Boot Flags
309 *
310 */
311#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
312#define BOOTFLAG_WARM 0x02 /* Software reboot */
313
314#endif /* __CONFIG_H */